u-boot/include/configs/db12x.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros AR934x based devices
   6  *
   7  * Reference designs: AP123, MI124, DB120
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _DB12X_H
  13 #define _DB12X_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
  25     defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
  26
  27         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
  28                                                 GPIO14 | GPIO15
  29         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO21 | GPIO22 |\
  30                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  31         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
  32         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO21 | GPIO22 |\
  33                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  34
  35 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
  36
  37         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO13 | GPIO14 |\
  38                                                 GPIO15 | GPIO18 | GPIO19 |\
  39                                                 GPIO20 | GPIO21 | GPIO22
  40         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO12 |\
  41                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  42         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
  43         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO12 |\
  44                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  45
  46 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
  47
  48         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
  49                                                 GPIO14 | GPIO15 | GPIO18 |\
  50                                                 GPIO19 | GPIO20 | GPIO21
  51         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO4 |\
  52                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  53         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
  54         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4 |\
  55                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  56
  57 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
  58
  59         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO12 | GPIO13 | GPIO14 |\
  60                                                 GPIO15 | GPIO18 | GPIO19 |\
  61                                                 GPIO20 | GPIO21
  62         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  63         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
  64         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  65
  66 #elif defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
  67       defined(CONFIG_FOR_TPLINK_WA830RE_V2)
  68
  69         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14 | GPIO15 |\
  70                                                 GPIO18
  71         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  72         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
  73         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  74
  75 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
  76
  77         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO1  | GPIO2  |\
  78                                                 GPIO3 | GPIO13 | GPIO19 |\
  79                                                 GPIO20
  80         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  81         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
  82         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  83
  84 #endif
  85
  86 /*
  87  * ================
  88  * Default bootargs
  89  * ================
  90  */
  91 #if defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
  92     defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
  93     defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
  94
  95         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
  96                                 "rootfstype=squashfs init=/sbin/init "\
  97                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(art)"
  98
  99 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 100
 101         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 102                                 "rootfstype=squashfs,jffs2 init=/sbin/init "\
 103                                 "mtdparts=ath-nor0:64k(u-boot),64k(u-boot-env),6528k(rootfs),1408K(uImage)"\
 104                                 ",7936k@0x20000(firmware),64k(NVRAM),64k(ART),8128k@0x00000(firmware2)"
 105
 106 #else
 107
 108         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 109                                 "rootfstype=squashfs init=/sbin/init "\
 110                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 111
 112 #endif
 113
 114 /*
 115  * =============================
 116  * Load address and boot command
 117  * =============================
 118  */
 119 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 120         #define CFG_LOAD_ADDR           0x9F680000
 121 #else
 122         #define CFG_LOAD_ADDR           0x9F020000
 123 #endif
 124
 125 #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 126
 127 /*
 128  * =========================
 129  * Environment configuration
 130  * =========================
 131  */
 132 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 133         #define CFG_ENV_ADDR            0x9F020000
 134         #define CFG_ENV_SIZE            0xFC00
 135         #define CFG_ENV_SECT_SIZE       0x10000
 136 #else
 137         #define CFG_ENV_ADDR            0x9F01EC00
 138         #define CFG_ENV_SIZE            0x1000
 139         #define CFG_ENV_SECT_SIZE       0x10000
 140 #endif
 141
 142 /*
 143  * ===========================
 144  * List of available baudrates
 145  * ===========================
 146  */
 147 #define CFG_BAUDRATE_TABLE      \
 148                 { 600,    1200,   2400,    4800,    9600,    14400, \
 149                   19200,  28800,  38400,   56000,   57600,   115200 }
 150
 151 /*
 152  * ==================================================
 153  * MAC address/es, model and WPS pin offsets in FLASH
 154  * ==================================================
 155  */
 156 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 157         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 158         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 159         #define OFFSET_MAC_ADDRESS              0x000000
 160 #else
 161         #define OFFSET_MAC_DATA_BLOCK           0x010000
 162         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 163         #define OFFSET_MAC_ADDRESS              0x00FC00
 164         #define OFFSET_ROUTER_MODEL             0x00FD00
 165         #define OFFSET_PIN_NUMBER               0x00FE00
 166 #endif
 167
 168 /*
 169  * =========================
 170  * Custom changes per device
 171  * =========================
 172  */
 173
 174 /*
 175  * YunCore CPE870 is limited to 64 KB only,
 176  * disable some commands
 177  */
 178 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 179         #undef CONFIG_CMD_DHCP
 180         #undef CONFIG_CMD_LOADB
 181         #undef CONFIG_CMD_SNTP
 182         #undef CONFIG_CMD_IMI
 183 #endif
 184
 185 /*
 186  * ===========================
 187  * HTTP recovery configuration
 188  * ===========================
 189  */
 190 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 191         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_FLASH_BASE + 0x20000
 192 #else
 193         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 194 #endif
 195
 196 /* Firmware size limit */
 197 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 198         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 199 #else
 200         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 201 #endif
 202
 203 /*
 204  * ========================
 205  * PLL/Clocks configuration
 206  * ========================
 207  */
 208 #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
 209
 210 #if defined(CONFIG_FOR_TPLINK_MR3420_V2)  ||\
 211     defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
 212     defined(CONFIG_FOR_TPLINK_WA830RE_V2) ||\
 213     defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
 214     defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
 215     defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
 216     defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
 217     defined(CONFIG_FOR_YUNCORE_CPE870)
 218
 219         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 220         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 221
 222 #endif
 223
 224 /*
 225  * ==================================
 226  * For upgrade scripts in environment
 227  * ==================================
 228  */
 229 #if !defined(CONFIG_FOR_YUNCORE_CPE870)
 230         #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
 231 #endif
 232
 233 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 234         #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F020000
 235 #endif
 236
 237 /*
 238  * ===================
 239  * Other configuration
 240  * ===================
 241  */
 242
 243 /* Cache lock for stack */
 244 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd007000
 245
 246 #endif /* _DB12X_H */