2 * This file contains the configuration parameters for the DB12x (AR9344) board.
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8 #include <configs/ar7240.h>
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12 * FLASH and environment organization
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14 #define CFG_MAX_FLASH_BANKS 1
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15 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
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17 * We boot from this flash
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19 #define CFG_FLASH_BASE 0x9F000000
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20 #ifdef COMPRESSED_UBOOT
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21 #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
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22 #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
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26 * The following #defines are needed to get flash environment right
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28 #define CFG_MONITOR_BASE TEXT_BASE
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29 #define CFG_MONITOR_LEN (192 << 10)
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34 #undef CONFIG_BOOTARGS
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35 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || defined (CONFIG_FOR_TPLINK_WDR3500_V1)
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36 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
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38 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
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42 * Other env default values
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44 #undef CONFIG_BOOTFILE
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45 #define CONFIG_BOOTFILE "firmware.bin"
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47 #undef CONFIG_LOADADDR
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48 #define CONFIG_LOADADDR 0x80800000
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50 #define CFG_LOAD_ADDR 0x9F020000
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51 #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
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54 #define CONFIG_IPADDR 192.168.1.1
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55 #define CONFIG_SERVERIP 192.168.1.2
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60 // CPU-RAM-AHB frequency setting
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61 #if !defined(CONFIG_AP123)
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62 #define CFG_PLL_FREQ CFG_PLL_560_480_240
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63 #define CFG_HZ_FALLBACK (560000000LU/2)
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65 #define CFG_PLL_FREQ CFG_PLL_533_400_200
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66 #define CFG_HZ_FALLBACK (535000000LU/2)
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69 #define CFG_HZ bd->bi_cfg_hz
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70 #define AR7240_SPI_CONTROL 0x43
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71 #define AR7240_SPI_CONTROL_DEFAULT AR7240_SPI_CONTROL
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73 * MIPS32 24K Processor Core Family Software User's Manual
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75 * 6.2.9 Count Register (CP0 Register 9, Select 0)
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76 * The Count register acts as a timer, incrementing at a constant
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77 * rate, whether or not an instruction is executed, retired, or
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78 * any forward progress is made through the pipeline. The counter
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79 * increments every other clock, if the DC bit in the Cause register
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82 * Since the count is incremented every other tick, divide by 2
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83 * XXX derive this from CFG_PLL_FREQ
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87 * Cache lock for stack
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89 #define CFG_INIT_SP_OFFSET 0x1000
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92 * Address and size of Primary Environment Sector
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94 #undef CFG_ENV_IS_IN_FLASH
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95 #define CFG_ENV_IS_NOWHERE 1
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97 #define CFG_ENV_ADDR 0x9F040000
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98 #define CFG_ENV_SIZE 0x10000
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101 * Available commands
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103 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
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115 // Enable NetConsole and custom NetConsole port
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116 #define CONFIG_NETCONSOLE
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117 #define CONFIG_NETCONSOLE_PORT 6666
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119 /* DDR settings for WASP */
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120 #define CFG_DDR_REFRESH_VAL 0x4270
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121 #define CFG_DDR_CONFIG_VAL 0xc7bc8cd0
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122 #define CFG_DDR_MODE_VAL_INIT 0x133
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123 #define CFG_DDR_EXT_MODE_VAL 0x0
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124 #define CFG_DDR_MODE_VAL 0x33
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125 #define CFG_DDR_TRTW_VAL 0x1f
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126 #define CFG_DDR_TWTR_VAL 0x1e
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127 #define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8
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129 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
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130 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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132 #if DDR2_32BIT_SUPPORT
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133 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32
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135 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16
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138 #define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL 0xffff
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139 #define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL 0xffffffff
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141 /* DDR2 Init values */
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142 #define CFG_DDR2_EXT_MODE_VAL 0x402
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144 #define CONFIG_NET_MULTI
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146 #ifdef CFG_ATHRS27_PHY
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147 /* use eth1(LAN) as the net interface */
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148 #define CONFIG_AG7240_SPEPHY
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151 #define CONFIG_PCI 1
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154 * Web Failsafe configuration
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156 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
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157 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
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159 // Firmware partition offset
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160 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
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162 // U-Boot partition size
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163 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024)
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165 // ART partition size
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166 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
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168 // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
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169 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
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170 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
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172 // progress state info
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173 #define WEBFAILSAFE_PROGRESS_START 0
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174 #define WEBFAILSAFE_PROGRESS_TIMEOUT 1
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175 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
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176 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
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177 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
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180 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
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181 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
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182 #define WEBFAILSAFE_UPGRADE_TYPE_ART 2
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184 /*-----------------------------------------------------------------------*/
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186 /* For Merlin, both PCI, PCI-E interfaces are valid */
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187 #define AR7240_ART_PCICFG_OFFSET 12
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189 #define WLANCAL 0x9fff1000
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190 #define CFG_MII0_RMII 1
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191 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
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194 #define milisecdelay(_x) udelay((_x) * 1000)
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196 /* MAC address, model and PIN number offsets in FLASH */
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197 #define OFFSET_MAC_DATA_BLOCK 0x010000
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198 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
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199 #define OFFSET_MAC_ADDRESS 0x00FC00
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200 #define OFFSET_ROUTER_MODEL 0x00FD00
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201 #define OFFSET_PIN_NUMBER 0x00FE00
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203 #include <cmd_confdefs.h>
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205 #endif /* __CONFIG_H */
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