2 * This file contains the configuration parameters for the DB12x (AR9344) board.
8 #include <configs/ar7240.h>
10 #include <soc/soc_common.h>
15 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
17 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15)
20 #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
21 #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
24 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
26 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
28 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
29 GPIO19 | GPIO20 | GPIO21 | GPIO22)
32 #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
33 #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
36 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
38 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
40 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 |\
41 GPIO18 | GPIO19 | GPIO20 | GPIO21)
44 #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
45 #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
48 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
50 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
52 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO12 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
53 GPIO19 | GPIO20 | GPIO21)
56 #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
57 #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
60 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
62 #elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
64 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO13 | GPIO14 | GPIO15 | GPIO18)
67 #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
68 #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
71 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
76 * FLASH and environment organization
78 #define CFG_MAX_FLASH_BANKS 1
79 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
81 * We boot from this flash
83 #define CFG_FLASH_BASE 0x9F000000
84 #ifdef COMPRESSED_UBOOT
85 #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
86 #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
90 * The following #defines are needed to get flash environment right
92 #define CFG_MONITOR_BASE TEXT_BASE
93 #define CFG_MONITOR_LEN (192 << 10)
98 #undef CONFIG_BOOTARGS
99 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || defined (CONFIG_FOR_TPLINK_WDR3500_V1)
100 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
102 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
106 * Other env default values
108 #undef CONFIG_BOOTFILE
109 #define CONFIG_BOOTFILE "firmware.bin"
111 #undef CONFIG_LOADADDR
112 #define CONFIG_LOADADDR 0x80800000
114 #define CFG_LOAD_ADDR 0x9F020000
115 #define UPDATE_SCRIPT_FW_ADDR "0x9F020000"
116 #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
119 #define CONFIG_IPADDR 192.168.1.1
120 #define CONFIG_SERVERIP 192.168.1.2
123 * PLL/Clocks configuration
128 #define CFG_HZ bd->bi_cfg_hz
130 /* For now, use some safe clocks for all AR934x */
131 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
135 * For PLL/clocks recovery use reset button by default
137 #ifdef CONFIG_GPIO_RESET_BTN
138 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN
141 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
142 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
146 * MIPS32 24K Processor Core Family Software User's Manual
148 * 6.2.9 Count Register (CP0 Register 9, Select 0)
149 * The Count register acts as a timer, incrementing at a constant
150 * rate, whether or not an instruction is executed, retired, or
151 * any forward progress is made through the pipeline. The counter
152 * increments every other clock, if the DC bit in the Cause register
155 * Since the count is incremented every other tick, divide by 2
156 * XXX derive this from CFG_PLL_FREQ
160 * Cache lock for stack
162 #define CFG_INIT_SP_OFFSET 0x1000
163 #define CONFIG_INIT_SRAM_SP_OFFSET 0xbd007000
166 * Address and size of Primary Environment Sector
168 #define CFG_ENV_IS_IN_FLASH 1
169 #undef CFG_ENV_IS_NOWHERE
171 #define CFG_ENV_ADDR 0x9F01EC00
172 #define CFG_ENV_SIZE 0x1000
173 #define CFG_ENV_SECT_SIZE 0x10000
178 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
192 // Enable NetConsole and custom NetConsole port
193 #define CONFIG_NETCONSOLE
194 #define CONFIG_NETCONSOLE_PORT 6666
196 #define CONFIG_NET_MULTI
198 #ifdef CFG_ATHRS27_PHY
199 /* use eth1(LAN) as the net interface */
200 #define CONFIG_AG7240_SPEPHY
206 * Web Failsafe configuration
208 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
209 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
211 // Firmware partition offset
212 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
214 // U-Boot partition size
215 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
217 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
218 #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00"
219 #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000"
221 // ART partition size
222 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
224 // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
225 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
226 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
228 // progress state info
229 #define WEBFAILSAFE_PROGRESS_START 0
230 #define WEBFAILSAFE_PROGRESS_TIMEOUT 1
231 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
232 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
233 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
236 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
237 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
238 #define WEBFAILSAFE_UPGRADE_TYPE_ART 2
240 /*-----------------------------------------------------------------------*/
243 * Additional environment variables for simple upgrades
245 #define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \
246 "uboot_name=uboot.bin\0" \
247 "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
248 "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
250 "if ping $serverip; then " \
251 "mw.b $loadaddr 0xFF $uboot_backup_size && " \
252 "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
253 "tftp $loadaddr $uboot_name && " \
254 "if itest.l $filesize <= $uboot_size; then " \
255 "erase $uboot_addr +$uboot_backup_size && " \
256 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
259 "echo ERROR! Wrong file size!; " \
262 "echo ERROR! Server not reachable!; " \
264 "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \
265 "firmware_name=firmware.bin\0" \
267 "if ping $serverip; then " \
268 "tftp $loadaddr $firmware_name && " \
269 "erase $firmware_addr +$filesize && " \
270 "cp.b $loadaddr $firmware_addr $filesize && " \
273 "echo ERROR! Server not reachable!; " \
277 /* For Merlin, both PCI, PCI-E interfaces are valid */
278 #define AR7240_ART_PCICFG_OFFSET 12
280 #define WLANCAL 0x9fff1000
281 #define CFG_MII0_RMII 1
282 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
286 /* MAC address, model and PIN number offsets in FLASH */
287 #define OFFSET_MAC_DATA_BLOCK 0x010000
288 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
289 #define OFFSET_MAC_ADDRESS 0x00FC00
290 #define OFFSET_ROUTER_MODEL 0x00FD00
291 #define OFFSET_PIN_NUMBER 0x00FE00
294 * PLL and clocks configurations from FLASH
296 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || \
297 defined(CONFIG_FOR_TPLINK_WDR3500_V1) || \
298 defined(CONFIG_FOR_TPLINK_MR3420_V2) || \
299 defined(CONFIG_FOR_TPLINK_WR841N_V8) || \
300 defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
302 * All TP-Link routers have a lot of unused space
303 * in FLASH, in second 64 KiB block.
304 * We will store there PLL and CLOCK
305 * registers configuration.
307 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000
308 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
312 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
313 /* Use last 32 bytes */
314 #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \
315 CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
319 #include <cmd_confdefs.h>
321 #endif /* __CONFIG_H */