2 * This file contains the configuration parameters for the dbau1x00 board.
8 #ifndef CONFIG_BOOTDELAY
9 #define CONFIG_BOOTDELAY 1 /* autoboot after x seconds */
12 #define CONFIG_MENUPROMPT "Hit any key to stop autobooting: %2d "
13 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in:\t%d s (type 'tpl' to run U-Boot console)\n\n"
14 #define CONFIG_AUTOBOOT_STOP_STR "tpl"
15 #undef CONFIG_AUTOBOOT_DELAY_STR
16 #define DEBUG_BOOTKEYS 0
17 #define CONFIG_BAUDRATE 115200
18 #define CFG_BAUDRATE_TABLE {115200}
21 * Miscellaneous configurable options
23 #define CFG_ALT_MEMTEST
24 #define CFG_HUSH_PARSER
25 #define CFG_LONGHELP /* undef to save memory */
26 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
27 #define CFG_PROMPT_HUSH_PS2 "> "
28 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
29 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */
30 #define CFG_MAXARGS 16 /* max number of command */
31 #define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */
32 #define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */
33 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
34 #define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */
35 #define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
36 #define CFG_RX_ETH_BUFFER 16
38 #if defined(CONFIG_SILENT_CONSOLE)
39 #define SILENT_ENV_VARIABLE "silent=1\0"
41 #define SILENT_ENV_VARIABLE ""
45 ** PLL Config for different CPU/DDR/AHB frequencies
47 #define CFG_PLL_200_200_100 1
48 #define CFG_PLL_200_200_200 2
49 #define CFG_PLL_225_225_112 3
50 #define CFG_PLL_225_225_225 4
51 #define CFG_PLL_250_250_125 5
52 #define CFG_PLL_250_250_250 6
53 #define CFG_PLL_300_300_150 7
54 #define CFG_PLL_325_325_162 8
55 #define CFG_PLL_350_350_175 9
56 #define CFG_PLL_360_360_180 10
57 #define CFG_PLL_380_380_190 11
58 #define CFG_PLL_400_400_200 12
59 #define CFG_PLL_412_412_206 13
60 #define CFG_PLL_420_420_210 14
61 #define CFG_PLL_425_425_212 15
62 #define CFG_PLL_437_437_218 16
63 #define CFG_PLL_440_440_220 17
64 #define CFG_PLL_450_450_225 18
65 #define CFG_PLL_460_460_230 19
66 #define CFG_PLL_475_475_237 20
67 #define CFG_PLL_480_480_240 21
68 #define CFG_PLL_487_487_243 22
69 #define CFG_PLL_500_500_250 23
70 #define CFG_PLL_500_250_250 24
71 #define CFG_PLL_520_520_260 25
72 #define CFG_PLL_525_262_131 26
73 #define CFG_PLL_560_280_140 27
74 #define CFG_PLL_580_290_145 28
75 #define CFG_PLL_600_300_200 29
78 #define CFG_PLL_566_400_200 101
79 #define CFG_PLL_566_500_250 102
80 #define CFG_PLL_600_1_2G_400_200 103
81 #define CFG_PLL_560_480_240 104
82 #define CFG_PLL_533_400_200 105
84 /*-----------------------------------------------------------------------
87 #define CFG_DCACHE_SIZE 32768
88 #define CFG_ICACHE_SIZE 65536
89 #define CFG_CACHELINE_SIZE 32
91 #endif /* __CONFIG_H */