2 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
4 * This file contains the configuration parameters
5 * for Qualcomm Atheros QCA953x based devices
7 * Reference designs: AP143
9 * SPDX-License-Identifier: GPL-2.0
16 #include <configs/qca9k_common.h>
17 #include <soc/soc_common.h>
24 #if defined(CONFIG_FOR_COMFAST_CF_E520N)
26 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11
27 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
28 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
29 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
31 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
32 defined(CONFIG_FOR_TPLINK_WR802N)
34 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13
35 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
36 #define CONFIG_QCA_GPIO_MASK_IN GPIO12
37 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
39 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
41 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO3 | GPIO4 | GPIO11 |\
42 GPIO13 | GPIO14 | GPIO15 |\
44 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
45 #define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
46 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
48 #elif defined(CONFIG_FOR_WALLYS_DR531)
50 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
51 GPIO14 | GPIO15 | GPIO16
52 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
53 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
54 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
56 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
58 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
59 GPIO13 | GPIO14 | GPIO15 |\
61 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
62 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
63 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
72 #if defined(CONFIG_FOR_COMFAST_CF_E520N)
74 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
75 "rootfstype=jffs2 init=/sbin/init "\
76 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
78 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN)
80 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
81 "rootfstype=squashfs init=/sbin/init "\
82 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
84 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
85 defined(CONFIG_FOR_TPLINK_WR802N)
87 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
88 "rootfstype=squashfs init=/sbin/init "\
89 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
91 #elif defined(CONFIG_FOR_WALLYS_DR531)
93 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
94 "rootfstype=jffs2 init=/sbin/init "\
95 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
97 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
99 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
100 "rootfstype=squashfs init=/sbin/init "\
101 "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
106 * =============================
107 * Load address and boot command
108 * =============================
110 #if defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
111 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
112 defined(CONFIG_FOR_TPLINK_WR802N) ||\
113 defined(CONFIG_FOR_TPLINK_WR841N_V9)
114 #define CFG_LOAD_ADDR 0x9F020000
115 #elif defined(CONFIG_FOR_WALLYS_DR531)
116 #define CFG_LOAD_ADDR 0x9F050000
117 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
118 #define CFG_LOAD_ADDR 0x9FE80000
121 #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
124 * =========================
125 * Environment configuration
126 * =========================
128 #if defined(CONFIG_FOR_COMFAST_CF_E520N)
129 #define CFG_ENV_ADDR 0x9F018000
130 #define CFG_ENV_SIZE 0x7C00
131 #define CFG_ENV_SECT_SIZE 0x10000
132 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
133 defined(CONFIG_FOR_TPLINK_WR802N) ||\
134 defined(CONFIG_FOR_TPLINK_WR841N_V9)
135 #define CFG_ENV_ADDR 0x9F01EC00
136 #define CFG_ENV_SIZE 0x1000
137 #define CFG_ENV_SECT_SIZE 0x10000
138 #elif defined(CONFIG_FOR_WALLYS_DR531)
139 #define CFG_ENV_ADDR 0x9F030000
140 #define CFG_ENV_SIZE 0xF800
141 #define CFG_ENV_SECT_SIZE 0x10000
142 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
143 #define CFG_ENV_ADDR 0x9F040000
144 #define CFG_ENV_SIZE 0xFC00
145 #define CFG_ENV_SECT_SIZE 0x10000
149 * ===========================
150 * List of available baudrates
151 * ===========================
153 #define CFG_BAUDRATE_TABLE \
154 { 600, 1200, 2400, 4800, 9600, 14400, \
155 19200, 28800, 38400, 56000, 57600, 115200 }
158 * ==================================================
159 * MAC address/es, model and WPS pin offsets in FLASH
160 * ==================================================
162 #if defined(CONFIG_FOR_COMFAST_CF_E520N)
163 #define OFFSET_MAC_DATA_BLOCK 0x10000
164 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x10000
165 #define OFFSET_MAC_ADDRESS 0x00000
166 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
167 defined(CONFIG_FOR_TPLINK_WR802N) ||\
168 defined(CONFIG_FOR_TPLINK_WR841N_V9)
169 #define OFFSET_MAC_DATA_BLOCK 0x010000
170 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
171 #define OFFSET_MAC_ADDRESS 0x00FC00
172 #define OFFSET_ROUTER_MODEL 0x00FD00
173 #define OFFSET_PIN_NUMBER 0x00FE00
174 #elif defined(CONFIG_FOR_WALLYS_DR531)
175 #define OFFSET_MAC_DATA_BLOCK 0x030000
176 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
177 #define OFFSET_MAC_ADDRESS 0x00F810
178 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
179 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
180 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
181 #define OFFSET_MAC_ADDRESS 0x000000
185 * =========================
186 * Custom changes per device
187 * =========================
190 /* Comfast CF-E520N is limited to 64 KB only, disable some commands */
191 #if defined(CONFIG_FOR_COMFAST_CF_E520N)
192 #undef CONFIG_CMD_DHCP
193 #undef CONFIG_CMD_LOADB
197 * ===========================
198 * HTTP recovery configuration
199 * ===========================
201 #if defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
202 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_FLASH_BASE + 0x50000
204 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
207 /* Firmware size limit */
208 #if defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
209 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
210 defined(CONFIG_FOR_TPLINK_WR802N) ||\
211 defined(CONFIG_FOR_TPLINK_WR841N_V9)
212 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
213 #elif defined(CONFIG_FOR_WALLYS_DR531) ||\
214 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
215 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
219 * ========================
220 * PLL/Clocks configuration
221 * ========================
223 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
224 defined(CONFIG_FOR_TPLINK_WR802N) ||\
225 defined(CONFIG_FOR_TPLINK_WR841N_V9)
226 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
227 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
228 defined(CONFIG_FOR_WALLYS_DR531) ||\
229 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
230 #define CONFIG_QCA_PLL QCA_PLL_PRESET_650_400_200
233 #if defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
234 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
235 defined(CONFIG_FOR_TPLINK_WR802N) ||\
236 defined(CONFIG_FOR_TPLINK_WR841N_V9)
238 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
239 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
241 #elif defined(CONFIG_FOR_WALLYS_DR531)
243 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
244 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
246 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
248 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000
249 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
254 * ==================================
255 * For upgrade scripts in environment
256 * ==================================
258 #if !defined(CONFIG_FOR_COMFAST_CF_E520N) &&\
259 !defined(CONFIG_FOR_WALLYS_DR531) &&\
260 !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
261 #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX 0x20000
264 #if defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
265 #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX 0x9F050000
269 * ===================
270 * Other configuration
271 * ===================
274 /* Cache lock for stack */
275 #define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800
277 #endif /* _AP143_H */