u-boot/include/configs/ap143.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef _AP143_CONFIG_H
   6 #define _AP143_CONFIG_H
   7
   8 #include <config.h>
   9 #include <atheros.h>
  10 #include <soc/soc_common.h>
  11
  12 /*
  13  * GPIO configuration
  14  */
  15 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  16         defined(CONFIG_FOR_TPLINK_WR802N)
  17         /* LEDs */
  18         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO13
  19
  20         /* Outputs, inputs */
  21         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  22         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO12
  23
  24         /* Initial states */
  25         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  26
  27 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
  28         /* LEDs */
  29         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO3 | GPIO4  | GPIO11 | GPIO13 |\
  30                                                                                                         GPIO14 | GPIO15 | GPIO16)
  31
  32         /* Outputs, inputs */
  33         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  34         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO12 | GPIO17)
  35
  36         /* Initial states */
  37         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  38
  39 #endif
  40
  41 /*
  42  * Miscellaneous configurable options
  43  */
  44 #ifndef CONFIG_BOOTDELAY
  45         #define CONFIG_BOOTDELAY        1
  46 #endif
  47
  48 #define CFG_LONGHELP
  49
  50 #define CONFIG_BAUDRATE                         115200
  51 #define CFG_BAUDRATE_TABLE                      { 600,    1200,   2400,    4800,    9600,    14400, \
  52                                                                           19200,  28800,  38400,   56000,   57600,   115200 }
  53
  54 #define CFG_ALT_MEMTEST
  55 #define CFG_HUSH_PARSER
  56 #define CFG_LONGHELP                                                                                                            /* undef to save memory      */
  57 #define CFG_PROMPT                      "uboot> "                                                                               /* Monitor Command Prompt    */
  58 #define CFG_PROMPT_HUSH_PS2     "> "
  59 #define CFG_CBSIZE                      1024                                                                                    /* Console I/O Buffer Size   */
  60 #define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)                              /* Print Buffer Size, was: def + 16 */
  61 #define CFG_MAXARGS                     16                                                                                              /* max number of command */
  62 #define CFG_MALLOC_LEN          512*1024                                                                                /* def: 128*1024 */
  63 #define CFG_BOOTPARAMS_LEN      512*1024                                                                                /* def: 128 */
  64 #define CFG_SDRAM_BASE          0x80000000                                                                              /* Cached addr */
  65 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x200000)                                             /* RAM test start = CFG_SDRAM_BASE + 2 MB */
  66 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001)    /* RAM test end   = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
  67 #define CFG_RX_ETH_BUFFER   16
  68
  69 #if defined(CONFIG_SILENT_CONSOLE)
  70         #define SILENT_ENV_VARIABLE     "silent=1\0"
  71 #else
  72         #define SILENT_ENV_VARIABLE     ""
  73 #endif
  74
  75 #define CFG_DCACHE_SIZE         32768
  76 #define CFG_ICACHE_SIZE         65536
  77 #define CFG_CACHELINE_SIZE      32
  78
  79 /*
  80  * FLASH and environment organization
  81  */
  82 #define CFG_MAX_FLASH_BANKS                     1
  83 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  84 #define CFG_FLASH_SECTOR_SIZE           64 * 1024
  85
  86 /*
  87  * We boot from this flash
  88  */
  89 #define CFG_FLASH_BASE                                  0x9F000000
  90 #ifdef COMPRESSED_UBOOT
  91         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  92         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  93 #endif
  94
  95 /*
  96  * The following #defines are needed to get flash environment right
  97  */
  98 #define CFG_MONITOR_BASE        TEXT_BASE
  99 #define CFG_MONITOR_LEN         (192 << 10)
 100
 101 /*
 102  * Default bootargs
 103  */
 104 #undef CONFIG_BOOTARGS
 105 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
 106         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
 107 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 108           defined(CONFIG_FOR_TPLINK_WR802N)
 109         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 110 #endif
 111
 112 /*
 113  * Other env default values
 114  */
 115 #undef CONFIG_BOOTFILE
 116 #define CONFIG_BOOTFILE                 "firmware.bin"
 117
 118 #undef CONFIG_LOADADDR
 119 #define CONFIG_LOADADDR                 0x80800000
 120
 121 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 122         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 123         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 124         #define CFG_LOAD_ADDR                    0x9F020000
 125         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 126         #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 127 #endif
 128
 129 #define CONFIG_IPADDR                   192.168.1.1
 130 #define CONFIG_SERVERIP                 192.168.1.2
 131
 132 /*
 133  * PLL/Clocks configuration
 134  */
 135 #ifdef CFG_HZ
 136         #undef  CFG_HZ
 137 #endif
 138 #define CFG_HZ  bd->bi_cfg_hz
 139
 140 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 141         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 142         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 143         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 144 #endif
 145
 146 /*
 147  * For PLL/clocks recovery use reset button by default
 148  */
 149 #ifdef CONFIG_GPIO_RESET_BTN
 150         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 151 #endif
 152
 153 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 154         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 155 #endif
 156
 157 /*
 158  * Address and size of Primary Environment Sector
 159  */
 160 #define CFG_ENV_IS_IN_FLASH     1
 161 #undef  CFG_ENV_IS_NOWHERE
 162
 163 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 164         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 165         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 166         #define CFG_ENV_ADDR            0x9F01EC00
 167         #define CFG_ENV_SIZE            0x1000
 168         #define CFG_ENV_SECT_SIZE       0x10000
 169 #endif
 170
 171 /*
 172  * Available commands
 173  */
 174 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 175         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 176         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 177         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 178                                                          CFG_CMD_DHCP   | \
 179                                                          CFG_CMD_PING   | \
 180                                                          CFG_CMD_FLASH  | \
 181                                                          CFG_CMD_NET    | \
 182                                                          CFG_CMD_RUN    | \
 183                                                          CFG_CMD_DATE   | \
 184                                                          CFG_CMD_SNTP   | \
 185                                                          CFG_CMD_ECHO   | \
 186                                                          CFG_CMD_BOOTD  | \
 187                                                          CFG_CMD_ITEST  | \
 188                                                          CFG_CMD_ENV    | \
 189                                                          CFG_CMD_LOADB)
 190 #endif
 191
 192 // Enable NetConsole and custom NetConsole port
 193 #define CONFIG_NETCONSOLE
 194 #define CONFIG_NETCONSOLE_PORT  6666
 195
 196 /*
 197  * Web Failsafe configuration
 198  */
 199 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 200 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 201
 202 // Firmware partition offset
 203 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 204         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 205         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 206         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 207 #endif
 208
 209 // U-Boot partition size
 210 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 211
 212 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 213 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 214         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 215         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 216         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 217         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 218 #endif
 219
 220 // ART partition size
 221 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 222
 223 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 224 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 225 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 226         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 227         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 228         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 229 #endif
 230
 231 // progress state info
 232 #define WEBFAILSAFE_PROGRESS_START                              0
 233 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 234 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 235 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 236 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 237
 238 // update type
 239 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 240 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 241 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 242
 243 /*-----------------------------------------------------------------------*/
 244
 245 /*
 246  * Additional environment variables for simple upgrades
 247  */
 248 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 249                                                                         "uboot_name=uboot.bin\0" \
 250                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 251                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 252                                                                         "uboot_upg=" \
 253                                                                                 "if ping $serverip; then " \
 254                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 255                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 256                                                                                         "tftp $loadaddr $uboot_name && " \
 257                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 258                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 259                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 260                                                                                                 "echo OK!; " \
 261                                                                                         "else " \
 262                                                                                                 "echo ERROR! Wrong file size!; " \
 263                                                                                         "fi; " \
 264                                                                                 "else " \
 265                                                                                         "echo ERROR! Server not reachable!; " \
 266                                                                                 "fi\0" \
 267                                                                         SILENT_ENV_VARIABLE
 268
 269 /*
 270  * Cache lock for stack
 271  */
 272 #define CFG_INIT_SP_OFFSET                      0x1000
 273 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 274
 275 /* For Merlin, both PCI, PCI-E interfaces are valid */
 276 #define ATH_ART_PCICFG_OFFSET           12
 277 /* use eth1(LAN) as the net interface */
 278 #define CONFIG_AG7240_SPEPHY
 279 #define CONFIG_NET_MULTI
 280 #define CONFIG_PCI 1
 281 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 282         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 283         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 284         #define WLANCAL                                 0x9fff1000
 285         #define BOARDCAL                                0x9fff0000
 286 #endif
 287 #define CFG_MII0_RMII                           1
 288 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 289
 290 #undef DEBUG
 291
 292 /* MAC address, model and PIN number offsets in FLASH */
 293 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 294         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 295         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 296         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 297         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 298         #define OFFSET_MAC_ADDRESS                              0x00FC00
 299         #define OFFSET_ROUTER_MODEL                             0x00FD00
 300         #define OFFSET_PIN_NUMBER                               0x00FE00
 301 #endif
 302
 303 /*
 304  * PLL and clocks configurations from FLASH
 305  */
 306 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 307         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 308         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 309         /*
 310          * All TP-Link routers have a lot of unused space
 311          * in FLASH, in second 64 KiB block.
 312          * We will store there PLL and CLOCK
 313          * registers configuration.
 314          */
 315         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 316         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 317
 318 #endif
 319
 320 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 321         /* Use last 32 bytes */
 322         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 323                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 324                                                                                                          0x0000FFE0)
 325 #endif
 326
 327 #include <cmd_confdefs.h>
 328
 329 #endif  /* __AP143_CONFIG_H */