u-boot/include/configs/ap143.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef _AP143_CONFIG_H
   6 #define _AP143_CONFIG_H
   7
   8 #include <config.h>
   9 #include <soc/soc_common.h>
  10
  11 /*
  12  * GPIO configuration
  13  */
  14 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  15         defined(CONFIG_FOR_TPLINK_WR802N)
  16         /* LEDs */
  17         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO13
  18
  19         /* Outputs, inputs */
  20         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  21         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO12
  22
  23         /* Initial states */
  24         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  25
  26 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
  27         /* LEDs */
  28         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO3 | GPIO4  | GPIO11 | GPIO13 |\
  29                                                                                                         GPIO14 | GPIO15 | GPIO16)
  30
  31         /* Outputs, inputs */
  32         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  33         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO12 | GPIO17)
  34
  35         /* Initial states */
  36         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  37
  38 #elif defined(CONFIG_FOR_WALLYS_DR531)
  39         /* LEDs */
  40         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO11 | GPIO12 | GPIO13 | GPIO14 |\
  41                                                                                                          GPIO15 | GPIO16)
  42
  43         /* Outputs, inputs */
  44         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  45         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO17
  46
  47         /* Initial states */
  48         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  49
  50 #endif
  51
  52 /*
  53  * Miscellaneous configurable options
  54  */
  55 #ifndef CONFIG_BOOTDELAY
  56         #define CONFIG_BOOTDELAY        1
  57 #endif
  58
  59 #define CFG_LONGHELP
  60
  61 #define CONFIG_BAUDRATE                         115200
  62 #define CFG_BAUDRATE_TABLE                      { 600,    1200,   2400,    4800,    9600,    14400, \
  63                                                                           19200,  28800,  38400,   56000,   57600,   115200 }
  64
  65 #define CFG_ALT_MEMTEST
  66 #define CFG_HUSH_PARSER
  67 #define CFG_LONGHELP                                                                                                            /* undef to save memory      */
  68 #define CFG_PROMPT                      "uboot> "                                                                               /* Monitor Command Prompt    */
  69 #define CFG_PROMPT_HUSH_PS2     "> "
  70 #define CFG_CBSIZE                      1024                                                                                    /* Console I/O Buffer Size   */
  71 #define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)                              /* Print Buffer Size, was: def + 16 */
  72 #define CFG_MAXARGS                     16                                                                                              /* max number of command */
  73 #define CFG_MALLOC_LEN          512*1024                                                                                /* def: 128*1024 */
  74 #define CFG_BOOTPARAMS_LEN      512*1024                                                                                /* def: 128 */
  75 #define CFG_SDRAM_BASE          0x80000000                                                                              /* Cached addr */
  76 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x200000)                                             /* RAM test start = CFG_SDRAM_BASE + 2 MB */
  77 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001)    /* RAM test end   = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
  78 #define CFG_RX_ETH_BUFFER   16
  79
  80 #if defined(CONFIG_SILENT_CONSOLE)
  81         #define SILENT_ENV_VARIABLE     "silent=1\0"
  82 #else
  83         #define SILENT_ENV_VARIABLE     ""
  84 #endif
  85
  86 #define CFG_DCACHE_SIZE         32768
  87 #define CFG_ICACHE_SIZE         65536
  88 #define CFG_CACHELINE_SIZE      32
  89
  90 /*
  91  * FLASH and environment organization
  92  */
  93 #define CFG_MAX_FLASH_BANKS                     1
  94 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  95 #define CFG_FLASH_SECTOR_SIZE           64 * 1024
  96
  97 /*
  98  * We boot from this flash
  99  */
 100 #define CFG_FLASH_BASE                                  0x9F000000
 101 #ifdef COMPRESSED_UBOOT
 102         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
 103         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
 104 #endif
 105
 106 /*
 107  * The following #defines are needed to get flash environment right
 108  */
 109 #define CFG_MONITOR_BASE        TEXT_BASE
 110 #define CFG_MONITOR_LEN         (192 << 10)
 111
 112 /*
 113  * Default bootargs
 114  */
 115 #undef CONFIG_BOOTARGS
 116 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
 117         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
 118 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 119           defined(CONFIG_FOR_TPLINK_WR802N)
 120         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 121 #elif defined(CONFIG_FOR_WALLYS_DR531)
 122         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
 123 #endif
 124
 125 /*
 126  * Other env default values
 127  */
 128 #undef CONFIG_BOOTFILE
 129 #define CONFIG_BOOTFILE                 "firmware.bin"
 130
 131 #undef CONFIG_LOADADDR
 132 #define CONFIG_LOADADDR                 0x80800000
 133
 134 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 135         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 136         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 137         #define CFG_LOAD_ADDR                    0x9F020000
 138         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 139         #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 140 #elif defined(CONFIG_FOR_WALLYS_DR531)
 141         #define CFG_LOAD_ADDR                    0x9F050000
 142         #define UPDATE_SCRIPT_FW_ADDR   "0x9F050000"
 143         #define CONFIG_BOOTCOMMAND              "bootm 0x9F050000"
 144 #endif
 145
 146 #define CONFIG_IPADDR                   192.168.1.1
 147 #define CONFIG_SERVERIP                 192.168.1.2
 148
 149 /*
 150  * PLL/Clocks configuration
 151  */
 152 #ifdef CFG_HZ
 153         #undef  CFG_HZ
 154 #endif
 155 #define CFG_HZ  bd->bi_cfg_hz
 156
 157 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 158         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 159         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 160         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 161 #elif defined(CONFIG_FOR_WALLYS_DR531)
 162         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_650_400_200
 163 #endif
 164
 165 /*
 166  * For PLL/clocks recovery use reset button by default
 167  */
 168 #ifdef CONFIG_GPIO_RESET_BTN
 169         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 170 #endif
 171
 172 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 173         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 174 #endif
 175
 176 /*
 177  * Address and size of Primary Environment Sector
 178  */
 179 #define CFG_ENV_IS_IN_FLASH     1
 180 #undef  CFG_ENV_IS_NOWHERE
 181
 182 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 183         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 184         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 185         #define CFG_ENV_ADDR            0x9F01EC00
 186         #define CFG_ENV_SIZE            0x1000
 187         #define CFG_ENV_SECT_SIZE       0x10000
 188 #elif defined(CONFIG_FOR_WALLYS_DR531)
 189         #define CFG_ENV_ADDR            0x9F030000
 190         #define CFG_ENV_SIZE            0xF800
 191         #define CFG_ENV_SECT_SIZE       0x10000
 192 #endif
 193
 194 /*
 195  * Available commands
 196  */
 197 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 198         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 199         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 200         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 201                                                          CFG_CMD_DHCP   | \
 202                                                          CFG_CMD_PING   | \
 203                                                          CFG_CMD_FLASH  | \
 204                                                          CFG_CMD_NET    | \
 205                                                          CFG_CMD_RUN    | \
 206                                                          CFG_CMD_DATE   | \
 207                                                          CFG_CMD_SNTP   | \
 208                                                          CFG_CMD_ECHO   | \
 209                                                          CFG_CMD_BOOTD  | \
 210                                                          CFG_CMD_ITEST  | \
 211                                                          CFG_CMD_ENV    | \
 212                                                          CFG_CMD_LOADB)
 213
 214 #elif defined(CONFIG_FOR_WALLYS_DR531)
 215
 216         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 217                                                          CFG_CMD_DHCP   | \
 218                                                          CFG_CMD_PING   | \
 219                                                          CFG_CMD_FLASH  | \
 220                                                          CFG_CMD_NET    | \
 221                                                          CFG_CMD_RUN    | \
 222                                                          CFG_CMD_DATE   | \
 223                                                          CFG_CMD_SNTP   | \
 224                                                          CFG_CMD_ECHO   | \
 225                                                          CFG_CMD_BOOTD  | \
 226                                                          CFG_CMD_ITEST  | \
 227                                                          CFG_CMD_IMI    | \
 228                                                          CFG_CMD_ENV    | \
 229                                                          CFG_CMD_LOADB)
 230
 231 #endif
 232
 233 // Enable NetConsole and custom NetConsole port
 234 #define CONFIG_NETCONSOLE
 235 #define CONFIG_NETCONSOLE_PORT  6666
 236
 237 /*
 238  * Web Failsafe configuration
 239  */
 240 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 241 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 242
 243 // Firmware partition offset
 244 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 245         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 246         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 247         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 248 #elif defined(CONFIG_FOR_WALLYS_DR531)
 249         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
 250 #endif
 251
 252 // U-Boot partition size
 253 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 254
 255 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 256 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 257         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 258         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 259         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 260         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 261 #elif defined(CONFIG_FOR_WALLYS_DR531)
 262         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x30000"
 263         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 264 #endif
 265
 266 // ART partition size
 267 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 268
 269 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 270 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 271 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 272         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 273         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 274         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 275 #elif defined(CONFIG_FOR_WALLYS_DR531)
 276         // Wallys DR531: 192k(U-Boot),64k(U-Boot env),64k(partition-table),64k(ART)
 277         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 278 #endif
 279
 280 // progress state info
 281 #define WEBFAILSAFE_PROGRESS_START                              0
 282 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 283 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 284 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 285 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 286
 287 // update type
 288 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 289 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 290 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 291
 292 /*-----------------------------------------------------------------------*/
 293
 294 /*
 295  * Additional environment variables for simple upgrades
 296  */
 297 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 298                                                                         "uboot_name=uboot.bin\0" \
 299                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 300                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 301                                                                         "uboot_upg=" \
 302                                                                                 "if ping $serverip; then " \
 303                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 304                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 305                                                                                         "tftp $loadaddr $uboot_name && " \
 306                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 307                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 308                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 309                                                                                                 "echo OK!; " \
 310                                                                                         "else " \
 311                                                                                                 "echo ERROR! Wrong file size!; " \
 312                                                                                         "fi; " \
 313                                                                                 "else " \
 314                                                                                         "echo ERROR! Server not reachable!; " \
 315                                                                                 "fi\0" \
 316                                                                         SILENT_ENV_VARIABLE
 317
 318 /*
 319  * Cache lock for stack
 320  */
 321 #define CFG_INIT_SP_OFFSET                      0x1000
 322 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 323
 324 /* use eth1(LAN) as the net interface */
 325 #define CONFIG_AG7240_SPEPHY
 326 #define CONFIG_NET_MULTI
 327
 328 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 329         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 330         defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 331         defined(CONFIG_FOR_WALLYS_DR531)
 332         #define BOARDCAL                                0x9fff0000
 333 #endif
 334 #define CFG_MII0_RMII                           1
 335 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 336
 337 #undef DEBUG
 338
 339 /* MAC address, model and PIN number offsets in FLASH */
 340 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 341         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 342         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 343         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 344         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 345         #define OFFSET_MAC_ADDRESS                              0x00FC00
 346         #define OFFSET_ROUTER_MODEL                             0x00FD00
 347         #define OFFSET_PIN_NUMBER                               0x00FE00
 348 #elif defined(CONFIG_FOR_WALLYS_DR531)
 349         #define OFFSET_MAC_DATA_BLOCK                   0x030000
 350         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 351         #define OFFSET_MAC_ADDRESS                              0x00F810
 352 #endif
 353
 354 /*
 355  * PLL and clocks configurations from FLASH
 356  */
 357 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 358         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 359         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 360         /*
 361          * All TP-Link routers have a lot of unused space
 362          * in FLASH, in second 64 KiB block.
 363          * We will store there PLL and CLOCK
 364          * registers configuration.
 365          */
 366         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 367         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 368
 369 #elif defined(CONFIG_FOR_WALLYS_DR531)
 370         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00030000
 371         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 372 #endif
 373
 374 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 375         /* Use last 32 bytes */
 376         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 377                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 378                                                                                                          0x0000FFE0)
 379 #endif
 380
 381 #include <cmd_confdefs.h>
 382
 383 #endif  /* __AP143_CONFIG_H */