u-boot/include/configs/ap143.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef _AP143_CONFIG_H
   6 #define _AP143_CONFIG_H
   7
   8 #include <config.h>
   9 #include <soc/soc_common.h>
  10
  11 /*
  12  * GPIO configuration
  13  */
  14 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  15         defined(CONFIG_FOR_TPLINK_WR802N)
  16         /* LEDs */
  17         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO13
  18
  19         /* Outputs, inputs */
  20         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  21         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO12
  22
  23         /* Initial states */
  24         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  25
  26 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
  27         /* LEDs */
  28         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO3 | GPIO4  | GPIO11 | GPIO13 |\
  29                                                                                                         GPIO14 | GPIO15 | GPIO16)
  30
  31         /* Outputs, inputs */
  32         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  33         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO12 | GPIO17)
  34
  35         /* Initial states */
  36         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  37
  38 #elif defined(CONFIG_FOR_WALLYS_DR531)
  39         /* LEDs */
  40         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO11 | GPIO12 | GPIO13 | GPIO14 |\
  41                                                                                                          GPIO15 | GPIO16)
  42
  43         /* Outputs, inputs */
  44         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  45         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO17
  46
  47         /* Initial states */
  48         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  49
  50 #endif
  51
  52 /*
  53  * Miscellaneous configurable options
  54  */
  55 #ifndef CONFIG_BOOTDELAY
  56         #define CONFIG_BOOTDELAY        1
  57 #endif
  58
  59 #define CFG_LONGHELP
  60
  61 #define CONFIG_BAUDRATE                         115200
  62 #define CFG_BAUDRATE_TABLE                      { 600,    1200,   2400,    4800,    9600,    14400, \
  63                                                                           19200,  28800,  38400,   56000,   57600,   115200 }
  64
  65 #define CFG_ALT_MEMTEST
  66 #define CFG_HUSH_PARSER
  67 #define CFG_LONGHELP                                                                                                            /* undef to save memory      */
  68 #define CFG_PROMPT                      "uboot> "                                                                               /* Monitor Command Prompt    */
  69 #define CFG_PROMPT_HUSH_PS2     "> "
  70 #define CFG_CBSIZE                      1024                                                                                    /* Console I/O Buffer Size   */
  71 #define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)                              /* Print Buffer Size, was: def + 16 */
  72 #define CFG_MAXARGS                     16                                                                                              /* max number of command */
  73 #define CFG_MALLOC_LEN          512*1024                                                                                /* def: 128*1024 */
  74 #define CFG_BOOTPARAMS_LEN      512*1024                                                                                /* def: 128 */
  75 #define CFG_SDRAM_BASE          0x80000000                                                                              /* Cached addr */
  76 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x200000)                                             /* RAM test start = CFG_SDRAM_BASE + 2 MB */
  77 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001)    /* RAM test end   = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
  78 #define CFG_RX_ETH_BUFFER   16
  79
  80 #define CFG_DCACHE_SIZE         32768
  81 #define CFG_ICACHE_SIZE         65536
  82 #define CFG_CACHELINE_SIZE      32
  83
  84 /*
  85  * FLASH and environment organization
  86  */
  87 #define CFG_MAX_FLASH_BANKS                     1
  88 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  89 #define CFG_FLASH_SECTOR_SIZE           64 * 1024
  90
  91 /*
  92  * We boot from this flash
  93  */
  94 #define CFG_FLASH_BASE                                  0x9F000000
  95 #ifdef COMPRESSED_UBOOT
  96         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  97         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  98 #endif
  99
 100 /*
 101  * The following #defines are needed to get flash environment right
 102  */
 103 #define CFG_MONITOR_BASE        TEXT_BASE
 104 #define CFG_MONITOR_LEN         (192 << 10)
 105
 106 /*
 107  * Default bootargs
 108  */
 109 #undef CONFIG_BOOTARGS
 110 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
 111         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
 112 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 113           defined(CONFIG_FOR_TPLINK_WR802N)
 114         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 115 #elif defined(CONFIG_FOR_WALLYS_DR531)
 116         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
 117 #endif
 118
 119 /*
 120  * Other env default values
 121  */
 122 #undef CONFIG_BOOTFILE
 123 #define CONFIG_BOOTFILE                 "firmware.bin"
 124
 125 #undef CONFIG_LOADADDR
 126 #define CONFIG_LOADADDR                 0x80800000
 127
 128 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 129         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 130         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 131         #define CFG_LOAD_ADDR                    0x9F020000
 132         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 133         #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 134 #elif defined(CONFIG_FOR_WALLYS_DR531)
 135         #define CFG_LOAD_ADDR                    0x9F050000
 136         #define UPDATE_SCRIPT_FW_ADDR   "0x9F050000"
 137         #define CONFIG_BOOTCOMMAND              "bootm 0x9F050000"
 138 #endif
 139
 140 #define CONFIG_IPADDR                   192.168.1.1
 141 #define CONFIG_SERVERIP                 192.168.1.2
 142
 143 /*
 144  * PLL/Clocks configuration
 145  */
 146 #ifdef CFG_HZ
 147         #undef  CFG_HZ
 148 #endif
 149 #define CFG_HZ  bd->bi_cfg_hz
 150
 151 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 152         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 153         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 154         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 155 #elif defined(CONFIG_FOR_WALLYS_DR531)
 156         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_650_400_200
 157 #endif
 158
 159 /*
 160  * For PLL/clocks recovery use reset button by default
 161  */
 162 #ifdef CONFIG_GPIO_RESET_BTN
 163         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 164 #endif
 165
 166 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 167         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 168 #endif
 169
 170 /*
 171  * Address and size of Primary Environment Sector
 172  */
 173 #define CFG_ENV_IS_IN_FLASH     1
 174 #undef  CFG_ENV_IS_NOWHERE
 175
 176 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 177         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 178         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 179         #define CFG_ENV_ADDR            0x9F01EC00
 180         #define CFG_ENV_SIZE            0x1000
 181         #define CFG_ENV_SECT_SIZE       0x10000
 182 #elif defined(CONFIG_FOR_WALLYS_DR531)
 183         #define CFG_ENV_ADDR            0x9F030000
 184         #define CFG_ENV_SIZE            0xF800
 185         #define CFG_ENV_SECT_SIZE       0x10000
 186 #endif
 187
 188 /*
 189  * Available commands
 190  */
 191 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 192                                                  CFG_CMD_DHCP   | \
 193                                                  CFG_CMD_PING   | \
 194                                                  CFG_CMD_FLASH  | \
 195                                                  CFG_CMD_NET    | \
 196                                                  CFG_CMD_RUN    | \
 197                                                  CFG_CMD_DATE   | \
 198                                                  CFG_CMD_SNTP   | \
 199                                                  CFG_CMD_ECHO   | \
 200                                                  CFG_CMD_BOOTD  | \
 201                                                  CFG_CMD_ITEST  | \
 202                                                  CFG_CMD_IMI    | \
 203                                                  CFG_CMD_ENV    | \
 204                                                  CFG_CMD_LOADB)
 205
 206 // Enable NetConsole and custom NetConsole port
 207 #define CONFIG_NETCONSOLE
 208 #define CONFIG_NETCONSOLE_PORT  6666
 209
 210 /*
 211  * Web Failsafe configuration
 212  */
 213 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 214 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 215
 216 // Firmware partition offset
 217 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 218         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 219         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 220         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 221 #elif defined(CONFIG_FOR_WALLYS_DR531)
 222         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
 223 #endif
 224
 225 // U-Boot partition size
 226 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 227
 228 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 229 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 230         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 231         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 232         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 233         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 234 #elif defined(CONFIG_FOR_WALLYS_DR531)
 235         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x30000"
 236         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 237 #endif
 238
 239 // ART partition size
 240 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 241
 242 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 243 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 244 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 245         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 246         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 247         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 248 #elif defined(CONFIG_FOR_WALLYS_DR531)
 249         // Wallys DR531: 192k(U-Boot),64k(U-Boot env),64k(partition-table),64k(ART)
 250         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 251 #endif
 252
 253 // progress state info
 254 #define WEBFAILSAFE_PROGRESS_START                              0
 255 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 256 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 257 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 258 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 259
 260 // update type
 261 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 262 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 263 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 264
 265 /*-----------------------------------------------------------------------*/
 266
 267 /*
 268  * Additional environment variables for simple upgrades
 269  */
 270 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 271                                                                         "uboot_name=uboot.bin\0" \
 272                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 273                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 274                                                                         "uboot_upg=" \
 275                                                                                 "if ping $serverip; then " \
 276                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 277                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 278                                                                                         "tftp $loadaddr $uboot_name && " \
 279                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 280                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 281                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 282                                                                                                 "echo OK!; " \
 283                                                                                         "else " \
 284                                                                                                 "echo ERROR! Wrong file size!; " \
 285                                                                                         "fi; " \
 286                                                                                 "else " \
 287                                                                                         "echo ERROR! Server not reachable!; " \
 288                                                                                 "fi\0"
 289 /*
 290  * Cache lock for stack
 291  */
 292 #define CFG_INIT_SP_OFFSET                      0x1000
 293 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 294
 295 /* use eth1(LAN) as the net interface */
 296 #define CONFIG_AG7240_SPEPHY
 297 #define CONFIG_NET_MULTI
 298
 299 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 300         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 301         defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 302         defined(CONFIG_FOR_WALLYS_DR531)
 303         #define BOARDCAL                                0x9fff0000
 304 #endif
 305 #define CFG_MII0_RMII                           1
 306 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 307
 308 #undef DEBUG
 309
 310 /* MAC address, model and PIN number offsets in FLASH */
 311 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 312         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 313         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 314         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 315         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 316         #define OFFSET_MAC_ADDRESS                              0x00FC00
 317         #define OFFSET_ROUTER_MODEL                             0x00FD00
 318         #define OFFSET_PIN_NUMBER                               0x00FE00
 319 #elif defined(CONFIG_FOR_WALLYS_DR531)
 320         #define OFFSET_MAC_DATA_BLOCK                   0x030000
 321         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 322         #define OFFSET_MAC_ADDRESS                              0x00F810
 323 #endif
 324
 325 /*
 326  * PLL and clocks configurations from FLASH
 327  */
 328 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 329         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 330         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 331         /*
 332          * All TP-Link routers have a lot of unused space
 333          * in FLASH, in second 64 KiB block.
 334          * We will store there PLL and CLOCK
 335          * registers configuration.
 336          */
 337         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 338         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 339
 340 #elif defined(CONFIG_FOR_WALLYS_DR531)
 341         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00030000
 342         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 343 #endif
 344
 345 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 346         /* Use last 32 bytes */
 347         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 348                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 349                                                                                                          0x0000FFE0)
 350 #endif
 351
 352 #include <cmd_confdefs.h>
 353
 354 #endif  /* __AP143_CONFIG_H */