2 * This file contains the configuration parameters for the DB12x (AR9344) board.
5 #ifndef _AP143_CONFIG_H
6 #define _AP143_CONFIG_H
10 #include <soc/soc_common.h>
15 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
17 #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO13
20 #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
21 #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO12
24 #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
28 * Miscellaneous configurable options
30 #ifndef CONFIG_BOOTDELAY
31 #define CONFIG_BOOTDELAY 1
36 #define CONFIG_BAUDRATE 115200
37 #define CFG_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \
38 19200, 28800, 38400, 56000, 57600, 115200 }
40 #define CFG_ALT_MEMTEST
41 #define CFG_HUSH_PARSER
42 #define CFG_LONGHELP /* undef to save memory */
43 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
44 #define CFG_PROMPT_HUSH_PS2 "> "
45 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
46 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */
47 #define CFG_MAXARGS 16 /* max number of command */
48 #define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */
49 #define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */
50 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
51 #define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */
52 #define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
53 #define CFG_RX_ETH_BUFFER 16
55 #if defined(CONFIG_SILENT_CONSOLE)
56 #define SILENT_ENV_VARIABLE "silent=1\0"
58 #define SILENT_ENV_VARIABLE ""
61 #define CFG_DCACHE_SIZE 32768
62 #define CFG_ICACHE_SIZE 65536
63 #define CFG_CACHELINE_SIZE 32
66 * FLASH and environment organization
68 #define CFG_MAX_FLASH_BANKS 1
69 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
70 #define CFG_FLASH_SECTOR_SIZE 64 * 1024
73 * We boot from this flash
75 #define CFG_FLASH_BASE 0x9F000000
76 #ifdef COMPRESSED_UBOOT
77 #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
78 #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
82 * The following #defines are needed to get flash environment right
84 #define CFG_MONITOR_BASE TEXT_BASE
85 #define CFG_MONITOR_LEN (192 << 10)
90 #undef CONFIG_BOOTARGS
91 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
92 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
96 * Other env default values
98 #undef CONFIG_BOOTFILE
99 #define CONFIG_BOOTFILE "firmware.bin"
101 #undef CONFIG_LOADADDR
102 #define CONFIG_LOADADDR 0x80800000
104 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
105 #define CFG_LOAD_ADDR 0x9F020000
106 #define UPDATE_SCRIPT_FW_ADDR "0x9F020000"
107 #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
110 #define CONFIG_IPADDR 192.168.1.1
111 #define CONFIG_SERVERIP 192.168.1.2
114 * PLL/Clocks configuration
119 #define CFG_HZ bd->bi_cfg_hz
121 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
122 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
123 #define CFG_HZ_FALLBACK (550000000LU/2)
127 * For PLL/clocks recovery use reset button by default
129 #ifdef GPIO_RST_BUTTON_BIT
130 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN GPIO_RST_BUTTON_BIT
133 #ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW
134 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
138 * Address and size of Primary Environment Sector
140 #define CFG_ENV_IS_IN_FLASH 1
141 #undef CFG_ENV_IS_NOWHERE
143 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
144 #define CFG_ENV_ADDR 0x9F01EC00
145 #define CFG_ENV_SIZE 0x1000
146 #define CFG_ENV_SECT_SIZE 0x10000
152 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
153 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
168 // Enable NetConsole and custom NetConsole port
169 #define CONFIG_NETCONSOLE
170 #define CONFIG_NETCONSOLE_PORT 6666
172 /*modify from 0x4138 to 0x40c3, ddr refresh interval: 12uS to 7.8uS. by wkp
173 from Li Guanwen, 30Dec14. */
174 //#define CFG_DDR_REFRESH_VAL 0x40c3 (??????????????????)
175 #define CFG_DDR_REFRESH_VAL 0x4138
178 * Web Failsafe configuration
180 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
181 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
183 // Firmware partition offset
184 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
185 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
188 // U-Boot partition size
189 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
191 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
192 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
193 #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00"
194 #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000"
197 // ART partition size
198 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
200 // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
201 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
202 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
203 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
206 // progress state info
207 #define WEBFAILSAFE_PROGRESS_START 0
208 #define WEBFAILSAFE_PROGRESS_TIMEOUT 1
209 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
210 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
211 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
214 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
215 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
216 #define WEBFAILSAFE_UPGRADE_TYPE_ART 2
218 /*-----------------------------------------------------------------------*/
221 * Additional environment variables for simple upgrades
223 #define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \
224 "uboot_name=uboot.bin\0" \
225 "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
226 "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
228 "if ping $serverip; then " \
229 "mw.b $loadaddr 0xFF $uboot_backup_size && " \
230 "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
231 "tftp $loadaddr $uboot_name && " \
232 "if itest.l $filesize <= $uboot_size; then " \
233 "erase $uboot_addr +$uboot_backup_size && " \
234 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
237 "echo ERROR! Wrong file size!; " \
240 "echo ERROR! Server not reachable!; " \
245 * Cache lock for stack
247 #define CFG_INIT_SP_OFFSET 0x1000
248 #define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800
250 /* For Merlin, both PCI, PCI-E interfaces are valid */
251 #define ATH_ART_PCICFG_OFFSET 12
252 /* use eth1(LAN) as the net interface */
253 #define CONFIG_AG7240_SPEPHY
254 #define CONFIG_NET_MULTI
256 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
257 #define WLANCAL 0x9fff1000
258 #define BOARDCAL 0x9fff0000
260 #define CFG_MII0_RMII 1
261 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
265 /* MAC address, model and PIN number offsets in FLASH */
266 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
267 #define OFFSET_MAC_DATA_BLOCK 0x010000
268 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
269 #define OFFSET_MAC_ADDRESS 0x00FC00
270 #define OFFSET_ROUTER_MODEL 0x00FD00
271 #define OFFSET_PIN_NUMBER 0x00FE00
275 * PLL and clocks configurations from FLASH
277 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
279 * All TP-Link routers have a lot of unused space
280 * in FLASH, in second 64 KiB block.
281 * We will store there PLL and CLOCK
282 * registers configuration.
284 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000
285 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
289 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
290 /* Use last 32 bytes */
291 #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \
292 CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
296 #include <cmd_confdefs.h>
298 #endif /* __AP143_CONFIG_H */