u-boot/include/configs/ap143.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros QCA953x based devices
   6  *
   7  * Reference designs: AP143
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _AP143_H
  13 #define _AP143_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  25     defined(CONFIG_FOR_TPLINK_WR802N)
  26
  27         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  28         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  29         #define CONFIG_QCA_GPIO_MASK_IN         GPIO12
  30         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  31
  32 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
  33
  34         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO3  | GPIO4  | GPIO11 |\
  35                                                 GPIO13 | GPIO14 | GPIO15 |\
  36                                                 GPIO16
  37         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  38         #define CONFIG_QCA_GPIO_MASK_IN         GPIO12 | GPIO17
  39         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  40
  41 #elif defined(CONFIG_FOR_WALLYS_DR531)
  42
  43         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
  44                                                 GPIO14 | GPIO15 | GPIO16
  45         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  46         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  47         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  48
  49 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
  50
  51         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
  52                                                 GPIO13 | GPIO14 | GPIO15 |\
  53                                                 GPIO16
  54         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  55         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  56         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  57
  58 #endif
  59
  60 /*
  61  * ================
  62  * Default bootargs
  63  * ================
  64  */
  65 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
  66
  67         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
  68                                 "rootfstype=squashfs init=/sbin/init "\
  69                                 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
  70
  71 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
  72       defined(CONFIG_FOR_TPLINK_WR802N)
  73
  74         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
  75                                 "rootfstype=squashfs init=/sbin/init "\
  76                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
  77
  78 #elif defined(CONFIG_FOR_WALLYS_DR531)
  79
  80         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
  81                                 "rootfstype=jffs2 init=/sbin/init "\
  82                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
  83
  84 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
  85
  86         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
  87                                 "rootfstype=squashfs init=/sbin/init "\
  88                                 "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
  89
  90 #endif
  91
  92 /*
  93  * =============================
  94  * Load address and boot command
  95  * =============================
  96  */
  97 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  98     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
  99     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 100         #define CFG_LOAD_ADDR   0x9F020000
 101 #elif defined(CONFIG_FOR_WALLYS_DR531)
 102         #define CFG_LOAD_ADDR   0x9F050000
 103 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 104         #define CFG_LOAD_ADDR   0x9FE80000
 105 #endif
 106
 107 #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 108
 109 /*
 110  * =========================
 111  * Environment configuration
 112  * =========================
 113  */
 114 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 115     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 116     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 117         #define CFG_ENV_ADDR            0x9F01EC00
 118         #define CFG_ENV_SIZE            0x1000
 119         #define CFG_ENV_SECT_SIZE       0x10000
 120 #elif defined(CONFIG_FOR_WALLYS_DR531)
 121         #define CFG_ENV_ADDR            0x9F030000
 122         #define CFG_ENV_SIZE            0xF800
 123         #define CFG_ENV_SECT_SIZE       0x10000
 124 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 125         #define CFG_ENV_ADDR            0x9F040000
 126         #define CFG_ENV_SIZE            0xFC00
 127         #define CFG_ENV_SECT_SIZE       0x10000
 128 #endif
 129
 130 /*
 131  * ===========================
 132  * List of available baudrates
 133  * ===========================
 134  */
 135 #define CFG_BAUDRATE_TABLE      \
 136                 { 600,    1200,   2400,    4800,    9600,    14400, \
 137                   19200,  28800,  38400,   56000,   57600,   115200 }
 138
 139 /*
 140  * ==================================================
 141  * MAC address/es, model and WPS pin offsets in FLASH
 142  * ==================================================
 143  */
 144 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 145     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 146     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 147         #define OFFSET_MAC_DATA_BLOCK           0x010000
 148         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 149         #define OFFSET_MAC_ADDRESS              0x00FC00
 150         #define OFFSET_ROUTER_MODEL             0x00FD00
 151         #define OFFSET_PIN_NUMBER               0x00FE00
 152 #elif defined(CONFIG_FOR_WALLYS_DR531)
 153         #define OFFSET_MAC_DATA_BLOCK           0x030000
 154         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 155         #define OFFSET_MAC_ADDRESS              0x00F810
 156 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 157         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 158         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 159         #define OFFSET_MAC_ADDRESS              0x000000
 160 #endif
 161
 162 /*
 163  * ===========================
 164  * HTTP recovery configuration
 165  * ===========================
 166  */
 167 #if defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 168         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_FLASH_BASE + 0x50000
 169 #else
 170         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 171 #endif
 172
 173 /* Firmware size limit */
 174 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 175     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 176     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 177         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 178 #elif defined(CONFIG_FOR_WALLYS_DR531) ||\
 179       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 180         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 181 #endif
 182
 183 /*
 184  * ========================
 185  * PLL/Clocks configuration
 186  * ========================
 187  */
 188 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 189     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 190     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 191         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
 192 #elif defined(CONFIG_FOR_WALLYS_DR531) ||\
 193       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 194         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_650_400_200
 195 #endif
 196
 197 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 198     defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 199     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 200
 201         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 202         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 203
 204 #elif defined(CONFIG_FOR_WALLYS_DR531)
 205
 206         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x30000
 207         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 208
 209 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 210
 211         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 212         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 213
 214 #endif
 215
 216 /*
 217  * ===================
 218  * Other configuration
 219  * ===================
 220  */
 221
 222 /* Cache lock for stack */
 223 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 224
 225 #endif /* _AP143_H */