2 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
4 * This file contains the configuration parameters
5 * for Qualcomm Atheros QCA953x based devices
7 * Reference designs: AP143
9 * SPDX-License-Identifier: GPL-2.0
16 #include <configs/qca9k_common.h>
17 #include <soc/soc_common.h>
24 #if defined(CONFIG_FOR_COMFAST_CF_E314N)
26 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO4 | GPIO11 | GPIO14 |\
28 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO2 | GPIO3
29 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H |\
30 CONFIG_QCA_GPIO_MASK_LED_ACT_L
31 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
32 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
33 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
35 #elif defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
37 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO2 | GPIO3
38 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H
39 #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO12 | GPIO14 |\
41 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
43 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
44 defined(CONFIG_FOR_COMFAST_CF_E530N)
46 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11
47 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
48 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
49 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
51 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
52 defined(CONFIG_FOR_TPLINK_WR802N)
54 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13
55 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
56 #define CONFIG_QCA_GPIO_MASK_IN GPIO12
57 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
59 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
60 defined(CONFIG_FOR_TPLINK_WR841N_V9)
62 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO3 | GPIO4 | GPIO11 |\
63 GPIO13 | GPIO14 | GPIO15 |\
65 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
66 #define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
67 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
69 #elif defined(CONFIG_FOR_TPLINK_WR841N_V11)
71 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO1 | GPIO2 | GPIO3 |\
72 GPIO4 | GPIO11 | GPIO13 |\
73 GPIO14 | GPIO15 | GPIO16
74 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
75 #define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
76 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
78 #elif defined(CONFIG_FOR_WALLYS_DR531)
80 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
81 GPIO14 | GPIO15 | GPIO16
82 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
83 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
84 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
86 #elif defined(CONFIG_FOR_YUNCORE_AP90Q)
88 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO12 | GPIO16
89 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
90 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
91 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
93 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
95 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
96 GPIO13 | GPIO14 | GPIO15 |\
98 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
99 #define CONFIG_QCA_GPIO_MASK_IN GPIO17
100 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
109 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
110 defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
112 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
113 "rootfstype=jffs2 init=/sbin/init "\
114 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),14656k(rootfs),64k(mib0)"
116 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
117 defined(CONFIG_FOR_COMFAST_CF_E530N)
119 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
120 "rootfstype=jffs2 init=/sbin/init "\
121 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
123 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN)
125 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
126 "rootfstype=squashfs init=/sbin/init "\
127 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
129 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
130 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
131 defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
132 defined(CONFIG_FOR_TPLINK_WR802N)
134 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
135 "rootfstype=squashfs init=/sbin/init "\
136 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
138 #elif defined(CONFIG_FOR_WALLYS_DR531)
140 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
141 "rootfstype=jffs2 init=/sbin/init "\
142 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
144 #elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
145 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
147 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
148 "rootfstype=squashfs init=/sbin/init "\
149 "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
154 * =============================
155 * Load address and boot command
156 * =============================
158 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
159 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
160 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
161 defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
162 defined(CONFIG_FOR_TPLINK_WR802N) ||\
163 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
164 defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
165 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
166 defined(CONFIG_FOR_TPLINK_WR841N_V9)
167 #define CFG_LOAD_ADDR 0x9F020000
168 #elif defined(CONFIG_FOR_WALLYS_DR531)
169 #define CFG_LOAD_ADDR 0x9F050000
170 #elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
171 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
172 #define CFG_LOAD_ADDR 0x9FE80000
175 #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
178 * =========================
179 * Environment configuration
180 * =========================
182 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
183 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
184 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
185 defined(CONFIG_FOR_COMFAST_CF_E530N)
186 #define CFG_ENV_ADDR 0x9F018000
187 #define CFG_ENV_SIZE 0x7C00
188 #define CFG_ENV_SECT_SIZE 0x10000
189 #elif defined(CONFIG_FOR_TPLINK_WR802N) ||\
190 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
191 defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
192 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
193 defined(CONFIG_FOR_TPLINK_WR841N_V9)
194 #define CFG_ENV_ADDR 0x9F01EC00
195 #define CFG_ENV_SIZE 0x1000
196 #define CFG_ENV_SECT_SIZE 0x10000
197 #elif defined(CONFIG_FOR_WALLYS_DR531)
198 #define CFG_ENV_ADDR 0x9F030000
199 #define CFG_ENV_SIZE 0xF800
200 #define CFG_ENV_SECT_SIZE 0x10000
201 #elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
202 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
203 #define CFG_ENV_ADDR 0x9F040000
204 #define CFG_ENV_SIZE 0xFC00
205 #define CFG_ENV_SECT_SIZE 0x10000
209 * ===========================
210 * List of available baudrates
211 * ===========================
213 #define CFG_BAUDRATE_TABLE \
214 { 600, 1200, 2400, 4800, 9600, 14400, \
215 19200, 28800, 38400, 56000, 57600, 115200 }
218 * ==================================================
219 * MAC address/es, model and WPS pin offsets in FLASH
220 * ==================================================
222 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
223 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
224 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
225 defined(CONFIG_FOR_COMFAST_CF_E530N)
226 #define OFFSET_MAC_DATA_BLOCK 0x10000
227 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x10000
228 #define OFFSET_MAC_ADDRESS 0x00000
229 #elif defined(CONFIG_FOR_TPLINK_WR802N) ||\
230 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
231 defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
232 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
233 defined(CONFIG_FOR_TPLINK_WR841N_V9)
234 #define OFFSET_MAC_DATA_BLOCK 0x010000
235 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
236 #define OFFSET_MAC_ADDRESS 0x00FC00
237 #define OFFSET_ROUTER_MODEL 0x00FD00
238 #define OFFSET_PIN_NUMBER 0x00FE00
239 #elif defined(CONFIG_FOR_WALLYS_DR531)
240 #define OFFSET_MAC_DATA_BLOCK 0x030000
241 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
242 #define OFFSET_MAC_ADDRESS 0x00F810
243 #elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
244 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
245 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
246 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
247 #define OFFSET_MAC_ADDRESS 0x000000
251 * =========================
252 * Custom changes per device
253 * =========================
257 * Comfast CF-E520N and E320Nv2 are limited to 64 KB only,
258 * disable some commands
260 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
261 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
262 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
263 defined(CONFIG_FOR_COMFAST_CF_E530N)
264 #undef CONFIG_CMD_DHCP
265 #undef CONFIG_CMD_LOADB
266 #undef CONFIG_CMD_SNTP
270 * ===========================
271 * HTTP recovery configuration
272 * ===========================
274 #if defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
275 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
276 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_FLASH_BASE + 0x50000
278 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
281 /* Firmware size limit */
282 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
283 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
284 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
285 defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
286 defined(CONFIG_FOR_TPLINK_WR802N) ||\
287 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
288 defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
289 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
290 defined(CONFIG_FOR_TPLINK_WR841N_V9)
291 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
292 #elif defined(CONFIG_FOR_WALLYS_DR531) ||\
293 defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
294 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
295 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
299 * ========================
300 * PLL/Clocks configuration
301 * ========================
303 #if defined(CONFIG_FOR_TPLINK_WR802N) ||\
304 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
305 defined(CONFIG_FOR_TPLINK_WR841N_V9)
306 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
308 #define CONFIG_QCA_PLL QCA_PLL_PRESET_650_400_200
311 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
312 defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
313 defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
314 defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
315 defined(CONFIG_FOR_TPLINK_WR802N) ||\
316 defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
317 defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
318 defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
319 defined(CONFIG_FOR_TPLINK_WR841N_V9)
321 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
322 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
324 #elif defined(CONFIG_FOR_WALLYS_DR531)
326 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
327 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
329 #elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
330 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
332 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000
333 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
338 * ==================================
339 * For upgrade scripts in environment
340 * ==================================
342 #if !defined(CONFIG_FOR_COMFAST_CF_E314N) &&\
343 !defined(CONFIG_FOR_COMFAST_CF_E320N_V2) &&\
344 !defined(CONFIG_FOR_COMFAST_CF_E520N) &&\
345 !defined(CONFIG_FOR_COMFAST_CF_E530N) &&\
346 !defined(CONFIG_FOR_WALLYS_DR531) &&\
347 !defined(CONFIG_FOR_YUNCORE_AP90Q) &&\
348 !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
349 #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX 0x20000
352 #if defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
353 defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
354 #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX 0x9F050000
358 * ===================
359 * Other configuration
360 * ===================
363 /* Cache lock for stack */
364 #define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800
366 #endif /* _AP143_H */