u-boot/include/configs/ap143.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros QCA953x based devices
   6  *
   7  * Reference designs: AP143
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _AP143_H
  13 #define _AP143_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_COMFAST_CF_E314N)
  25
  26         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO4  | GPIO11 | GPIO14 |\
  27                                                 GPIO15 | GPIO16
  28         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO2 | GPIO3
  29         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H |\
  30                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  31         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  32         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  33         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  34
  35 #elif defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
  36
  37         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO2 | GPIO3
  38         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H
  39         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO12 | GPIO14 |\
  40                                                 GPIO16 | GPIO17
  41         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  42
  43 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
  44       defined(CONFIG_FOR_COMFAST_CF_E530N)
  45
  46         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11
  47         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  48         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  49         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  50
  51 #elif defined(CONFIG_FOR_P2W_CPE505N)
  52
  53         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
  54                                                 GPIO14 | GPIO15
  55         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  56         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  57         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  58
  59 #elif defined(CONFIG_FOR_P2W_R602N)
  60
  61         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
  62                                                 GPIO14 | GPIO15 | GPIO16
  63         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  64         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  65         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  66
  67 #elif defined(CONFIG_FOR_TPLINK_WR810N)
  68
  69         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  70         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO11 |\
  71                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  72         #define CONFIG_QCA_GPIO_MASK_IN         GPIO0 | GPIO1 | GPIO12
  73         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11 |\
  74                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  75
  76 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  77       defined(CONFIG_FOR_TPLINK_WR802N)
  78
  79         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  80         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  81         #define CONFIG_QCA_GPIO_MASK_IN         GPIO12
  82         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  83
  84 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
  85       defined(CONFIG_FOR_TPLINK_WR841N_V9)
  86
  87         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO3  | GPIO4  | GPIO11 |\
  88                                                 GPIO13 | GPIO14 | GPIO15 |\
  89                                                 GPIO16
  90         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  91         #define CONFIG_QCA_GPIO_MASK_IN         GPIO12 | GPIO17
  92         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  93
  94 #elif defined(CONFIG_FOR_TPLINK_WR841N_V11)
  95
  96         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO1  | GPIO2  | GPIO3  |\
  97                                                 GPIO4  | GPIO11 | GPIO13 |\
  98                                                 GPIO14 | GPIO15 | GPIO16
  99         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 100         #define CONFIG_QCA_GPIO_MASK_IN         GPIO12 | GPIO17
 101         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 102
 103 #elif defined(CONFIG_FOR_WALLYS_DR531)
 104
 105         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
 106                                                 GPIO14 | GPIO15 | GPIO16
 107         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 108         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 109         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 110
 111 #elif defined(CONFIG_FOR_YUNCORE_AP90Q)
 112
 113         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4 | GPIO12 | GPIO16
 114         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 115         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 116         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 117
 118 #elif defined(CONFIG_FOR_YUNCORE_CPE830)
 119
 120         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO1 | GPIO2  |\
 121                                                 GPIO3 | GPIO4 | GPIO12 |\
 122                                                 GPIO16
 123         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 124         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 125         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 126
 127 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 128
 129         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
 130                                                 GPIO13 | GPIO14 | GPIO15 |\
 131                                                 GPIO16
 132         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 133         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 134         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 135
 136 #endif
 137
 138 /*
 139  * ================
 140  * Default bootargs
 141  * ================
 142  */
 143 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
 144     defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
 145
 146         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
 147                                 "rootfstype=jffs2 init=/sbin/init "\
 148                                 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),14656k(rootfs),64k(mib0)"
 149
 150 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
 151       defined(CONFIG_FOR_COMFAST_CF_E530N)
 152
 153         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
 154                                 "rootfstype=jffs2 init=/sbin/init "\
 155                                 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
 156
 157 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 158       defined(CONFIG_FOR_P2W_R602N)      ||\
 159       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 160       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 161       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 162
 163         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 164                                 "rootfstype=squashfs init=/sbin/init "\
 165                                 "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
 166
 167 #elif defined(CONFIG_FOR_TPLINK_WR810N)
 168
 169         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 170                                 "rootfstype=squashfs init=/sbin/init "\
 171                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 172
 173 #elif defined(CONFIG_FOR_TPLINK_WR820N_CN)
 174
 175         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 176                                 "rootfstype=squashfs init=/sbin/init "\
 177                                 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
 178
 179 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
 180       defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
 181       defined(CONFIG_FOR_TPLINK_WR841N_V9)  ||\
 182       defined(CONFIG_FOR_TPLINK_WR802N)
 183
 184         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 185                                 "rootfstype=squashfs init=/sbin/init "\
 186                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 187
 188 #elif defined(CONFIG_FOR_WALLYS_DR531)
 189
 190         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 191                                 "rootfstype=jffs2 init=/sbin/init "\
 192                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
 193
 194 #endif
 195
 196 /*
 197  * =============================
 198  * Load address and boot command
 199  * =============================
 200  */
 201 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 202     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 203     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 204     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 205     defined(CONFIG_FOR_TPLINK_WR802N)       ||\
 206     defined(CONFIG_FOR_TPLINK_WR810N)       ||\
 207     defined(CONFIG_FOR_TPLINK_WR820N_CN)    ||\
 208     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 209     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 210     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 211         #define CFG_LOAD_ADDR   0x9F020000
 212 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 213       defined(CONFIG_FOR_P2W_R602N)      ||\
 214       defined(CONFIG_FOR_WALLYS_DR531)   ||\
 215       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 216       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 217       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 218         #define CFG_LOAD_ADDR   0x9F050000
 219 #endif
 220
 221 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
 222     defined(CONFIG_FOR_P2W_R602N)      ||\
 223     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 224     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 225     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 226         #define CONFIG_BOOTCOMMAND      "bootm 0x9F050000 || bootm 0x9FE80000"
 227 #else
 228         #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 229 #endif
 230
 231 /*
 232  * =========================
 233  * Environment configuration
 234  * =========================
 235  */
 236 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 237     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 238     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 239     defined(CONFIG_FOR_COMFAST_CF_E530N)
 240         #define CFG_ENV_ADDR            0x9F018000
 241         #define CFG_ENV_SIZE            0x7C00
 242         #define CFG_ENV_SECT_SIZE       0x10000
 243 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 244       defined(CONFIG_FOR_P2W_R602N)      ||\
 245       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 246       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 247       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 248         #define CFG_ENV_ADDR            0x9F040000
 249         #define CFG_ENV_SIZE            0xFC00
 250         #define CFG_ENV_SECT_SIZE       0x10000
 251 #elif defined(CONFIG_FOR_TPLINK_WR802N)     ||\
 252       defined(CONFIG_FOR_TPLINK_WR810N)     ||\
 253       defined(CONFIG_FOR_TPLINK_WR820N_CN)  ||\
 254       defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
 255       defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
 256       defined(CONFIG_FOR_TPLINK_WR841N_V9)
 257         #define CFG_ENV_ADDR            0x9F01EC00
 258         #define CFG_ENV_SIZE            0x1000
 259         #define CFG_ENV_SECT_SIZE       0x10000
 260 #elif defined(CONFIG_FOR_WALLYS_DR531)
 261         #define CFG_ENV_ADDR            0x9F030000
 262         #define CFG_ENV_SIZE            0xF800
 263         #define CFG_ENV_SECT_SIZE       0x10000
 264 #endif
 265
 266 /*
 267  * ===========================
 268  * List of available baudrates
 269  * ===========================
 270  */
 271 #define CFG_BAUDRATE_TABLE      \
 272                 { 600,    1200,   2400,    4800,    9600,    14400, \
 273                   19200,  28800,  38400,   56000,   57600,   115200 }
 274
 275 /*
 276  * ==================================================
 277  * MAC address/es, model and WPS pin offsets in FLASH
 278  * ==================================================
 279  */
 280 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 281     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 282     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 283     defined(CONFIG_FOR_COMFAST_CF_E530N)
 284         #define OFFSET_MAC_DATA_BLOCK           0x10000
 285         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x10000
 286         #define OFFSET_MAC_ADDRESS              0x00000
 287 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 288       defined(CONFIG_FOR_P2W_R602N)      ||\
 289       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 290       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 291       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 292         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 293         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 294         #define OFFSET_MAC_ADDRESS              0x000000
 295 #elif defined(CONFIG_FOR_TPLINK_WR802N)     ||\
 296       defined(CONFIG_FOR_TPLINK_WR810N)     ||\
 297       defined(CONFIG_FOR_TPLINK_WR820N_CN)  ||\
 298       defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
 299       defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
 300       defined(CONFIG_FOR_TPLINK_WR841N_V9)
 301         #define OFFSET_MAC_DATA_BLOCK           0x010000
 302         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 303         #define OFFSET_MAC_ADDRESS              0x00FC00
 304         #define OFFSET_ROUTER_MODEL             0x00FD00
 305         #define OFFSET_PIN_NUMBER               0x00FE00
 306 #elif defined(CONFIG_FOR_WALLYS_DR531)
 307         #define OFFSET_MAC_DATA_BLOCK           0x030000
 308         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 309         #define OFFSET_MAC_ADDRESS              0x00F810
 310 #endif
 311
 312 /*
 313  * =========================
 314  * Custom changes per device
 315  * =========================
 316  */
 317
 318 /*
 319  * Comfast CF-E520N and E320Nv2 are limited to 64 KB only,
 320  * disable some commands
 321  */
 322 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 323     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 324     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 325     defined(CONFIG_FOR_COMFAST_CF_E530N)
 326         #undef CONFIG_CMD_DHCP
 327         #undef CONFIG_CMD_LOADB
 328         #undef CONFIG_CMD_SNTP
 329 #endif
 330
 331 /*
 332  * ===========================
 333  * HTTP recovery configuration
 334  * ===========================
 335  */
 336 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 337
 338 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 339     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 340     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 341     defined(CONFIG_FOR_COMFAST_CF_E530N)
 342         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
 343 #endif
 344
 345 /* Firmware size limit */
 346 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 347     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 348     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 349     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 350     defined(CONFIG_FOR_TPLINK_WR802N)       ||\
 351     defined(CONFIG_FOR_TPLINK_WR810N)       ||\
 352     defined(CONFIG_FOR_TPLINK_WR820N_CN)    ||\
 353     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 354     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 355     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 356         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 357 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 358       defined(CONFIG_FOR_P2W_R602N)      ||\
 359       defined(CONFIG_FOR_WALLYS_DR531)   ||\
 360       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 361       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 362       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 363         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 364 #endif
 365
 366 /*
 367  * ========================
 368  * PLL/Clocks configuration
 369  * ========================
 370  */
 371 #if defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 372     defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 373     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 374         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
 375 #else
 376         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_650_400_200
 377 #endif
 378
 379 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 380     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 381     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 382     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 383     defined(CONFIG_FOR_TPLINK_WR802N)       ||\
 384     defined(CONFIG_FOR_TPLINK_WR810N)       ||\
 385     defined(CONFIG_FOR_TPLINK_WR820N_CN)    ||\
 386     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 387     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 388     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 389
 390         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 391         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 392
 393 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 394       defined(CONFIG_FOR_P2W_R602N)      ||\
 395       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 396       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 397       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 398
 399         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 400         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 401
 402 #elif defined(CONFIG_FOR_WALLYS_DR531)
 403
 404         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x30000
 405         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 406
 407 #endif
 408
 409 /*
 410  * ==================================
 411  * For upgrade scripts in environment
 412  * ==================================
 413  */
 414 #if !defined(CONFIG_FOR_COMFAST_CF_E314N)    &&\
 415     !defined(CONFIG_FOR_COMFAST_CF_E320N_V2) &&\
 416     !defined(CONFIG_FOR_COMFAST_CF_E520N)    &&\
 417     !defined(CONFIG_FOR_COMFAST_CF_E530N)    &&\
 418     !defined(CONFIG_FOR_P2W_CPE505N)         &&\
 419     !defined(CONFIG_FOR_P2W_R602N)           &&\
 420     !defined(CONFIG_FOR_WALLYS_DR531)        &&\
 421     !defined(CONFIG_FOR_YUNCORE_AP90Q)       &&\
 422     !defined(CONFIG_FOR_YUNCORE_CPE830)      &&\
 423     !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 424         #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
 425 #endif
 426
 427 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
 428     defined(CONFIG_FOR_P2W_R602N)      ||\
 429     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 430     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 431     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 432         #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F050000
 433 #endif
 434
 435 /*
 436  * ===================
 437  * Other configuration
 438  * ===================
 439  */
 440
 441 /* Cache lock for stack */
 442 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 443
 444 #endif /* _AP143_H */