u-boot/include/configs/ap143.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef _AP143_CONFIG_H
   6 #define _AP143_CONFIG_H
   7
   8 #include <config.h>
   9 #include <atheros.h>
  10 #include <soc/soc_common.h>
  11
  12 /*
  13  * GPIO configuration
  14  */
  15 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
  16         /* LEDs */
  17         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO13
  18
  19         /* Outputs, inputs */
  20         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  21         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO12
  22
  23         /* Initial states */
  24         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  25 #endif
  26
  27 /*
  28  * Miscellaneous configurable options
  29  */
  30 #ifndef CONFIG_BOOTDELAY
  31         #define CONFIG_BOOTDELAY        1
  32 #endif
  33
  34 #define CFG_LONGHELP
  35
  36 #define CONFIG_BAUDRATE                         115200
  37 #define CFG_BAUDRATE_TABLE                      { 600,    1200,   2400,    4800,    9600,    14400, \
  38                                                                           19200,  28800,  38400,   56000,   57600,   115200 }
  39
  40 #define CFG_ALT_MEMTEST
  41 #define CFG_HUSH_PARSER
  42 #define CFG_LONGHELP                                                                                                            /* undef to save memory      */
  43 #define CFG_PROMPT                      "uboot> "                                                                               /* Monitor Command Prompt    */
  44 #define CFG_PROMPT_HUSH_PS2     "> "
  45 #define CFG_CBSIZE                      1024                                                                                    /* Console I/O Buffer Size   */
  46 #define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)                              /* Print Buffer Size, was: def + 16 */
  47 #define CFG_MAXARGS                     16                                                                                              /* max number of command */
  48 #define CFG_MALLOC_LEN          512*1024                                                                                /* def: 128*1024 */
  49 #define CFG_BOOTPARAMS_LEN      512*1024                                                                                /* def: 128 */
  50 #define CFG_SDRAM_BASE          0x80000000                                                                              /* Cached addr */
  51 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x200000)                                             /* RAM test start = CFG_SDRAM_BASE + 2 MB */
  52 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001)    /* RAM test end   = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
  53 #define CFG_RX_ETH_BUFFER   16
  54
  55 #if defined(CONFIG_SILENT_CONSOLE)
  56         #define SILENT_ENV_VARIABLE     "silent=1\0"
  57 #else
  58         #define SILENT_ENV_VARIABLE     ""
  59 #endif
  60
  61 #define CFG_DCACHE_SIZE         32768
  62 #define CFG_ICACHE_SIZE         65536
  63 #define CFG_CACHELINE_SIZE      32
  64
  65 /*
  66  * FLASH and environment organization
  67  */
  68 #define CFG_MAX_FLASH_BANKS                     1
  69 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  70 #define CFG_FLASH_SECTOR_SIZE           64 * 1024
  71
  72 /*
  73  * We boot from this flash
  74  */
  75 #define CFG_FLASH_BASE                                  0x9F000000
  76 #ifdef COMPRESSED_UBOOT
  77         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  78         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  79 #endif
  80
  81 /*
  82  * The following #defines are needed to get flash environment right
  83  */
  84 #define CFG_MONITOR_BASE        TEXT_BASE
  85 #define CFG_MONITOR_LEN         (192 << 10)
  86
  87 /*
  88  * Default bootargs
  89  */
  90 #undef CONFIG_BOOTARGS
  91 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
  92         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
  93 #endif
  94
  95 /*
  96  * Other env default values
  97  */
  98 #undef CONFIG_BOOTFILE
  99 #define CONFIG_BOOTFILE                 "firmware.bin"
 100
 101 #undef CONFIG_LOADADDR
 102 #define CONFIG_LOADADDR                 0x80800000
 103
 104 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 105         #define CFG_LOAD_ADDR                    0x9F020000
 106         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 107         #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 108 #endif
 109
 110 #define CONFIG_IPADDR                   192.168.1.1
 111 #define CONFIG_SERVERIP                 192.168.1.2
 112
 113 /*
 114  * PLL/Clocks configuration
 115  */
 116 #ifdef CFG_HZ
 117         #undef  CFG_HZ
 118 #endif
 119 #define CFG_HZ  bd->bi_cfg_hz
 120
 121 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 122         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 123         #define CFG_HZ_FALLBACK         (550000000LU/2)
 124 #endif
 125
 126 /*
 127  * For PLL/clocks recovery use reset button by default
 128  */
 129 #ifdef GPIO_RST_BUTTON_BIT
 130         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         GPIO_RST_BUTTON_BIT
 131 #endif
 132
 133 #ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW
 134         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 135 #endif
 136
 137 /*
 138  * Address and size of Primary Environment Sector
 139  */
 140 #define CFG_ENV_IS_IN_FLASH     1
 141 #undef  CFG_ENV_IS_NOWHERE
 142
 143 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 144         #define CFG_ENV_ADDR            0x9F01EC00
 145         #define CFG_ENV_SIZE            0x1000
 146         #define CFG_ENV_SECT_SIZE       0x10000
 147 #endif
 148
 149 /*
 150  * Available commands
 151  */
 152 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 153         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 154                                                          CFG_CMD_DHCP   | \
 155                                                          CFG_CMD_PING   | \
 156                                                          CFG_CMD_FLASH  | \
 157                                                          CFG_CMD_NET    | \
 158                                                          CFG_CMD_RUN    | \
 159                                                          CFG_CMD_DATE   | \
 160                                                          CFG_CMD_SNTP   | \
 161                                                          CFG_CMD_ECHO   | \
 162                                                          CFG_CMD_BOOTD  | \
 163                                                          CFG_CMD_ITEST  | \
 164                                                          CFG_CMD_ENV    | \
 165                                                          CFG_CMD_LOADB)
 166 #endif
 167
 168 // Enable NetConsole and custom NetConsole port
 169 #define CONFIG_NETCONSOLE
 170 #define CONFIG_NETCONSOLE_PORT  6666
 171
 172 /*modify from 0x4138 to 0x40c3, ddr refresh interval: 12uS to 7.8uS. by wkp
 173   from Li Guanwen, 30Dec14. */
 174 //#define CFG_DDR_REFRESH_VAL           0x40c3 (??????????????????)
 175 #define CFG_DDR_REFRESH_VAL             0x4138
 176
 177 /*
 178  * Web Failsafe configuration
 179  */
 180 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 181 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 182
 183 // Firmware partition offset
 184 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 185         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 186 #endif
 187
 188 // U-Boot partition size
 189 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 190
 191 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 192 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 193         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 194         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 195 #endif
 196
 197 // ART partition size
 198 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 199
 200 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 201 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 202 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 203         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 204 #endif
 205
 206 // progress state info
 207 #define WEBFAILSAFE_PROGRESS_START                              0
 208 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 209 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 210 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 211 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 212
 213 // update type
 214 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 215 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 216 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 217
 218 /*-----------------------------------------------------------------------*/
 219
 220 /*
 221  * Additional environment variables for simple upgrades
 222  */
 223 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 224                                                                         "uboot_name=uboot.bin\0" \
 225                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 226                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 227                                                                         "uboot_upg=" \
 228                                                                                 "if ping $serverip; then " \
 229                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 230                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 231                                                                                         "tftp $loadaddr $uboot_name && " \
 232                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 233                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 234                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 235                                                                                                 "echo OK!; " \
 236                                                                                         "else " \
 237                                                                                                 "echo ERROR! Wrong file size!; " \
 238                                                                                         "fi; " \
 239                                                                                 "else " \
 240                                                                                         "echo ERROR! Server not reachable!; " \
 241                                                                                 "fi\0" \
 242                                                                         SILENT_ENV_VARIABLE
 243
 244 /*
 245  * Cache lock for stack
 246  */
 247 #define CFG_INIT_SP_OFFSET                      0x1000
 248 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 249
 250 /* For Merlin, both PCI, PCI-E interfaces are valid */
 251 #define ATH_ART_PCICFG_OFFSET           12
 252 /* use eth1(LAN) as the net interface */
 253 #define CONFIG_AG7240_SPEPHY
 254 #define CONFIG_NET_MULTI
 255 #define CONFIG_PCI 1
 256 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 257         #define WLANCAL                                 0x9fff1000
 258         #define BOARDCAL                                0x9fff0000
 259 #endif
 260 #define CFG_MII0_RMII                           1
 261 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 262
 263 #undef DEBUG
 264
 265 /* MAC address, model and PIN number offsets in FLASH */
 266 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 267         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 268         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 269         #define OFFSET_MAC_ADDRESS                              0x00FC00
 270         #define OFFSET_ROUTER_MODEL                             0x00FD00
 271         #define OFFSET_PIN_NUMBER                               0x00FE00
 272 #endif
 273
 274 /*
 275  * PLL and clocks configurations from FLASH
 276  */
 277 #if defined(CONFIG_FOR_TPLINK_WR820N_CH)
 278         /*
 279          * All TP-Link routers have a lot of unused space
 280          * in FLASH, in second 64 KiB block.
 281          * We will store there PLL and CLOCK
 282          * registers configuration.
 283          */
 284         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 285         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 286
 287 #endif
 288
 289 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 290         /* Use last 32 bytes */
 291         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 292                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 293                                                                                                          0x0000FFE0)
 294 #endif
 295
 296 #include <cmd_confdefs.h>
 297
 298 #endif  /* __AP143_CONFIG_H */