2 * This file contains the configuration parameters for the AP121 (AR9331) board.
8 #include <configs/ar7240.h>
12 * FLASH and environment organization
14 #define CFG_MAX_FLASH_BANKS 1
15 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
18 * We boot from this flash
20 #define CFG_FLASH_BASE 0x9F000000
21 #ifdef COMPRESSED_UBOOT
22 #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
23 #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
27 * The following #defines are needed to get flash environment right
29 #define CFG_MONITOR_BASE TEXT_BASE
30 #define CFG_MONITOR_LEN (192 << 10)
35 #undef CONFIG_BOOTARGS
37 #if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \
38 defined(CONFIG_FOR_TPLINK_WR720N_V3) || \
39 defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
40 defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \
41 defined(CONFIG_FOR_TPLINK_MR10U_V1) || \
42 defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
43 defined(CONFIG_FOR_TPLINK_MR3220_V2)
45 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
47 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
49 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)"
51 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
53 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
55 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
57 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)"
62 * Other env default values
64 #undef CONFIG_BOOTFILE
65 #define CONFIG_BOOTFILE "firmware.bin"
67 #undef CONFIG_LOADADDR
68 #define CONFIG_LOADADDR 0x80800000
70 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
71 #define CFG_LOAD_ADDR 0x9F080000
72 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
73 #define CFG_LOAD_ADDR 0x9F050000
75 #define CFG_LOAD_ADDR 0x9F020000
78 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
79 #define CONFIG_BOOTCOMMAND "bootm 0x9F080000"
80 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
81 #define CONFIG_BOOTCOMMAND "bootm 0x9F050000"
83 #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
86 #define CONFIG_IPADDR 192.168.1.1
87 #define CONFIG_SERVERIP 192.168.1.2
91 #undef CPU_PLL_CONFIG_VAL1
92 #undef CPU_CLK_CONTROL_VAL2
94 // CPU-RAM-AHB frequency setting
95 #define CFG_PLL_FREQ CFG_PLL_400_400_200
98 * MIPS32 24K Processor Core Family Software User's Manual
100 * 6.2.9 Count Register (CP0 Register 9, Select 0)
101 * The Count register acts as a timer, incrementing at a constant
102 * rate, whether or not an instruction is executed, retired, or
103 * any forward progress is made through the pipeline. The counter
104 * increments every other clock, if the DC bit in the Cause register
107 * Since the count is incremented every other tick, divide by 2
108 * XXX derive this from CFG_PLL_FREQ
113 * CPU_PLL_DITHER_FRAC_VAL
115 * Value written into CPU PLL Dither FRAC Register (PLL_DITHER_FRAC)
117 * bits 0..9 NFRAC_MAX => 1000 (0x3E8)
118 * bits 10..13 NFRAC_MIN => 0 (minimum value is used)
119 * bits 20..29 NFRAC_STEP => 1
122 #define CPU_PLL_DITHER_FRAC_VAL 0x001003e8
125 * CPU_PLL_SETTLE_TIME_VAL
127 * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2)
129 * bits 0..11 SETTLE_TIME => 580 (0x352)
132 #if CONFIG_40MHZ_XTAL_SUPPORT
133 #define CPU_PLL_SETTLE_TIME_VAL 0x00000550
135 #define CPU_PLL_SETTLE_TIME_VAL 0x00000352
139 * CPU_CLK_CONTROL_VAL1
140 * CPU_CLK_CONTROL_VAL2
142 * Values written into CPU Clock Control Register CLOCK_CONTROL
143 * with PLL bypass disabled
145 * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0)
146 * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
147 * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
148 * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
153 * CPU_PLL_CONFIG_VAL1
154 * CPU_PLL_CONFIG_VAL2
156 * In CPU_PLL_CONFIG_VAL1 bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
157 * In CPU_PLL_CONFIG_VAL2 bit 30 is unset
159 * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG)
161 * bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20)
162 * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at valuse different than 1 (maybe need to change other dividers?)]
163 * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values]
164 * bits 23..25 (3bit) OUTDIV (Define the ratio betwee VCO output and PLL output => 1 (0x1)
165 * VCOOUT * (1/2^OUTDIV) = PLLOUT)
169 * = PLL CALCULATION (guess) =============
170 * PLL = (25 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz
172 * PLL = (40 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz
174 * CPU = PLL / CPU_POST_DIV
175 * DDR = PLL / DDR_POST_DIV
176 * AHB = PLL / AHB_POST_DIV
183 * Value written into SPI Control (SPI_CONTROL) register
185 * bits 0..5 (6bit) CLOCK_DIVIDER (Specifies the clock divider setting. Actual clock frequency would be (AHB_CLK / ((CLOCK_DIVIDER+1)*2)) )
186 * bits 6 (1bit) REMAP_DISABLE (Remaps 4 MB space over unless explicitly disabled by setting this bit to 1. If set to 1, 16 MB is accessible.)
190 #if (CFG_PLL_FREQ == CFG_PLL_400_400_200)
192 #define CFG_HZ (400000000LU/2)
194 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
195 #define CPU_CLK_CONTROL_VAL1 0x00018004
196 #define CPU_CLK_CONTROL_VAL2 0x00008000
198 #if CONFIG_40MHZ_XTAL_SUPPORT
199 // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz)
203 #define CPU_PLL_CONFIG_VAL1 0x40815000
204 #define CPU_PLL_CONFIG_VAL2 0x00815000
206 // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz)
210 #define CPU_PLL_CONFIG_VAL1 0x40818000
211 #define CPU_PLL_CONFIG_VAL2 0x00818000
214 // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
215 #define AR7240_SPI_CONTROL 0x42
217 #elif (CFG_PLL_FREQ == CFG_PLL_412_412_206)
219 #define CFG_HZ (412500000LU/2)
221 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
222 #define CPU_CLK_CONTROL_VAL1 0x00018004
223 #define CPU_CLK_CONTROL_VAL2 0x00008000
225 // DIV_INT = 33 (25 MHz * 33/2 = 412,5 MHz)
229 #define CPU_PLL_CONFIG_VAL1 0x40818400
230 #define CPU_PLL_CONFIG_VAL2 0x00818400
232 // CLOCK_DIVIDER = 2 (SPI clock = 206,25 / 6 ~ 34,4 MHz)
233 #define AR7240_SPI_CONTROL 0x42
235 #elif (CFG_PLL_FREQ == CFG_PLL_425_425_212)
237 #define CFG_HZ (425000000LU/2)
239 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
240 #define CPU_CLK_CONTROL_VAL1 0x00018004
241 #define CPU_CLK_CONTROL_VAL2 0x00008000
243 // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz)
247 #define CPU_PLL_CONFIG_VAL1 0x40818800
248 #define CPU_PLL_CONFIG_VAL2 0x00818800
250 // CLOCK_DIVIDER = 2 (SPI clock = 212,5 / 6 ~ 35,4 MHz)
251 #define AR7240_SPI_CONTROL 0x42
253 #elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
255 #define CFG_HZ (437500000LU/2)
257 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
258 #define CPU_CLK_CONTROL_VAL1 0x00018004
259 #define CPU_CLK_CONTROL_VAL2 0x00008000
261 // DIV_INT = 35 (25 MHz * 35/2 = 437,5 MHz)
265 #define CPU_PLL_CONFIG_VAL1 0x40818C00
266 #define CPU_PLL_CONFIG_VAL2 0x00818C00
268 // CLOCK_DIVIDER = 2 (SPI clock = 218,75 / 6 ~ 36,5 MHz)
269 #define AR7240_SPI_CONTROL 0x42
272 #elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
274 #define CFG_HZ (450000000LU/2)
276 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
277 #define CPU_CLK_CONTROL_VAL1 0x00018004
278 #define CPU_CLK_CONTROL_VAL2 0x00008000
280 // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz)
284 #define CPU_PLL_CONFIG_VAL1 0x40819000
285 #define CPU_PLL_CONFIG_VAL2 0x00819000
287 // CLOCK_DIVIDER = 3 (SPI clock = 225 / 6 ~ 37,5 MHz)
288 #define AR7240_SPI_CONTROL 0x42
290 #elif (CFG_PLL_FREQ == CFG_PLL_462_462_231)
292 #define CFG_HZ (462500000LU/2)
294 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
295 #define CPU_CLK_CONTROL_VAL1 0x00018004
296 #define CPU_CLK_CONTROL_VAL2 0x00008000
298 // DIV_INT = 37 (25 MHz * 37/2 = 462,5 MHz)
302 #define CPU_PLL_CONFIG_VAL1 0x40819400
303 #define CPU_PLL_CONFIG_VAL2 0x00819400
305 // CLOCK_DIVIDER = 3 (SPI clock = 231,25 / 6 ~ 38,5 MHz)
306 #define AR7240_SPI_CONTROL 0x42
308 #elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
310 #define CFG_HZ (475000000LU/2)
312 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
313 #define CPU_CLK_CONTROL_VAL1 0x00018004
314 #define CPU_CLK_CONTROL_VAL2 0x00008000
316 // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz)
320 #define CPU_PLL_CONFIG_VAL1 0x40819800
321 #define CPU_PLL_CONFIG_VAL2 0x00819800
323 // CLOCK_DIVIDER = 3 (SPI clock = 237,5 / 6 ~ 39,6 MHz)
324 #define AR7240_SPI_CONTROL 0x42
326 #elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
328 #define CFG_HZ (487500000LU/2)
330 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
331 #define CPU_CLK_CONTROL_VAL1 0x00018004
332 #define CPU_CLK_CONTROL_VAL2 0x00008000
334 // DIV_INT = 39 (25 MHz * 39/2 = 487,5 MHz)
338 #define CPU_PLL_CONFIG_VAL1 0x40819C00
339 #define CPU_PLL_CONFIG_VAL2 0x00819C00
341 // CLOCK_DIVIDER = 3 (SPI clock = 243,75 / 8 ~ 30,5 MHz)
342 #define AR7240_SPI_CONTROL 0x43
345 #elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
347 #define CFG_HZ (500000000LU/2)
349 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
350 #define CPU_CLK_CONTROL_VAL1 0x00018004
351 #define CPU_CLK_CONTROL_VAL2 0x00008000
353 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz)
357 #define CPU_PLL_CONFIG_VAL1 0x4081A000
358 #define CPU_PLL_CONFIG_VAL2 0x0081A000
360 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
361 #define AR7240_SPI_CONTROL 0x43
363 #elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
365 #define CFG_HZ (500000000LU/2)
367 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
368 #define CPU_CLK_CONTROL_VAL1 0x00018404
369 #define CPU_CLK_CONTROL_VAL2 0x00008400
371 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz)
375 #define CPU_PLL_CONFIG_VAL1 0x4081A000
376 #define CPU_PLL_CONFIG_VAL2 0x0081A000
378 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
379 #define AR7240_SPI_CONTROL 0x43
381 #elif (CFG_PLL_FREQ == CFG_PLL_562_281_140)
383 #define CFG_HZ (562500000LU/2)
385 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
386 #define CPU_CLK_CONTROL_VAL1 0x00018404
387 #define CPU_CLK_CONTROL_VAL2 0x00018400
389 // DIV_INT = 45 (25 MHz * 45/2 = 562,5 MHz)
393 #define CPU_PLL_CONFIG_VAL1 0x4081B400
394 #define CPU_PLL_CONFIG_VAL2 0x0081B400
396 // CLOCK_DIVIDER = 1 (SPI clock = 140,625 / 4 ~ 35,2 MHz)
397 #define AR7240_SPI_CONTROL 0x41
399 #elif (CFG_PLL_FREQ == CFG_PLL_525_262_131)
401 #define CFG_HZ (525000000LU/2)
403 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
404 #define CPU_CLK_CONTROL_VAL1 0x00018404
405 #define CPU_CLK_CONTROL_VAL2 0x00018400
407 // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz)
411 #define CPU_PLL_CONFIG_VAL1 0x4081A800
412 #define CPU_PLL_CONFIG_VAL2 0x0081A800
414 // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz)
415 #define AR7240_SPI_CONTROL 0x41
420 * Cache lock for stack
422 #define CFG_INIT_SP_OFFSET 0x1000
425 * Address and size of Primary Environment Sector
427 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
428 #define CFG_ENV_IS_IN_FLASH 1
429 #undef CFG_ENV_IS_NOWHERE
431 #undef CFG_ENV_IS_IN_FLASH
432 #define CFG_ENV_IS_NOWHERE 1
435 #define CFG_ENV_ADDR 0x9F040000
436 #define CFG_ENV_SIZE 0x10000
441 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
442 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_DATE | CFG_CMD_IMI )
443 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
444 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_RUN | CFG_CMD_DATE | CFG_CMD_IMI | CFG_CMD_SNTP)
446 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_PING )
449 // Enable NetConsole and custom NetConsole port
450 #define CONFIG_NETCONSOLE
451 #define CONFIG_NETCONSOLE_PORT 6666
453 /* DDR init values */
454 #if CONFIG_40MHZ_XTAL_SUPPORT
455 #define CFG_DDR_REFRESH_VAL 0x4270
457 #define CFG_DDR_REFRESH_VAL 0x4186
460 #define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
461 #define CFG_DDR_MODE_VAL_INIT 0x133
463 #ifdef LOW_DRIVE_STRENGTH
464 #define CFG_DDR_EXT_MODE_VAL 0x2
466 #define CFG_DDR_EXT_MODE_VAL 0x0
469 #define CFG_DDR_MODE_VAL 0x33
470 #define CFG_DDR_TRTW_VAL 0x1f
471 #define CFG_DDR_TWTR_VAL 0x1e
473 //#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0
474 #define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1
475 #define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff
476 #define CFG_DDR_TAP0_VAL 0x8
477 #define CFG_DDR_TAP1_VAL 0x9
479 /* DDR2 Init values */
480 #define CFG_DDR2_EXT_MODE_VAL 0x402
482 #define CONFIG_NET_MULTI
484 /* choose eth1 first for tftpboot interface added by ZJin, 110328 */
485 #define CONFIG_AG7240_SPEPHY
488 * Web Failsafe configuration
490 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
492 // U-Boot partition size and offset
493 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
495 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
496 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024)
497 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
498 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (256 * 1024)
500 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024)
503 // Firmware partition offset
504 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
505 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x80000
506 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
507 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
509 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
512 // ART partition size and offset
513 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
514 #define WEBFAILSAFE_UPLOAD_ART_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x10000
517 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
519 // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
520 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
521 // D-Link DIR-505: 64k(U-Boot),64k(ART),64k(MAC),64k(NVRAM),256k(Language)
522 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (512 * 1024)
523 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
524 // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART)
525 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
527 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
528 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
531 // progress state info
532 #define WEBFAILSAFE_PROGRESS_START 0
533 #define WEBFAILSAFE_PROGRESS_TIMEOUT 1
534 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
535 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
536 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
539 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
540 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
541 #define WEBFAILSAFE_UPGRADE_TYPE_ART 2
543 /*-----------------------------------------------------------------------*/
545 #define CFG_ATHRS26_PHY 1
546 #define CFG_AG7240_NMACS 2
547 #define CFG_MII0_RMII 1
548 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
551 #define milisecdelay(_x) udelay((_x) * 1000)
553 /* MAC address, model and PIN number offsets in FLASH */
554 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
555 // DIR-505 has two MAC addresses inside dedicated MAC partition
556 // They are stored in plain text... TODO: read/write MAC stored as plain text
557 //#define OFFSET_MAC_DATA_BLOCK 0x020000
558 //#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
559 //#define OFFSET_MAC_ADDRESS 0x000004
560 //#define OFFSET_MAC_ADDRESS2 0x000016
561 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
562 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
563 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
564 #define OFFSET_MAC_ADDRESS 0x000000 // Carambola 2 has two MAC addresses at the beginning of ART partition
565 #define OFFSET_MAC_ADDRESS2 0x000006
567 #define OFFSET_MAC_DATA_BLOCK 0x010000
568 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
569 #define OFFSET_MAC_ADDRESS 0x00FC00
572 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
573 !defined(CONFIG_FOR_DLINK_DIR505_A1)
574 #define OFFSET_ROUTER_MODEL 0x00FD00
577 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
578 defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
579 defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
580 defined(CONFIG_FOR_TPLINK_WR710N_V1)
581 #define OFFSET_PIN_NUMBER 0x00FE00
584 #include <cmd_confdefs.h>
586 #endif /* __CONFIG_H */