u-boot/include/configs/ap121.h

   1 /*
   2  * This file contains the configuration parameters for the AP121 (AR9331) board.
   3  */
   4
   5 #ifndef __CONFIG_H
   6 #define __CONFIG_H
   7
   8 #include <configs/ar7240.h>
   9 #include <config.h>
  10 #include <soc/soc_common.h>
  11
  12 /*
  13  * GPIO configuration
  14  */
  15 #if defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
  16         defined(CONFIG_FOR_TPLINK_WR710N_V1)
  17         /* LEDs */
  18         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO27
  19
  20         /* Outputs, inputs */
  21         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
  22         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
  23
  24         /* Initial states */
  25         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
  26
  27 #elif defined(CONFIG_FOR_TPLINK_MR10U_V1)
  28         /* LEDs */
  29         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO27
  30
  31         /* Outputs, inputs */
  32         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
  33         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
  34
  35         /* Initial states */
  36         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
  37
  38 #elif defined(CONFIG_FOR_TPLINK_WR720N_V3)
  39         /* LEDs */
  40         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO27
  41
  42         /* Outputs, inputs */
  43         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
  44         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO11 | GPIO18 | GPIO20)
  45
  46         /* Initial states */
  47         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
  48
  49 #elif defined(CONFIG_FOR_TPLINK_MR13U_V1)
  50         /* LEDs */
  51         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO27
  52
  53         /* Outputs, inputs */
  54         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
  55         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO6 | GPIO7 | GPIO11)
  56
  57         /* Initial states */
  58         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
  59
  60 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
  61         /* LEDs */
  62         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO26 | GPIO27)
  63
  64         /* Outputs, inputs */
  65         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  66         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
  67
  68         /* Initial states */
  69         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  70
  71 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
  72         /* LEDs */
  73         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO27
  74
  75         /* Outputs, inputs */
  76         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  77         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
  78
  79         /* Initial states */
  80         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  81
  82 #elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
  83         /* LEDs */
  84         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             GPIO0
  85         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO17 | GPIO26 | GPIO27)
  86
  87         /* Outputs, inputs */
  88         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
  89                                                                                                          CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI |\
  90                                                                                                          GPIO8)
  91         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO11 | GPIO18 | GPIO20)
  92
  93         /* Initial states */
  94         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
  95         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
  96
  97 #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
  98         /* LEDs */
  99         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO17 | GPIO26 | GPIO27)
 100
 101         /* Outputs, inputs */
 102         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
 103         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
 104
 105         /* Initial states */
 106         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
 107         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 108
 109 #elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
 110         /* LEDs */
 111         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             (GPIO0  | GPIO1 | GPIO13 | GPIO14 | GPIO15 | GPIO16)
 112         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO17 | GPIO27)
 113
 114         /* Outputs, inputs */
 115         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
 116                                                                                                          CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
 117         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO11 | GPIO26)
 118
 119         /* Initial states */
 120         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
 121         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 122
 123 #elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
 124         /* LEDs */
 125         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             (GPIO0  | GPIO1 | GPIO13 | GPIO14 | GPIO15 | GPIO16 | GPIO26)
 126         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO17 | GPIO27)
 127
 128         /* Outputs, inputs */
 129         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
 130                                                                                                          CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI |\
 131                                                                                                          GPIO8)
 132         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO11)
 133
 134         /* Initial states */
 135         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
 136         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 137
 138 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 139         /* LEDs */
 140         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO13 | GPIO15 | GPIO17 | GPIO27)
 141
 142         /* Outputs, inputs */
 143         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
 144         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO11)
 145
 146         /* Initial states */
 147         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
 148
 149 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 150         /* LEDs */
 151         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             (GPIO13 | GPIO14)
 152         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO0
 153
 154         /* Outputs, inputs */
 155         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
 156                                                                                                          CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
 157         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
 158
 159         /* Initial states */
 160         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
 161         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 162
 163 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 164           defined(CONFIG_FOR_MESH_POTATO_V2)
 165         /* LEDs */
 166         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             (GPIO0  | GPIO28)
 167         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO13 | GPIO17)
 168
 169         /* Outputs, inputs */
 170         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
 171                                                                                                          CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
 172         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
 173
 174         /* Initial states */
 175         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
 176         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 177
 178 #elif defined(CONFIG_FOR_GL_INET)
 179         /* LEDs */
 180         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI             (GPIO0 | GPIO13)
 181
 182         /* Outputs, inputs */
 183         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 184         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO11
 185
 186         /* Initial states */
 187         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
 188
 189 #endif
 190
 191 /*
 192  * FLASH and environment organization
 193  */
 194 #define CFG_MAX_FLASH_BANKS                     1
 195 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
 196
 197 /*
 198  * We boot from this flash
 199  */
 200 #define CFG_FLASH_BASE                                  0x9F000000
 201 #ifdef COMPRESSED_UBOOT
 202         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
 203         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
 204 #endif
 205
 206 /*
 207  * The following #defines are needed to get flash environment right
 208  */
 209 #define CFG_MONITOR_BASE        TEXT_BASE
 210 #define CFG_MONITOR_LEN         (192 << 10)
 211
 212 /*
 213  * Default bootargs
 214  */
 215 #undef CONFIG_BOOTARGS
 216
 217 #if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \
 218         defined(CONFIG_FOR_TPLINK_WR720N_V3) || \
 219         defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
 220         defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \
 221         defined(CONFIG_FOR_TPLINK_MR10U_V1) || \
 222         defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
 223         defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
 224         defined(CONFIG_FOR_TPLINK_MR13U_V1) || \
 225         defined(CONFIG_FOR_GL_INET)
 226
 227         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
 228
 229 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
 230
 231         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)"
 232
 233 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 234
 235         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
 236
 237 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 238
 239         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
 240
 241 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 242
 243         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(ART)"
 244
 245 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 246
 247         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)"
 248
 249 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 250       defined(CONFIG_FOR_MESH_POTATO_V2)
 251
 252         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(ART)"
 253
 254 #endif
 255
 256 /*
 257  * Other env default values
 258  */
 259 #undef CONFIG_BOOTFILE
 260 #define CONFIG_BOOTFILE                 "firmware.bin"
 261
 262 #undef CONFIG_LOADADDR
 263 #define CONFIG_LOADADDR                 0x80800000
 264
 265 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 266         #define CFG_LOAD_ADDR                    0x9F080000
 267         #define UPDATE_SCRIPT_FW_ADDR   "0x9F080000"
 268 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 269         #define CFG_LOAD_ADDR                    0x9F050000
 270         #define UPDATE_SCRIPT_FW_ADDR   "0x9F050000"
 271 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 272       defined(CONFIG_FOR_MESH_POTATO_V2)
 273         #define CFG_LOAD_ADDR                    0x9F040000
 274         #define UPDATE_SCRIPT_FW_ADDR   "0x9F040000"
 275 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 276         #define CFG_LOAD_ADDR                    0x9F030000
 277         #define UPDATE_SCRIPT_FW_ADDR   "0x9F030000"
 278 #else
 279         #define CFG_LOAD_ADDR                    0x9F020000
 280         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 281 #endif
 282
 283 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 284         #define CONFIG_BOOTCOMMAND "bootm 0x9F080000"
 285 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 286         #define CONFIG_BOOTCOMMAND "bootm 0x9F050000"
 287 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 288       defined(CONFIG_FOR_MESH_POTATO_V2)
 289         #define CONFIG_BOOTCOMMAND "bootm 0x9F040000"
 290 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 291         #define CONFIG_BOOTCOMMAND "bootm 0x9F030000"
 292 #else
 293         #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
 294 #endif
 295
 296 /*
 297  * Dragino 2 uses different IP addresses
 298  */
 299 #if defined(CONFIG_FOR_DRAGINO_V2)
 300         #define CONFIG_IPADDR           192.168.255.1
 301         #define CONFIG_SERVERIP         192.168.255.2
 302 #else
 303         #define CONFIG_IPADDR           192.168.1.1
 304         #define CONFIG_SERVERIP         192.168.1.2
 305 #endif
 306
 307 /*
 308  * Dragino 2 uses different prompt
 309  */
 310 #if defined(CONFIG_FOR_DRAGINO_V2) || \
 311     defined(CONFIG_FOR_MESH_POTATO_V2)
 312         #if defined(CFG_PROMPT)
 313                 #undef CFG_PROMPT
 314         #endif
 315         #define CFG_PROMPT "dr_boot> "
 316 #endif
 317
 318 #if defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 319         #if defined(CFG_PROMPT)
 320                 #undef CFG_PROMPT
 321         #endif
 322         #define CFG_PROMPT "BSB> "
 323 #endif
 324
 325 /*
 326  * PLL/Clocks configuration
 327  */
 328 #ifdef CFG_HZ
 329         #undef  CFG_HZ
 330 #endif
 331 #define CFG_HZ  bd->bi_cfg_hz
 332
 333 #define CONFIG_QCA_PLL          QCA_PLL_PRESET_400_400_200
 334
 335
 336 /*
 337  * For PLL/clocks recovery use reset button by default
 338  */
 339 #ifdef CONFIG_GPIO_RESET_BTN
 340         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 341 #endif
 342
 343 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 344         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 345 #endif
 346
 347 /*
 348  * Cache lock for stack
 349  */
 350 #define CFG_INIT_SP_OFFSET              0x1000
 351
 352 /*
 353  * Address and size of Primary Environment Sector
 354  */
 355 #if !defined(CONFIG_FOR_DLINK_DIR505_A1)
 356         #define CFG_ENV_IS_IN_FLASH     1
 357         #undef  CFG_ENV_IS_NOWHERE
 358 #else
 359         #undef  CFG_ENV_IS_IN_FLASH
 360         #define CFG_ENV_IS_NOWHERE      1
 361 #endif
 362
 363 #if defined(CONFIG_FOR_DRAGINO_V2) || \
 364         defined(CONFIG_FOR_MESH_POTATO_V2)
 365         #define CFG_ENV_ADDR            0x9F030000
 366         #define CFG_ENV_SIZE            0x8000
 367         #define CFG_ENV_SECT_SIZE       0x10000
 368 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 369         #define CFG_ENV_ADDR            0x9F040000
 370         #define CFG_ENV_SIZE            0x8000
 371         #define CFG_ENV_SECT_SIZE       0x10000
 372 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 373         #define CFG_ENV_ADDR            0x9F020000
 374         #define CFG_ENV_SIZE            0x8000
 375         #define CFG_ENV_SECT_SIZE       0x10000
 376 #else
 377         #define CFG_ENV_ADDR            0x9F01EC00
 378         #define CFG_ENV_SIZE            0x1000
 379         #define CFG_ENV_SECT_SIZE       0x10000
 380 #endif
 381
 382 /*
 383  * Available commands
 384  */
 385 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 386
 387         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 388                                                          CFG_CMD_PING   | \
 389                                                          CFG_CMD_FLASH  | \
 390                                                          CFG_CMD_NET    | \
 391                                                          CFG_CMD_RUN    | \
 392                                                          CFG_CMD_DATE   | \
 393                                                          CFG_CMD_ECHO   | \
 394                                                          CFG_CMD_BOOTD  | \
 395                                                          CFG_CMD_ITEST  | \
 396                                                          CFG_CMD_IMI)
 397
 398 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
 399       defined(CONFIG_FOR_DRAGINO_V2) || \
 400       defined(CONFIG_FOR_MESH_POTATO_V2) || \
 401       defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 402
 403         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 404                                                          CFG_CMD_DHCP   | \
 405                                                          CFG_CMD_PING   | \
 406                                                          CFG_CMD_FLASH  | \
 407                                                          CFG_CMD_NET    | \
 408                                                          CFG_CMD_RUN    | \
 409                                                          CFG_CMD_DATE   | \
 410                                                          CFG_CMD_SNTP   | \
 411                                                          CFG_CMD_ECHO   | \
 412                                                          CFG_CMD_BOOTD  | \
 413                                                          CFG_CMD_ITEST  | \
 414                                                          CFG_CMD_IMI    | \
 415                                                          CFG_CMD_ENV    | \
 416                                                          CFG_CMD_LOADB)
 417
 418 #else
 419
 420         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 421                                                          CFG_CMD_DHCP   | \
 422                                                          CFG_CMD_PING   | \
 423                                                          CFG_CMD_FLASH  | \
 424                                                          CFG_CMD_NET    | \
 425                                                          CFG_CMD_RUN    | \
 426                                                          CFG_CMD_DATE   | \
 427                                                          CFG_CMD_SNTP   | \
 428                                                          CFG_CMD_ECHO   | \
 429                                                          CFG_CMD_BOOTD  | \
 430                                                          CFG_CMD_ITEST  | \
 431                                                          CFG_CMD_ENV    | \
 432                                                          CFG_CMD_LOADB)
 433
 434 #endif
 435
 436 // Enable NetConsole and custom NetConsole port
 437 #define CONFIG_NETCONSOLE
 438 #define CONFIG_NETCONSOLE_PORT  6666
 439
 440 #define CONFIG_NET_MULTI
 441
 442 /* choose eth1 first for tftpboot interface added by ZJin, 110328 */
 443 #define CONFIG_AG7240_SPEPHY
 444
 445 /*
 446  * Web Failsafe configuration
 447  */
 448 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                                  CONFIG_LOADADDR
 449
 450 // U-Boot partition size and offset
 451 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                                CFG_FLASH_BASE
 452 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES                  (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 453
 454 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 455         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x10000"
 456         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 457 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 458         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x40000"
 459         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 460 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 461       defined(CONFIG_FOR_MESH_POTATO_V2)
 462         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x30000"
 463         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 464 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 465         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x20000"
 466         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
 467 #else
 468         // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 469         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 470         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 471 #endif
 472
 473 // Firmware partition offset
 474 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 475         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x80000
 476 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 477         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
 478 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 479       defined(CONFIG_FOR_MESH_POTATO_V2)
 480         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x40000
 481 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 482         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x30000
 483 #else
 484         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 485 #endif
 486
 487 // ART partition size and offset
 488 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 489         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS                          WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x10000
 490 #endif
 491
 492 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES                    (64 * 1024)
 493
 494 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 495 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 496         // D-Link DIR-505: 64k(U-Boot),64k(ART),64k(MAC),64k(NVRAM),256k(Language)
 497         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (512 * 1024)
 498 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 499         // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART)
 500         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 501 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 502       defined(CONFIG_FOR_MESH_POTATO_V2)
 503         // Dragino 2: 192k(U-Boot),64k(U-Boot env),64k(ART)
 504         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (320 * 1024)
 505 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 506         // GS-Oolite v1: 128k(U-Boot + MAC),64k(ART)
 507         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 508 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 509         // Black Swift board: 128k(U-Boot),64k(U-Boot env),64k(ART)
 510         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 511 #else
 512         // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 513         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 514 #endif
 515
 516 // progress state info
 517 #define WEBFAILSAFE_PROGRESS_START                              0
 518 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 519 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 520 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 521 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 522
 523 // update type
 524 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 525 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 526 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 527
 528 /*-----------------------------------------------------------------------*/
 529
 530 /*
 531  * Additional environment variables for simple upgrades
 532  */
 533 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 534                                                                         "uboot_name=uboot.bin\0" \
 535                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 536                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 537                                                                         "uboot_upg=" \
 538                                                                                 "if ping $serverip; then " \
 539                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 540                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 541                                                                                         "tftp $loadaddr $uboot_name && " \
 542                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 543                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 544                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 545                                                                                                 "echo OK!; " \
 546                                                                                         "else " \
 547                                                                                                 "echo ERROR! Wrong file size!; " \
 548                                                                                         "fi; " \
 549                                                                                 "else " \
 550                                                                                         "echo ERROR! Server not reachable!; " \
 551                                                                                 "fi\0" \
 552                                                                         "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \
 553                                                                         "firmware_name=firmware.bin\0" \
 554                                                                         "firmware_upg=" \
 555                                                                                 "if ping $serverip; then " \
 556                                                                                         "tftp $loadaddr $firmware_name && " \
 557                                                                                         "erase $firmware_addr +$filesize && " \
 558                                                                                         "cp.b $loadaddr $firmware_addr $filesize && " \
 559                                                                                         "echo OK!; " \
 560                                                                                 "else " \
 561                                                                                         "echo ERROR! Server not reachable!; " \
 562                                                                                 "fi\0" \
 563                                                                         SILENT_ENV_VARIABLE
 564
 565 #define CFG_ATHRS26_PHY                         1
 566 #define CFG_AG7240_NMACS                        2
 567 #define CFG_MII0_RMII                           1
 568 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 569
 570 #undef DEBUG
 571
 572 /* MAC address, model and PIN number offsets in FLASH */
 573 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 574         // DIR-505 has two MAC addresses inside dedicated MAC partition
 575         // They are stored in plain text... TODO: read/write MAC stored as plain text
 576         //#define OFFSET_MAC_DATA_BLOCK                 0x020000
 577         //#define OFFSET_MAC_DATA_BLOCK_LENGTH  0x010000
 578         //#define OFFSET_MAC_ADDRESS                            0x000004
 579         //#define OFFSET_MAC_ADDRESS2                           0x000016
 580 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
 581       defined(CONFIG_FOR_DRAGINO_V2) || \
 582       defined(CONFIG_FOR_MESH_POTATO_V2)
 583         // Carambola 2 and Dragino 2 have two MAC addresses at the beginning of ART partition
 584         #define OFFSET_MAC_DATA_BLOCK                   0xFF0000
 585         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 586         #define OFFSET_MAC_ADDRESS                              0x000000
 587         #define OFFSET_MAC_ADDRESS2                             0x000006
 588 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 589         // GS-OOlite has only one MAC, inside second block
 590         // It's some kind of TP-Link clone
 591         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 592         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 593         #define OFFSET_MAC_ADDRESS                              0x00FC00
 594 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 595         // Black Swift board has only one MAC address at the beginning of ART partition
 596         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 597         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 598         #define OFFSET_MAC_ADDRESS              0x000000
 599 #else
 600         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 601         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 602         #define OFFSET_MAC_ADDRESS                              0x00FC00
 603 #endif
 604
 605 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
 606         !defined(CONFIG_FOR_DLINK_DIR505_A1)     && \
 607         !defined(CONFIG_FOR_GS_OOLITE_V1_DEV)    && \
 608         !defined(CONFIG_FOR_DRAGINO_V2)          && \
 609         !defined(CONFIG_FOR_MESH_POTATO_V2)      && \
 610         !defined(CONFIG_FOR_GL_INET)             && \
 611         !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 612 #define OFFSET_ROUTER_MODEL                                     0x00FD00
 613 #endif
 614
 615 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
 616         defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
 617         defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
 618         defined(CONFIG_FOR_TPLINK_WR710N_V1)
 619         #define OFFSET_PIN_NUMBER                               0x00FE00
 620 #endif
 621
 622 /*
 623  * PLL and clocks configurations from FLASH
 624  */
 625 #if defined(CONFIG_FOR_DLINK_DIR505_A1) || \
 626     defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 627         /*
 628          * For DIR505 A1:
 629          * We will store PLL and CLOCK registers
 630          * configuration at the end of MAC data
 631          * partition (3rd 64 KiB block)
 632          * ----
 633          * For Black Swift board:
 634          * We will store PLL and CLOCK registers
 635          * configuration at the end of environment
 636          * sector (64 KB, environment uses only part!)
 637          */
 638         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00020000
 639         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 640
 641 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 642         /*
 643          * We will store PLL and CLOCK registers
 644          * configuration at the end of environment
 645          * sector (64 KB, environment uses only half!)
 646          */
 647         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00040000
 648         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 649
 650 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 651       defined(CONFIG_FOR_MESH_POTATO_V2)
 652         /*
 653          * We will store PLL and CLOCK registers
 654          * configuration at the end of environment
 655          * sector (64 KB, environment uses only half!)
 656          */
 657         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00030000
 658         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 659
 660 #else
 661         /*
 662          * All TP-Link routers have a lot of unused space
 663          * in FLASH, in second 64 KiB block.
 664          * We will store there PLL and CLOCK
 665          * registers configuration.
 666          */
 667         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 668         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 669
 670 #endif
 671
 672 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 673         /* Use last 32 bytes */
 674         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 675                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 676                                                                                                          0x0000FFE0)
 677 #endif
 678
 679 #include <cmd_confdefs.h>
 680
 681 #endif  /* __CONFIG_H */