u-boot/include/configs/ap121.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros AR933x based devices
   6  *
   7  * Reference designs: AP121
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _AP121_H
  13 #define _AP121_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
  25
  26         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO13 | GPIO14
  27         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0
  28         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  29                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  30         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  31         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  32         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  33
  34 #elif defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
  35
  36         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1 | GPIO13
  37         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO27
  38         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO26 | GPIO28 |\
  39                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  40                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  41         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO12
  42         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO26 | GPIO28 |\
  43                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  44         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  45
  46 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
  47
  48         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
  49         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  50         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  51         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  52
  53 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
  54
  55         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO26 | GPIO27
  56         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  57         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  58         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  59
  60 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
  61       defined(CONFIG_FOR_MESH_POTATO_V2)
  62
  63         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO28
  64         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO17
  65         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  66                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  67         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  68         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  69         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  70
  71 #elif defined(CONFIG_FOR_GL_AR150)
  72
  73         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13 | GPIO15
  74         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO6 |\
  75                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  76         #define CONFIG_QCA_GPIO_MASK_IN         GPIO1  | GPIO7  | GPIO8 | GPIO11 |\
  77                                                 GPIO14 | GPIO16 | GPIO17
  78         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO6
  79         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  80
  81 #elif defined(CONFIG_FOR_GL_INET)
  82
  83         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13
  84         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H
  85         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  86         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  87
  88 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
  89
  90         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO15 | GPIO17 |\
  91                                                 GPIO27
  92         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  93         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  94         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  95
  96 #elif defined(CONFIG_FOR_TPLINK_MR10U_V1)
  97
  98         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
  99         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
 100                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 101         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 102         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
 103                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 104
 105 #elif defined(CONFIG_FOR_TPLINK_MR13U_V1)
 106
 107         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO27
 108         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
 109                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 110         #define CONFIG_QCA_GPIO_MASK_IN         GPIO6 | GPIO7 | GPIO11
 111         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18
 112         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 113
 114 #elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
 115
 116         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0
 117         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO26 | GPIO27
 118         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 119                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
 120                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 121         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO18 | GPIO20
 122         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 123                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 124         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 125
 126 #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
 127
 128         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO26 | GPIO27
 129         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
 130                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 131         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 132         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
 133                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 134
 135 #elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
 136
 137         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1  | GPIO13 |\
 138                                                 GPIO14 | GPIO15 | GPIO16 |\
 139                                                 GPIO26
 140         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO27
 141         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 142                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
 143                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 144         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 145         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 146                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 147         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 148
 149 #elif defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
 150       defined(CONFIG_FOR_TPLINK_WR710N_V1)
 151
 152         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
 153         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 154                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 155         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 156         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 157                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 158
 159 #elif defined(CONFIG_FOR_TPLINK_WR720N_V3)
 160
 161         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
 162         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 163                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 164         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO18 | GPIO20
 165         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 166                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 167
 168 #elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
 169
 170         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1  | GPIO13 |\
 171                                                 GPIO14 | GPIO15 | GPIO16
 172         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO27
 173         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
 174                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 175         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO26
 176         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 177         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 178
 179 #endif
 180
 181 /*
 182  * ================
 183  * Default bootargs
 184  * ================
 185  */
 186 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 187
 188         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 189                                 "rootfstype=squashfs init=/sbin/init "\
 190                                 "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)"
 191
 192 #elif defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
 193
 194         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 195                                 "rootfstype=squashfs init=/sbin/init "\
 196                                 "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),6144k(rootfs),1600k(uImage),64k(NVRAM),64k(ART)"
 197
 198 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 199
 200         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 201                                 "rootfstype=squashfs init=/sbin/init "\
 202                                 "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)"
 203
 204 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 205
 206         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 "\
 207                                 "rootfstype=squashfs init=/sbin/init "\
 208                                 "mtdparts=ar7240-nor0:64k(u-boot),64k(art),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
 209
 210 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 211       defined(CONFIG_FOR_MESH_POTATO_V2)
 212
 213         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 214                                 "rootfstype=squashfs init=/sbin/init "\
 215                                 "mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(art)"
 216
 217 #elif defined(CONFIG_FOR_GL_AR150)
 218
 219         #define CONFIG_BOOTARGS "console=ttyATH0,115200 board=domino root=31:03 "\
 220                                 "rootfstype=squashfs,jffs2 noinitrd "\
 221                                 "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1280k(kernel),14656k(rootfs),64k(nvram),64k(art)ro,15936k@0x50000(firmware)"
 222
 223 #elif defined(CONFIG_FOR_GL_INET)            ||\
 224       defined(CONFIG_FOR_TPLINK_MR10U_V1)    ||\
 225       defined(CONFIG_FOR_TPLINK_MR13U_V1)    ||\
 226       defined(CONFIG_FOR_TPLINK_MR3020_V1)   ||\
 227       defined(CONFIG_FOR_TPLINK_MR3040_V1V2) ||\
 228       defined(CONFIG_FOR_TPLINK_MR3220_V2)   ||\
 229       defined(CONFIG_FOR_TPLINK_WR703N_V1)   ||\
 230       defined(CONFIG_FOR_TPLINK_WR720N_V3)   ||\
 231       defined(CONFIG_FOR_TPLINK_WR740N_V4)
 232
 233         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 234                                 "rootfstype=squashfs init=/sbin/init "\
 235                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 236
 237 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 238
 239         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 240                                 "rootfstype=squashfs init=/sbin/init "\
 241                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 242
 243 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
 244
 245         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 246                                 "rootfstype=squashfs init=/sbin/init "\
 247                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 248
 249 #endif
 250
 251 /*
 252  * =============================
 253  * Load address and boot command
 254  * =============================
 255  */
 256 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    ||\
 257     defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) ||\
 258     defined(CONFIG_FOR_GL_AR150)
 259         #define CFG_LOAD_ADDR   0x9F050000
 260 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 261         #define CFG_LOAD_ADDR   0x9F030000
 262 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 263         #define CFG_LOAD_ADDR   0x9F080000
 264 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 265       defined(CONFIG_FOR_MESH_POTATO_V2)
 266         #define CFG_LOAD_ADDR   0x9F040000
 267 #else
 268         #define CFG_LOAD_ADDR   0x9F020000
 269 #endif
 270
 271 #if defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
 272         #define CONFIG_BOOTCOMMAND      "bootm 0x9F050000 || bootm 0x9FE50000 || bootm 0x9F650000"
 273 #else
 274         #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 275 #endif
 276
 277 /*
 278  * =========================
 279  * Environment configuration
 280  * =========================
 281  */
 282 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    ||\
 283     defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) ||\
 284     defined(CONFIG_FOR_GL_AR150)
 285         #define CFG_ENV_ADDR            0x9F040000
 286         #define CFG_ENV_SIZE            0x8000
 287         #define CFG_ENV_SECT_SIZE       0x10000
 288 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 289         #define CFG_ENV_ADDR            0x9F020000
 290         #define CFG_ENV_SIZE            0x8000
 291         #define CFG_ENV_SECT_SIZE       0x10000
 292 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 293         #define CFG_ENV_ADDR            0x9F028000
 294         #define CFG_ENV_SIZE            0x7C00
 295         #define CFG_ENV_SECT_SIZE       0x10000
 296 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 297       defined(CONFIG_FOR_MESH_POTATO_V2)
 298         #define CFG_ENV_ADDR            0x9F030000
 299         #define CFG_ENV_SIZE            0x8000
 300         #define CFG_ENV_SECT_SIZE       0x10000
 301 #else
 302         #define CFG_ENV_ADDR            0x9F01EC00
 303         #define CFG_ENV_SIZE            0x1000
 304         #define CFG_ENV_SECT_SIZE       0x10000
 305 #endif
 306
 307 /*
 308  * ===========================
 309  * List of available baudrates
 310  * ===========================
 311  */
 312 #define CFG_BAUDRATE_TABLE      \
 313                 { 600,    1200,   2400,    4800,    9600,    14400,  \
 314                   19200,  28800,  38400,   56000,   57600,   115200, \
 315                   128000, 153600, 230400,  250000,  256000,  460800, \
 316                   576000, 921600, 1000000, 1152000, 1500000, 2000000 }
 317
 318 /*
 319  * ==================================================
 320  * MAC address/es, model and WPS pin offsets in FLASH
 321  * ==================================================
 322  */
 323 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    ||\
 324     defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) ||\
 325     defined(CONFIG_FOR_DRAGINO_V2)             ||\
 326     defined(CONFIG_FOR_MESH_POTATO_V2)
 327         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 328         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 329         #define OFFSET_MAC_ADDRESS              0x000000
 330         #define OFFSET_MAC_ADDRESS2             0x000006
 331 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) ||\
 332       defined(CONFIG_FOR_GL_AR150)
 333         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 334         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 335         #define OFFSET_MAC_ADDRESS              0x000000
 336 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 337         /*
 338          * DIR-505 has two MAC addresses inside dedicated MAC partition
 339          * They are stored in plain text...
 340          * TODO: read/write MAC stored as plain text
 341          * #define OFFSET_MAC_DATA_BLOCK        0x02000
 342          * #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
 343          * #define OFFSET_MAC_ADDRESS           0x000004
 344          * #define OFFSET_MAC_ADDRESS2          0x000016
 345          */
 346 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 347         #define OFFSET_MAC_DATA_BLOCK           0x010000
 348         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 349         #define OFFSET_MAC_ADDRESS              0x00FC00
 350 #else
 351         #define OFFSET_MAC_DATA_BLOCK           0x010000
 352         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 353         #define OFFSET_MAC_ADDRESS              0x00FC00
 354 #endif
 355
 356 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    &&\
 357     !defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) &&\
 358     !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)      &&\
 359     !defined(CONFIG_FOR_DLINK_DIR505_A1)        &&\
 360     !defined(CONFIG_FOR_DRAGINO_V2)             &&\
 361     !defined(CONFIG_FOR_GL_AR150)               &&\
 362     !defined(CONFIG_FOR_GL_INET)                &&\
 363     !defined(CONFIG_FOR_GS_OOLITE_V1_DEV)       &&\
 364     !defined(CONFIG_FOR_MESH_POTATO_V2)
 365         #define OFFSET_ROUTER_MODEL     0xFD00
 366 #endif
 367
 368 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\
 369     defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\
 370     defined(CONFIG_FOR_TPLINK_WR710N_V1) ||\
 371     defined(CONFIG_FOR_TPLINK_WR740N_V4)
 372         #define OFFSET_PIN_NUMBER       0xFE00
 373 #endif
 374
 375 /*
 376  * =========================
 377  * Custom changes per device
 378  * =========================
 379  */
 380
 381 /* Dragino 2 uses different IP addresses */
 382 #if defined(CONFIG_FOR_DRAGINO_V2)
 383         #undef  CONFIG_IPADDR
 384         #define CONFIG_IPADDR   192.168.255.1
 385
 386         #undef  CONFIG_SERVERIP
 387         #define CONFIG_SERVERIP 192.168.255.2
 388 #endif
 389
 390 /* Dragino 2 and Black Swift boards use different prompts */
 391 #if defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 392         #undef  CFG_PROMPT
 393         #define CFG_PROMPT      "BSB> "
 394 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 395       defined(CONFIG_FOR_MESH_POTATO_V2)
 396         #undef  CFG_PROMPT
 397         #define CFG_PROMPT      "dr_boot> "
 398 #endif
 399
 400 /* D-Link DIR-505 is limited to 64 KB only and doesn't use env */
 401 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 402         #undef CONFIG_CMD_DHCP
 403         #undef CONFIG_CMD_LOADB
 404 #endif
 405
 406 /*
 407  * ===========================
 408  * HTTP recovery configuration
 409  * ===========================
 410  */
 411 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 412
 413 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 414         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
 415 #endif
 416
 417 /* Firmware size limit */
 418 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) ||\
 419     defined(CONFIG_FOR_GL_AR150)
 420         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 421 #elif defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
 422         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (448 * 1024)
 423 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 424         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 425 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 426         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (512 * 1024)
 427 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 428       defined(CONFIG_FOR_MESH_POTATO_V2)
 429         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (320 * 1024)
 430 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 431         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 432 #else
 433         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 434 #endif
 435
 436 /*
 437  * ========================
 438  * PLL/Clocks configuration
 439  * ========================
 440  */
 441 #define CONFIG_QCA_PLL  QCA_PLL_PRESET_400_400_200
 442
 443 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    ||\
 444     defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) ||\
 445     defined(CONFIG_FOR_GL_AR150)
 446
 447         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 448         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 449
 450 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) ||\
 451       defined(CONFIG_FOR_DLINK_DIR505_A1)
 452
 453         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x20000
 454         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 455
 456 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 457       defined(CONFIG_FOR_MESH_POTATO_V2)
 458
 459         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x30000
 460         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 461
 462 #else
 463
 464         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 465         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 466
 467 #endif
 468
 469 /*
 470  * ==================================
 471  * For upgrade scripts in environment
 472  * ==================================
 473  */
 474 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)    &&\
 475     !defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB) &&\
 476     !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)      &&\
 477     !defined(CONFIG_FOR_DLINK_DIR505_A1)        &&\
 478     !defined(CONFIG_FOR_DRAGINO_V2)             &&\
 479     !defined(CONFIG_FOR_GL_AR150)               &&\
 480     !defined(CONFIG_FOR_MESH_POTATO_V2)
 481         #define CONFIG_UPG_SCRIPTS_UBOOT_SIZE_BCKP_HEX  0x20000
 482 #endif
 483
 484 #endif /* _AP121_H */