u-boot/include/configs/ap121.h

   1 /*
   2  * This file contains the configuration parameters for the AP121 (AR9331) board.
   3  */
   4
   5 #ifndef __CONFIG_H
   6 #define __CONFIG_H
   7
   8 #include <configs/ar7240.h>
   9 #include <config.h>
  10
  11 /*
  12  * FLASH and environment organization
  13  */
  14 #define CFG_MAX_FLASH_BANKS                     1
  15 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  16
  17 /*
  18  * We boot from this flash
  19  */
  20 #define CFG_FLASH_BASE                                  0x9F000000
  21 #ifdef COMPRESSED_UBOOT
  22         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  23         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  24 #endif
  25
  26 /*
  27  * The following #defines are needed to get flash environment right
  28  */
  29 #define CFG_MONITOR_BASE        TEXT_BASE
  30 #define CFG_MONITOR_LEN         (192 << 10)
  31
  32 /*
  33  * Default bootargs
  34  */
  35 #undef CONFIG_BOOTARGS
  36
  37 #if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \
  38         defined(CONFIG_FOR_TPLINK_WR720N_V3) || \
  39         defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
  40         defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \
  41         defined(CONFIG_FOR_TPLINK_MR10U_V1) || \
  42         defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
  43         defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
  44         defined(CONFIG_FOR_TPLINK_MR13U_V1) || \
  45         defined(CONFIG_FOR_GL_INET)
  46
  47         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
  48
  49 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
  50
  51         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)"
  52
  53 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
  54
  55         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
  56
  57 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
  58
  59         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
  60
  61 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
  62
  63         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)"
  64
  65 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
  66       defined(CONFIG_FOR_MESH_POTATO_V2)
  67
  68         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(ART)"
  69
  70 #endif
  71
  72 /*
  73  * Other env default values
  74  */
  75 #undef CONFIG_BOOTFILE
  76 #define CONFIG_BOOTFILE                 "firmware.bin"
  77
  78 #undef CONFIG_LOADADDR
  79 #define CONFIG_LOADADDR                 0x80800000
  80
  81 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
  82         #define CFG_LOAD_ADDR                    0x9F080000
  83         #define UPDATE_SCRIPT_FW_ADDR   "0x9F080000"
  84 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
  85         #define CFG_LOAD_ADDR                    0x9F050000
  86         #define UPDATE_SCRIPT_FW_ADDR   "0x9F050000"
  87 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
  88       defined(CONFIG_FOR_MESH_POTATO_V2)
  89         #define CFG_LOAD_ADDR                    0x9F040000
  90         #define UPDATE_SCRIPT_FW_ADDR   "0x9F040000"
  91 #else
  92         #define CFG_LOAD_ADDR                    0x9F020000
  93         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
  94 #endif
  95
  96 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
  97         #define CONFIG_BOOTCOMMAND "bootm 0x9F080000"
  98 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
  99         #define CONFIG_BOOTCOMMAND "bootm 0x9F050000"
 100 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 101       defined(CONFIG_FOR_MESH_POTATO_V2)
 102         #define CONFIG_BOOTCOMMAND "bootm 0x9F040000"
 103 #else
 104         #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
 105 #endif
 106
 107 /*
 108  * Dragino 2 uses different IP addresses
 109  */
 110 #if defined(CONFIG_FOR_DRAGINO_V2)
 111         #define CONFIG_IPADDR           192.168.255.1
 112         #define CONFIG_SERVERIP         192.168.255.2
 113 #else
 114         #define CONFIG_IPADDR           192.168.1.1
 115         #define CONFIG_SERVERIP         192.168.1.2
 116 #endif
 117
 118 /*
 119  * Dragino 2 uses different prompt
 120  */
 121 #if defined(CONFIG_FOR_DRAGINO_V2) || \
 122     defined(CONFIG_FOR_MESH_POTATO_V2)
 123         #if defined(CFG_PROMPT)
 124                 #undef CFG_PROMPT
 125         #endif
 126         #define CFG_PROMPT "dr_boot> "
 127 #endif
 128
 129 #undef  CFG_HZ
 130 #define CFG_HZ                          bd->bi_cfg_hz
 131 #undef  CPU_PLL_CONFIG_VAL
 132 #undef  CPU_CLK_CONTROL_VAL
 133
 134 // CPU-RAM-AHB frequency setting
 135 #ifndef CFG_PLL_FREQ
 136         #define CFG_PLL_FREQ    CFG_PLL_400_400_200
 137 #endif
 138
 139 /*
 140  * CPU_PLL_DITHER_FRAC_VAL
 141  *
 142  * Value written into CPU PLL Dither FRAC Register (PLL_DITHER_FRAC)
 143  *
 144  * bits 0..9    NFRAC_MAX       =>      1000 (0x3E8)
 145  * bits 10..13  NFRAC_MIN       =>      0 (minimum value is used)
 146  * bits 20..29  NFRAC_STEP      =>      1
 147  *
 148  */
 149 #define CPU_PLL_DITHER_FRAC_VAL         0x001003E8
 150
 151 /*
 152  * CPU_PLL_SETTLE_TIME_VAL
 153  *
 154  * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2)
 155  *
 156  * bits 0..11   SETTLE_TIME     =>      850 (0x352)
 157  *
 158  */
 159 #if CONFIG_40MHZ_XTAL_SUPPORT
 160         #define CPU_PLL_SETTLE_TIME_VAL         0x00000550
 161 #else
 162         #define CPU_PLL_SETTLE_TIME_VAL         0x00000352
 163 #endif
 164
 165 /*
 166  * CPU_CLK_CONTROL_VAL
 167  *
 168  * In CPU_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
 169  * After PLL configuration we nedd to clear this bit
 170  *
 171  * Values written into CPU Clock Control Register CLOCK_CONTROL
 172  *
 173  * bits 2               (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0)
 174  * bits 5..6    (2bit)  CPU_POST_DIV    =>      0       (DEFAULT, Ratio = 1)
 175  * bits 10..11  (2bit)  DDR_POST_DIV    =>      0       (DEFAULT, Ratio = 1)
 176  * bits 15..16  (2bit)  AHB_POST_DIV    =>      1       (DEFAULT, Ratio = 2)
 177  *
 178  */
 179
 180 /*
 181  * CPU_PLL_CONFIG_VAL
 182  *
 183  * In CPU_PLL_CONFIG_VAL bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
 184  * After PLL configuration we need to clear this bit
 185  *
 186  * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG)
 187  *
 188  * bits 10..15  (6bit)  DIV_INT (The integer part of the DIV to CPU PLL)                        =>      32      (0x20)
 189  * bits 16..20  (5bit)  REFDIV  (Reference clock divider)                                                       =>      1       (0x1)   [doesn't start at values different than 1 (maybe need to change other dividers?)]
 190  * bits 21              (1bit)  RANGE   (Determine the VCO frequency range of the CPU PLL)      =>      0       (0x0)   [doesn't have impact on clock values]
 191  * bits 23..25  (3bit)  OUTDIV  (Define the ratio between VCO output and PLL output     =>      1       (0x1)   [value == 0 is illegal!]
 192  *                                                              VCOOUT * (1/2^OUTDIV) = PLLOUT)
 193  */
 194
 195 /*
 196  * = PLL CALCULATION =============
 197  * PLL = ((25 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV)   // XTAL=25 MHz
 198  * OR
 199  * PLL = ((40 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV)   // XTAL=40 MHz
 200  *
 201  * CPU = PLL / CPU_POST_DIV
 202  * DDR = PLL / DDR_POST_DIV
 203  * AHB = PLL / AHB_POST_DIV
 204  *
 205  */
 206
 207 /*
 208  * AR7240_SPI_CONTROL
 209  *
 210  * Value written into SPI Control (SPI_CONTROL) register
 211  *
 212  * bits 0..5    (6bit)  CLOCK_DIVIDER   (Specifies the clock divider setting. Actual clock frequency would be (AHB_CLK / ((CLOCK_DIVIDER+1)*2)) )
 213  * bits 6               (1bit)  REMAP_DISABLE   (Remaps 4 MB space over unless explicitly disabled by setting this bit to 1. If set to 1, 16 MB is accessible.)
 214  *
 215  */
 216
 217 /*
 218  * CPU_PLL_CONFIG and CPU_CLK_CONTROL registers values generator
 219  */
 220 #define MAKE_AR9331_CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv)  ( ((0x3F & divint) << 10) | \
 221                                                                          ((0x1F & refdiv) << 16) | \
 222                                                                          ((0x1 & range)   << 21) | \
 223                                                                          ((0x7 & outdiv)  << 23) )
 224
 225 #define MAKE_AR9331_CPU_CLK_CONTROL_VAL(cpudiv, ddrdiv, ahbdiv)        ( ((0x3 & (cpudiv - 1)) << 5)  | \
 226                                                                          ((0x3 & (ddrdiv - 1)) << 10) | \
 227                                                                          ((0x3 & (ahbdiv - 1)) << 15) )
 228
 229 #define MAKE_AR9331_SPI_CONTROL_VAL(spidiv)                            ( ((spidiv >> 1) - 1) | 0x40 )
 230
 231 /*
 232  * Default values (400/400/200 MHz) for O/C recovery mode
 233  */
 234
 235 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 236 #define CPU_CLK_CONTROL_VAL_DEFAULT             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 237
 238 #if CONFIG_40MHZ_XTAL_SUPPORT
 239         // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 240         #define CPU_PLL_CONFIG_VAL_DEFAULT      MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
 241 #else
 242         // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 243         #define CPU_PLL_CONFIG_VAL_DEFAULT      MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 1)
 244 #endif
 245
 246 // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
 247 #define AR7240_SPI_CONTROL_DEFAULT      MAKE_AR9331_SPI_CONTROL_VAL(6)
 248
 249 #if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
 250
 251         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 252         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 253
 254         #if CONFIG_40MHZ_XTAL_SUPPORT
 255                 // DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 256                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
 257         #else
 258                 // DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 259                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
 260         #endif
 261
 262         // CLOCK_DIVIDER = 1 (SPI clock = 100 / 4 ~ 25 MHz)
 263         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 264
 265         #define CFG_HZ_FALLBACK (200000000LU/2)
 266
 267 #elif (CFG_PLL_FREQ == CFG_PLL_200_200_200)
 268
 269         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
 270         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
 271
 272         #if CONFIG_40MHZ_XTAL_SUPPORT
 273                 // DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 274                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
 275         #else
 276                 // DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 277                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
 278         #endif
 279
 280         // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
 281         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 282
 283         #define CFG_HZ_FALLBACK (200000000LU/2)
 284
 285 #elif (CFG_PLL_FREQ == CFG_PLL_225_225_112)
 286
 287         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 288         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 289
 290         #if CONFIG_40MHZ_XTAL_SUPPORT
 291                 #define FREQUENCY_NOT_SUPPORTED
 292         #else
 293                 // DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 294                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
 295         #endif
 296
 297         // CLOCK_DIVIDER = 1 (SPI clock = 112 / 4 ~ 28 MHz)
 298         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 299
 300         #define CFG_HZ_FALLBACK (225000000LU/2)
 301
 302 #elif (CFG_PLL_FREQ == CFG_PLL_225_225_225)
 303
 304         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
 305         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
 306
 307         #if CONFIG_40MHZ_XTAL_SUPPORT
 308                 #define FREQUENCY_NOT_SUPPORTED
 309         #else
 310                 // DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 311                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
 312         #endif
 313
 314         // CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
 315         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 316
 317         #define CFG_HZ_FALLBACK (225000000LU/2)
 318
 319 #elif (CFG_PLL_FREQ == CFG_PLL_250_250_125)
 320
 321         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 322         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 323
 324         #if CONFIG_40MHZ_XTAL_SUPPORT
 325                 // DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 326                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
 327         #else
 328                 // DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 329                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
 330         #endif
 331
 332         // CLOCK_DIVIDER = 1 (SPI clock = 125 / 4 ~ 31 MHz)
 333         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 334
 335         #define CFG_HZ_FALLBACK (250000000LU/2)
 336
 337 #elif (CFG_PLL_FREQ == CFG_PLL_250_250_250)
 338
 339         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
 340         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
 341
 342         #if CONFIG_40MHZ_XTAL_SUPPORT
 343                 // DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
 344                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
 345         #else
 346                 // DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 347                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
 348         #endif
 349
 350         // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
 351         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 352
 353         #define CFG_HZ_FALLBACK (250000000LU/2)
 354
 355 #elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
 356
 357         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 358         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 359
 360         #if CONFIG_40MHZ_XTAL_SUPPORT
 361                 // DIV_INT = 15 (40 MHz * 15/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 362                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(15, 1, 0, 1)
 363         #else
 364                 // DIV_INT = 24 (25 MHz * 24/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 365                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
 366         #endif
 367
 368         // CLOCK_DIVIDER = 2 (SPI clock = 150 / 6 ~ 25 MHz)
 369         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 370
 371         #define CFG_HZ_FALLBACK (300000000LU/2)
 372
 373 #elif (CFG_PLL_FREQ == CFG_PLL_325_325_162)
 374
 375         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 376         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 377
 378         #if CONFIG_40MHZ_XTAL_SUPPORT
 379                 #define FREQUENCY_NOT_SUPPORTED
 380         #else
 381                 // DIV_INT = 26 (25 MHz * 26/2 = 325 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 382                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
 383         #endif
 384
 385         // CLOCK_DIVIDER = 2 (SPI clock = 162 / 6 ~ 27 MHz)
 386         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 387
 388         #define CFG_HZ_FALLBACK (325000000LU/2)
 389
 390 #elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
 391
 392         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 393         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 394
 395         #if CONFIG_40MHZ_XTAL_SUPPORT
 396                 #define FREQUENCY_NOT_SUPPORTED
 397         #else
 398                 // DIV_INT = 28 (25 MHz * 28/2 = 350 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 399                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
 400         #endif
 401
 402         // CLOCK_DIVIDER = 2 (SPI clock = 175 / 6 ~ 29 MHz)
 403         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 404
 405         #define CFG_HZ_FALLBACK (350000000LU/2)
 406
 407 #elif (CFG_PLL_FREQ == CFG_PLL_360_360_180)
 408
 409         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 410         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 411
 412         #if CONFIG_40MHZ_XTAL_SUPPORT
 413                 // DIV_INT = 18 (40 MHz * 18/2 = 360 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 414                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(18, 1, 0, 1)
 415         #else
 416                 // DIV_INT = 29 (25 MHz * 28/2 = 362 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 417                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
 418         #endif
 419
 420         // CLOCK_DIVIDER = 2 (SPI clock = 180 / 6 ~ 30 MHz)
 421         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 422
 423         #define CFG_HZ_FALLBACK (360000000LU/2)
 424
 425 #elif (CFG_PLL_FREQ == CFG_PLL_380_380_190)
 426
 427         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 428         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 429
 430         #if CONFIG_40MHZ_XTAL_SUPPORT
 431                 // DIV_INT = 19 (40 MHz * 19/2 = 380 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 432                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(19, 1, 0, 1)
 433         #else
 434                 #define FREQUENCY_NOT_SUPPORTED
 435         #endif
 436
 437         // CLOCK_DIVIDER = 2 (SPI clock = 190 / 6 ~ 32 MHz)
 438         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 439
 440         #define CFG_HZ_FALLBACK (380000000LU/2)
 441
 442 #elif (CFG_PLL_FREQ == CFG_PLL_400_400_200)
 443
 444         // default configuration
 445         #define CPU_CLK_CONTROL_VAL     CPU_CLK_CONTROL_VAL_DEFAULT
 446         #define CPU_PLL_CONFIG_VAL      CPU_PLL_CONFIG_VAL_DEFAULT
 447         #define AR7240_SPI_CONTROL      AR7240_SPI_CONTROL_DEFAULT
 448
 449         #define CFG_HZ_FALLBACK (400000000LU/2)
 450
 451 #elif (CFG_PLL_FREQ == CFG_PLL_412_412_206)
 452
 453         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 454         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 455
 456         #if CONFIG_40MHZ_XTAL_SUPPORT
 457                 #define FREQUENCY_NOT_SUPPORTED
 458         #else
 459                 // DIV_INT = 33 (25 MHz * 33/2 = 412 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 460                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(33, 1, 0, 1)
 461         #endif
 462
 463         // CLOCK_DIVIDER = 2 (SPI clock = 206 / 6 ~ 34 MHz)
 464         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 465
 466         #define CFG_HZ_FALLBACK (412000000LU/2)
 467
 468 #elif (CFG_PLL_FREQ == CFG_PLL_420_420_210)
 469
 470         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 471         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 472
 473         #if CONFIG_40MHZ_XTAL_SUPPORT
 474                 // DIV_INT = 21 (40 MHz * 21/2 = 420 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 475                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(21, 1, 0, 1)
 476         #else
 477                 #define FREQUENCY_NOT_SUPPORTED
 478         #endif
 479
 480         // CLOCK_DIVIDER = 2 (SPI clock = 210 / 6 ~ 35 MHz)
 481         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 482
 483         #define CFG_HZ_FALLBACK (420000000LU/2)
 484
 485 #elif (CFG_PLL_FREQ == CFG_PLL_425_425_212)
 486
 487         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 488         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 489
 490         #if CONFIG_40MHZ_XTAL_SUPPORT
 491                 #define FREQUENCY_NOT_SUPPORTED
 492         #else
 493                 // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 494                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(34, 1, 0, 1)
 495         #endif
 496
 497         // CLOCK_DIVIDER = 2 (SPI clock = 212 / 6 ~ 35 MHz)
 498         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 499
 500         #define CFG_HZ_FALLBACK (425000000LU/2)
 501
 502 #elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
 503
 504         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 505         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 506
 507         #if CONFIG_40MHZ_XTAL_SUPPORT
 508                 #define FREQUENCY_NOT_SUPPORTED
 509         #else
 510                 // DIV_INT = 35 (25 MHz * 35/2 = 437 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 511                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(35, 1, 0, 1)
 512         #endif
 513
 514         // CLOCK_DIVIDER = 3 (SPI clock = 218 / 8 ~ 27 MHz)
 515         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 516
 517         #define CFG_HZ_FALLBACK (437000000LU/2)
 518
 519 #elif (CFG_PLL_FREQ == CFG_PLL_440_440_220)
 520
 521         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 522         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 523
 524         #if CONFIG_40MHZ_XTAL_SUPPORT
 525                 // DIV_INT = 22 (40 MHz * 22/2 = 440 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 526                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(22, 1, 0, 1)
 527         #else
 528                 #define FREQUENCY_NOT_SUPPORTED
 529         #endif
 530
 531         // CLOCK_DIVIDER = 3 (SPI clock = 220 / 8 ~ 27 MHz)
 532         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 533
 534         #define CFG_HZ_FALLBACK (440000000LU/2)
 535
 536 #elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
 537
 538         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 539         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 540
 541         #if CONFIG_40MHZ_XTAL_SUPPORT
 542                 #define FREQUENCY_NOT_SUPPORTED
 543         #else
 544                 // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 545                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 1)
 546         #endif
 547
 548         // CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
 549         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 550
 551         #define CFG_HZ_FALLBACK (450000000LU/2)
 552
 553 #elif (CFG_PLL_FREQ == CFG_PLL_460_460_230)
 554
 555         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 556         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 557
 558         #if CONFIG_40MHZ_XTAL_SUPPORT
 559                 // DIV_INT = 23 (40 MHz * 23/2 = 460 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 560                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(23, 1, 0, 1)
 561         #else
 562                 // DIV_INT = 37 (25 MHz * 36/2 = 462 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 563                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(37, 1, 0, 1)
 564         #endif
 565
 566         // CLOCK_DIVIDER = 3 (SPI clock = 230 / 8 ~ 29 MHz)
 567         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 568
 569         #define CFG_HZ_FALLBACK (460000000LU/2)
 570
 571 #elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
 572
 573         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 574         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 575
 576         #if CONFIG_40MHZ_XTAL_SUPPORT
 577                 #define FREQUENCY_NOT_SUPPORTED
 578         #else
 579                 // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 580                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(38, 1, 0, 1)
 581         #endif
 582
 583         // CLOCK_DIVIDER = 3 (SPI clock = 237 / 8 ~ 30 MHz)
 584         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 585
 586         #define CFG_HZ_FALLBACK (475000000LU/2)
 587
 588 #elif (CFG_PLL_FREQ == CFG_PLL_480_480_240)
 589
 590         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 591         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 592
 593         #if CONFIG_40MHZ_XTAL_SUPPORT
 594                 // DIV_INT = 24 (40 MHz * 24/2 = 480 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 595                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
 596         #else
 597                 #define FREQUENCY_NOT_SUPPORTED
 598         #endif
 599
 600         // CLOCK_DIVIDER = 3 (SPI clock = 240 / 8 ~ 30 MHz)
 601         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 602
 603         #define CFG_HZ_FALLBACK (480000000LU/2)
 604
 605 #elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
 606
 607         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 608         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 609
 610         #if CONFIG_40MHZ_XTAL_SUPPORT
 611                 #define FREQUENCY_NOT_SUPPORTED
 612         #else
 613                 // DIV_INT = 39 (25 MHz * 39/2 = 487 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 614                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(39, 1, 0, 1)
 615         #endif
 616
 617         // CLOCK_DIVIDER = 3 (SPI clock = 243 / 8 ~ 30 MHz)
 618         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 619
 620         #define CFG_HZ_FALLBACK (487000000LU/2)
 621
 622 #elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
 623
 624         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 625         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 626
 627         #if CONFIG_40MHZ_XTAL_SUPPORT
 628                 // DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 629                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
 630         #else
 631                 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 632                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
 633         #endif
 634
 635         // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
 636         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 637
 638         #define CFG_HZ_FALLBACK (500000000LU/2)
 639
 640 #elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
 641
 642         // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
 643         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 2)
 644
 645         #if CONFIG_40MHZ_XTAL_SUPPORT
 646                 // DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 647                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
 648         #else
 649                 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 650                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
 651         #endif
 652
 653         // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
 654         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 655
 656         #define CFG_HZ_FALLBACK (500000000LU/2)
 657
 658 #elif (CFG_PLL_FREQ == CFG_PLL_520_520_260)
 659
 660         // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
 661         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
 662
 663         #if CONFIG_40MHZ_XTAL_SUPPORT
 664                 // DIV_INT = 26 (40 MHz * 26/2 = 520 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 665                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
 666         #else
 667                 #define FREQUENCY_NOT_SUPPORTED
 668         #endif
 669
 670         // CLOCK_DIVIDER = 3 (SPI clock = 260 / 8 ~ 32 MHz)
 671         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(8)
 672
 673         #define CFG_HZ_FALLBACK (520000000LU/2)
 674
 675 #elif (CFG_PLL_FREQ == CFG_PLL_525_262_131)
 676
 677         // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
 678         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
 679
 680         #if CONFIG_40MHZ_XTAL_SUPPORT
 681                 #define FREQUENCY_NOT_SUPPORTED
 682         #else
 683                 // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 684                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(42, 1, 0, 1)
 685         #endif
 686
 687         // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 33 MHz)
 688         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 689
 690         #define CFG_HZ_FALLBACK (525000000LU/2)
 691
 692 #elif (CFG_PLL_FREQ == CFG_PLL_560_280_140)
 693
 694         // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
 695         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
 696
 697         #if CONFIG_40MHZ_XTAL_SUPPORT
 698                 // DIV_INT = 28 (40 MHz * 28/2 = 560 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 699                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
 700         #else
 701                 // DIV_INT = 45 (25 MHz * 45/2 = 562 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 702                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(45, 1, 0, 1)
 703         #endif
 704
 705         // CLOCK_DIVIDER = 1 (SPI clock = 140 / 4 ~ 35 MHz)
 706         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 707
 708         #define CFG_HZ_FALLBACK (560000000LU/2)
 709
 710 #elif (CFG_PLL_FREQ == CFG_PLL_580_290_145)
 711
 712         // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
 713         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
 714
 715         #if CONFIG_40MHZ_XTAL_SUPPORT
 716                 // DIV_INT = 29 (40 MHz * 29/2 = 580 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 717                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
 718         #else
 719                 #define FREQUENCY_NOT_SUPPORTED
 720         #endif
 721
 722         // CLOCK_DIVIDER = 1 (SPI clock = 145 / 4 ~ 36 MHz)
 723         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(4)
 724
 725         #define CFG_HZ_FALLBACK (580000000LU/2)
 726
 727 #elif (CFG_PLL_FREQ == CFG_PLL_600_300_200)
 728
 729         // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 3
 730         #define CPU_CLK_CONTROL_VAL             MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 3)
 731
 732         #if CONFIG_40MHZ_XTAL_SUPPORT
 733                 // DIV_INT = 30 (40 MHz * 30/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 734                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(30, 1, 0, 1)
 735         #else
 736                 // DIV_INT = 48 (25 MHz * 48/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
 737                 #define CPU_PLL_CONFIG_VAL      MAKE_AR9331_CPU_PLL_CONFIG_VAL(48, 1, 0, 1)
 738         #endif
 739
 740         // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
 741         #define AR7240_SPI_CONTROL      MAKE_AR9331_SPI_CONTROL_VAL(6)
 742
 743         #define CFG_HZ_FALLBACK (600000000LU/2)
 744
 745 #elif defined(CFG_PLL_FREQ)
 746         #error Unknown frequency setting!
 747 #endif
 748
 749 /*
 750  * Check if clocks configuration is valid
 751  */
 752 #ifdef FREQUENCY_NOT_SUPPORTED
 753         #error Selected frequency setting is not supported with your reference clock!
 754 #endif
 755
 756 /*
 757  * Cache lock for stack
 758  */
 759 #define CFG_INIT_SP_OFFSET              0x1000
 760
 761 /*
 762  * Address and size of Primary Environment Sector
 763  */
 764 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
 765         defined(CONFIG_FOR_DRAGINO_V2) || \
 766         defined(CONFIG_FOR_MESH_POTATO_V2)
 767         #define CFG_ENV_IS_IN_FLASH     1
 768         #undef CFG_ENV_IS_NOWHERE
 769 #else
 770         #undef  CFG_ENV_IS_IN_FLASH
 771         #define CFG_ENV_IS_NOWHERE      1
 772 #endif
 773
 774 #if defined(CONFIG_FOR_DRAGINO_V2) || \
 775         defined(CONFIG_FOR_MESH_POTATO_V2)
 776         #define CFG_ENV_ADDR            0x9F030000
 777         #define CFG_ENV_SIZE            0x8000
 778         #define CFG_ENV_SECT_SIZE       0x10000
 779 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 780         #define CFG_ENV_ADDR            0x9F040000
 781         #define CFG_ENV_SIZE            0x8000
 782         #define CFG_ENV_SECT_SIZE       0x10000
 783 #else
 784         #define CFG_ENV_ADDR            0x9F040000
 785         #define CFG_ENV_SIZE            0x10000
 786 #endif
 787
 788 /*
 789  * Available commands
 790  */
 791 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 792
 793         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 794                                                          CFG_CMD_DHCP   | \
 795                                                          CFG_CMD_PING   | \
 796                                                          CFG_CMD_FLASH  | \
 797                                                          CFG_CMD_NET    | \
 798                                                          CFG_CMD_RUN    | \
 799                                                          CFG_CMD_DATE   | \
 800                                                          CFG_CMD_ECHO   | \
 801                                                          CFG_CMD_BOOTD  | \
 802                                                          CFG_CMD_ITEST  | \
 803                                                          CFG_CMD_IMI)
 804
 805 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
 806       defined(CONFIG_FOR_DRAGINO_V2) || \
 807       defined(CONFIG_FOR_MESH_POTATO_V2)
 808
 809         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 810                                                          CFG_CMD_DHCP   | \
 811                                                          CFG_CMD_PING   | \
 812                                                          CFG_CMD_FLASH  | \
 813                                                          CFG_CMD_NET    | \
 814                                                          CFG_CMD_RUN    | \
 815                                                          CFG_CMD_DATE   | \
 816                                                          CFG_CMD_SNTP   | \
 817                                                          CFG_CMD_ECHO   | \
 818                                                          CFG_CMD_BOOTD  | \
 819                                                          CFG_CMD_ITEST  | \
 820                                                          CFG_CMD_IMI    | \
 821                                                          CFG_CMD_ENV)
 822
 823 #else
 824
 825         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 826                                                          CFG_CMD_DHCP   | \
 827                                                          CFG_CMD_PING   | \
 828                                                          CFG_CMD_FLASH  | \
 829                                                          CFG_CMD_NET    | \
 830                                                          CFG_CMD_RUN    | \
 831                                                          CFG_CMD_DATE   | \
 832                                                          CFG_CMD_ECHO   | \
 833                                                          CFG_CMD_BOOTD  | \
 834                                                          CFG_CMD_ITEST)
 835
 836 #endif
 837
 838 // Enable NetConsole and custom NetConsole port
 839 #define CONFIG_NETCONSOLE
 840 #define CONFIG_NETCONSOLE_PORT  6666
 841
 842 /* DDR init values */
 843 #if CONFIG_40MHZ_XTAL_SUPPORT
 844         #define CFG_DDR_REFRESH_VAL     0x4270
 845 #else
 846         #define CFG_DDR_REFRESH_VAL     0x4186
 847 #endif
 848
 849 #define CFG_DDR_CONFIG_VAL              0x7fbc8cd0
 850 #define CFG_DDR_MODE_VAL_INIT   0x133
 851
 852 #ifdef LOW_DRIVE_STRENGTH
 853         #define CFG_DDR_EXT_MODE_VAL    0x2
 854 #else
 855         #define CFG_DDR_EXT_MODE_VAL    0x0
 856 #endif
 857
 858 #define CFG_DDR_MODE_VAL        0x33
 859 #define CFG_DDR_TRTW_VAL        0x1f
 860 #define CFG_DDR_TWTR_VAL        0x1e
 861
 862 //#define CFG_DDR_CONFIG2_VAL                   0x99d0e6a8      // HORNET 1.0
 863 #define CFG_DDR_CONFIG2_VAL                             0x9dd0e6a8      // HORNET 1.1
 864 #define CFG_DDR_RD_DATA_THIS_CYCLE_VAL  0x00ff
 865 #define CFG_DDR_TAP0_VAL                                0x8
 866 #define CFG_DDR_TAP1_VAL                                0x9
 867
 868 /* DDR2 Init values */
 869 #define CFG_DDR2_EXT_MODE_VAL                   0x402
 870
 871 #define CONFIG_NET_MULTI
 872
 873 /* choose eth1 first for tftpboot interface added by ZJin, 110328 */
 874 #define CONFIG_AG7240_SPEPHY
 875
 876 /*
 877  * Web Failsafe configuration
 878  */
 879 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                                  CONFIG_LOADADDR
 880
 881 // U-Boot partition size and offset
 882 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                                CFG_FLASH_BASE
 883
 884 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 885         #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (64 * 1024)
 886         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x10000"
 887 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 888         #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (256 * 1024)
 889         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x40000"
 890 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 891       defined(CONFIG_FOR_MESH_POTATO_V2)
 892         #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (192 * 1024)
 893         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x30000"
 894 #else
 895         #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (64 * 1024)
 896         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x10000"
 897 #endif
 898
 899 // Firmware partition offset
 900 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 901         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x80000
 902 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 903         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
 904 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 905       defined(CONFIG_FOR_MESH_POTATO_V2)
 906         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x40000
 907 #else
 908         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 909 #endif
 910
 911 // ART partition size and offset
 912 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 913         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS                          WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x10000
 914 #endif
 915
 916 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES                    (64 * 1024)
 917
 918 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 919 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 920         // D-Link DIR-505: 64k(U-Boot),64k(ART),64k(MAC),64k(NVRAM),256k(Language)
 921         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (512 * 1024)
 922 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 923         // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART)
 924         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 925 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
 926       defined(CONFIG_FOR_MESH_POTATO_V2)
 927         // Dragino 2: 192k(U-Boot),64k(U-Boot env),64k(ART)
 928         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (320 * 1024)
 929 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 930         // GS-Oolite v1: 128k(U-Boot + MAC),64k(ART)
 931         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 932 #else
 933         // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 934         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 935 #endif
 936
 937 // progress state info
 938 #define WEBFAILSAFE_PROGRESS_START                              0
 939 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 940 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 941 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 942 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 943
 944 // update type
 945 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 946 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 947 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 948
 949 /*-----------------------------------------------------------------------*/
 950
 951 /*
 952  * Additional environment variables for simple upgrades
 953  */
 954 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 955                                                                         "uboot_name=uboot.bin\0" \
 956                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 957                                                                         "uboot_upg=" \
 958                                                                                 "if ping $serverip; then " \
 959                                                                                         "tftp $loadaddr $uboot_name && " \
 960                                                                                         "if itest.l $filesize == $uboot_size; then " \
 961                                                                                                 "erase $uboot_addr +$filesize && " \
 962                                                                                                 "cp.b $loadaddr $uboot_addr $filesize && " \
 963                                                                                                 "echo OK!; " \
 964                                                                                         "else " \
 965                                                                                                 "echo ERROR! Wrong file size!; " \
 966                                                                                         "fi; " \
 967                                                                                 "else " \
 968                                                                                         "ERROR! Server not reachable!; " \
 969                                                                                 "fi\0" \
 970                                                                         "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \
 971                                                                         "firmware_name=firmware.bin\0" \
 972                                                                         "firmware_upg=" \
 973                                                                                 "if ping $serverip; then " \
 974                                                                                         "tftp $loadaddr $firmware_name && " \
 975                                                                                         "erase $firmware_addr +$filesize && " \
 976                                                                                         "cp.b $loadaddr $firmware_addr $filesize && " \
 977                                                                                         "echo OK!; " \
 978                                                                                 "else " \
 979                                                                                         "ERROR! Server not reachable!; " \
 980                                                                                 "fi\0" \
 981                                                                         SILENT_ENV_VARIABLE
 982
 983 #define CFG_ATHRS26_PHY                         1
 984 #define CFG_AG7240_NMACS                        2
 985 #define CFG_MII0_RMII                           1
 986 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 987
 988 #undef DEBUG
 989 #define milisecdelay(_x)                        udelay((_x) * 1000)
 990
 991 /* MAC address, model and PIN number offsets in FLASH */
 992 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 993         // DIR-505 has two MAC addresses inside dedicated MAC partition
 994         // They are stored in plain text... TODO: read/write MAC stored as plain text
 995         //#define OFFSET_MAC_DATA_BLOCK                 0x020000
 996         //#define OFFSET_MAC_DATA_BLOCK_LENGTH  0x010000
 997         //#define OFFSET_MAC_ADDRESS                            0x000004
 998         //#define OFFSET_MAC_ADDRESS2                           0x000016
 999 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
1000       defined(CONFIG_FOR_DRAGINO_V2) || \
1001       defined(CONFIG_FOR_MESH_POTATO_V2)
1002         // Carambola 2 and Dragino 2 have two MAC addresses at the beginning of ART partition
1003         #define OFFSET_MAC_DATA_BLOCK                   0xFF0000
1004         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
1005         #define OFFSET_MAC_ADDRESS                              0x000000
1006         #define OFFSET_MAC_ADDRESS2                             0x000006
1007 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
1008         // GS-OOlite has only one MAC, inside second block
1009         // It's some kind of TP-Link clone
1010         #define OFFSET_MAC_DATA_BLOCK                   0x010000
1011         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
1012         #define OFFSET_MAC_ADDRESS                              0x00FC00
1013 #else
1014         #define OFFSET_MAC_DATA_BLOCK                   0x010000
1015         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
1016         #define OFFSET_MAC_ADDRESS                              0x00FC00
1017 #endif
1018
1019 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
1020         !defined(CONFIG_FOR_DLINK_DIR505_A1)     && \
1021         !defined(CONFIG_FOR_GS_OOLITE_V1_DEV)    && \
1022         !defined(CONFIG_FOR_DRAGINO_V2)          && \
1023         !defined(CONFIG_FOR_MESH_POTATO_V2)      && \
1024         !defined(CONFIG_FOR_GL_INET)
1025 #define OFFSET_ROUTER_MODEL                                     0x00FD00
1026 #endif
1027
1028 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
1029         defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
1030         defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
1031         defined(CONFIG_FOR_TPLINK_WR710N_V1)
1032         #define OFFSET_PIN_NUMBER                               0x00FE00
1033 #endif
1034
1035 /*
1036  * PLL and clocks configurations from FLASH
1037  *
1038  * We need space for 4x 32-bit variables:
1039  * - PLL_MAGIC_VARIABLE
1040  * - values of registers:
1041  *   - CPU_PLL_CONFIG (page 70 in datasheet)
1042  *   - CLOCK_CONTROL  (page 71)
1043  *   - SPI_CONTROL    (page 261)
1044  */
1045 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
1046         /*
1047          * We will store PLL and CLOCK registers
1048          * configuration at the end of MAC data
1049          * partition (3rd 64 KiB block)
1050          */
1051         #define PLL_IN_FLASH_MAGIC                              0x504C4C73
1052         #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00020000
1053         #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
1054         #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
1055 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
1056         /*
1057          * We will store PLL and CLOCK registers
1058          * configuration at the end of environment
1059          * sector (64 KB, environment uses only half!)
1060          */
1061         #define PLL_IN_FLASH_MAGIC                              0x504C4C73
1062         #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00040000
1063         #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
1064         #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
1065 #elif defined(CONFIG_FOR_DRAGINO_V2) || \
1066       defined(CONFIG_FOR_MESH_POTATO_V2)
1067         /*
1068          * We will store PLL and CLOCK registers
1069          * configuration at the end of environment
1070          * sector (64 KB, environment uses only half!)
1071          */
1072         #define PLL_IN_FLASH_MAGIC                              0x504C4C73
1073         #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00030000
1074         #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
1075         #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
1076 #else
1077         /*
1078          * All TP-Link routers have a lot of unused space
1079          * in FLASH, in second 64 KiB block.
1080          * We will store there PLL and CLOCK
1081          * registers configuration.
1082          */
1083         #define PLL_IN_FLASH_MAGIC                              0x504C4C73
1084         #define PLL_IN_FLASH_DATA_BLOCK_OFFSET  0x00010000
1085         #define PLL_IN_FLASH_DATA_BLOCK_LENGTH  0x00010000
1086         #define PLL_IN_FLASH_MAGIC_OFFSET               0x0000FFF0      // last 16 bytes
1087 #endif
1088
1089 #include <cmd_confdefs.h>
1090
1091 #endif  /* __CONFIG_H */