2 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
4 * This file contains the configuration parameters
5 * for Qualcomm Atheros AR933x based devices
7 * Reference designs: AP121
9 * SPDX-License-Identifier: GPL-2.0
16 #include <configs/qca9k_common.h>
17 #include <soc/soc_common.h>
24 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
26 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO13 | GPIO14
27 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0
28 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
29 CONFIG_QCA_GPIO_MASK_LED_ACT_H
30 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
31 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
32 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
34 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
36 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO26 | GPIO27
37 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
38 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
39 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
41 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
42 defined(CONFIG_FOR_MESH_POTATO_V2)
44 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO28
45 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO17
46 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
47 CONFIG_QCA_GPIO_MASK_LED_ACT_H
48 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
49 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
50 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
52 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
54 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO15 | GPIO17 |\
56 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
57 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
58 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
60 #elif defined(CONFIG_FOR_GL_INET)
62 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO13
63 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H
64 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
65 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
67 #elif defined(CONFIG_FOR_TPLINK_MR10U_V1)
69 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27
70 #define CONFIG_QCA_GPIO_MASK_OUT GPIO18 |\
71 CONFIG_QCA_GPIO_MASK_LED_ACT_L
72 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
73 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
74 CONFIG_QCA_GPIO_MASK_LED_ACT_L
76 #elif defined(CONFIG_FOR_TPLINK_MR13U_V1)
78 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO27
79 #define CONFIG_QCA_GPIO_MASK_OUT GPIO18 |\
80 CONFIG_QCA_GPIO_MASK_LED_ACT_H
81 #define CONFIG_QCA_GPIO_MASK_IN GPIO6 | GPIO7 | GPIO11
82 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18
83 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
85 #elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
87 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0
88 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO26 | GPIO27
89 #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\
90 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
91 CONFIG_QCA_GPIO_MASK_LED_ACT_H
92 #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO18 | GPIO20
93 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
94 CONFIG_QCA_GPIO_MASK_LED_ACT_L
95 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
97 #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
99 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO26 | GPIO27
100 #define CONFIG_QCA_GPIO_MASK_OUT GPIO18 |\
101 CONFIG_QCA_GPIO_MASK_LED_ACT_L
102 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
103 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
104 CONFIG_QCA_GPIO_MASK_LED_ACT_L
105 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
107 #elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
109 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO1 | GPIO13 |\
110 GPIO14 | GPIO15 | GPIO16 |\
112 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO27
113 #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\
114 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
115 CONFIG_QCA_GPIO_MASK_LED_ACT_H
116 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
117 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
118 CONFIG_QCA_GPIO_MASK_LED_ACT_L
119 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
121 #elif defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
122 defined(CONFIG_FOR_TPLINK_WR710N_V1)
124 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27
125 #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\
126 CONFIG_QCA_GPIO_MASK_LED_ACT_L
127 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
128 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
129 CONFIG_QCA_GPIO_MASK_LED_ACT_L
131 #elif defined(CONFIG_FOR_TPLINK_WR720N_V3)
133 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27
134 #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\
135 CONFIG_QCA_GPIO_MASK_LED_ACT_L
136 #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO18 | GPIO20
137 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
138 CONFIG_QCA_GPIO_MASK_LED_ACT_L
140 #elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
142 #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO1 | GPIO13 |\
143 GPIO14 | GPIO15 | GPIO16
144 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO27
145 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
146 CONFIG_QCA_GPIO_MASK_LED_ACT_H
147 #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO26
148 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
149 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
151 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
153 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27
154 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
155 #define CONFIG_QCA_GPIO_MASK_IN GPIO11
156 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
165 #if defined(CONFIG_FOR_GL_INET) ||\
166 defined(CONFIG_FOR_TPLINK_MR10U_V1) ||\
167 defined(CONFIG_FOR_TPLINK_MR13U_V1) ||\
168 defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\
169 defined(CONFIG_FOR_TPLINK_MR3040_V1V2) ||\
170 defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\
171 defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
172 defined(CONFIG_FOR_TPLINK_WR720N_V3) ||\
173 defined(CONFIG_FOR_TPLINK_WR740N_V4)
175 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
176 "rootfstype=squashfs init=/sbin/init "\
177 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
179 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
181 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
182 "rootfstype=squashfs init=/sbin/init "\
183 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
185 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
187 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 "\
188 "rootfstype=squashfs init=/sbin/init "\
189 "mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
191 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
193 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
194 "rootfstype=squashfs init=/sbin/init "\
195 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
197 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
199 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
200 "rootfstype=squashfs init=/sbin/init "\
201 "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)"
203 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
205 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
206 "rootfstype=squashfs init=/sbin/init "\
207 "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)"
209 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
210 defined(CONFIG_FOR_MESH_POTATO_V2)
212 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
213 "rootfstype=squashfs init=/sbin/init "\
214 "mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(art)"
219 * =============================
220 * Load address and boot command
221 * =============================
223 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
224 #define CFG_LOAD_ADDR 0x9F080000
225 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
226 #define CFG_LOAD_ADDR 0x9F050000
227 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
228 defined(CONFIG_FOR_MESH_POTATO_V2)
229 #define CFG_LOAD_ADDR 0x9F040000
230 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
231 #define CFG_LOAD_ADDR 0x9F030000
233 #define CFG_LOAD_ADDR 0x9F020000
236 #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
239 * =========================
240 * Environment configuration
241 * =========================
243 #if defined(CONFIG_FOR_DRAGINO_V2) ||\
244 defined(CONFIG_FOR_MESH_POTATO_V2)
245 #define CFG_ENV_ADDR 0x9F030000
246 #define CFG_ENV_SIZE 0x8000
247 #define CFG_ENV_SECT_SIZE 0x10000
248 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
249 #define CFG_ENV_ADDR 0x9F040000
250 #define CFG_ENV_SIZE 0x8000
251 #define CFG_ENV_SECT_SIZE 0x10000
252 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
253 #define CFG_ENV_ADDR 0x9F020000
254 #define CFG_ENV_SIZE 0x8000
255 #define CFG_ENV_SECT_SIZE 0x10000
257 #define CFG_ENV_ADDR 0x9F01EC00
258 #define CFG_ENV_SIZE 0x1000
259 #define CFG_ENV_SECT_SIZE 0x10000
263 * ===========================
264 * List of available baudrates
265 * ===========================
267 #define CFG_BAUDRATE_TABLE \
268 { 600, 1200, 2400, 4800, 9600, 14400, \
269 19200, 28800, 38400, 56000, 57600, 115200, \
270 128000, 153600, 230400, 250000, 256000, 460800, \
271 576000, 921600, 1000000, 1152000, 1500000, 2000000 }
274 * ==================================================
275 * MAC address/es, model and WPS pin offsets in FLASH
276 * ==================================================
278 #if defined(CONFIG_FOR_DRAGINO_V2) ||\
279 defined(CONFIG_FOR_MESH_POTATO_V2) ||\
280 defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
281 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
282 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
283 #define OFFSET_MAC_ADDRESS 0x000000
284 #define OFFSET_MAC_ADDRESS2 0x000006
285 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
286 #define OFFSET_MAC_DATA_BLOCK 0x010000
287 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
288 #define OFFSET_MAC_ADDRESS 0x00FC00
289 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
290 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
291 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
292 #define OFFSET_MAC_ADDRESS 0x000000
293 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
295 * DIR-505 has two MAC addresses inside dedicated MAC partition
296 * They are stored in plain text...
297 * TODO: read/write MAC stored as plain text
298 * #define OFFSET_MAC_DATA_BLOCK 0x02000
299 * #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
300 * #define OFFSET_MAC_ADDRESS 0x000004
301 * #define OFFSET_MAC_ADDRESS2 0x000016
304 #define OFFSET_MAC_DATA_BLOCK 0x010000
305 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
306 #define OFFSET_MAC_ADDRESS 0x00FC00
309 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) &&\
310 !defined(CONFIG_FOR_DLINK_DIR505_A1) &&\
311 !defined(CONFIG_FOR_GS_OOLITE_V1_DEV) &&\
312 !defined(CONFIG_FOR_DRAGINO_V2) &&\
313 !defined(CONFIG_FOR_MESH_POTATO_V2) &&\
314 !defined(CONFIG_FOR_GL_INET) &&\
315 !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
316 #define OFFSET_ROUTER_MODEL 0xFD00
319 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\
320 defined(CONFIG_FOR_TPLINK_WR740N_V4) ||\
321 defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\
322 defined(CONFIG_FOR_TPLINK_WR710N_V1)
323 #define OFFSET_PIN_NUMBER 0xFE00
327 * =========================
328 * Custom changes per device
329 * =========================
332 /* Dragino 2 uses different IP addresses */
333 #if defined(CONFIG_FOR_DRAGINO_V2)
335 #define CONFIG_IPADDR 192.168.255.1
337 #undef CONFIG_SERVERIP
338 #define CONFIG_SERVERIP 192.168.255.2
341 /* Dragino 2 and Black Swift boards use different prompts */
342 #if defined(CONFIG_FOR_DRAGINO_V2) ||\
343 defined(CONFIG_FOR_MESH_POTATO_V2)
345 #define CFG_PROMPT "dr_boot> "
346 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
348 #define CFG_PROMPT "BSB> "
351 /* D-Link DIR-505 is limited to 64 KB only and doesn't use env */
352 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
353 #define CFG_ENV_IS_NOWHERE 1
354 #undef CFG_ENV_IS_IN_FLASH
355 #undef CONFIG_CMD_DHCP
356 #undef CONFIG_CMD_SNTP
357 #undef CONFIG_CMD_IMI
358 #undef CONFIG_CMD_ENV
359 #undef CONFIG_CMD_LOADB
360 #undef CONFIG_CMD_BUTTON
361 #undef CONFIG_CMD_SLEEP
365 * ===========================
366 * HTTP recovery configuration
367 * ===========================
369 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
371 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
372 #define WEBFAILSAFE_UPLOAD_ART_ADDRESS (CFG_FLASH_BASE + 0x10000)
375 /* Firmware size limit */
376 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
377 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (512 * 1024)
378 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
379 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
380 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
381 defined(CONFIG_FOR_MESH_POTATO_V2)
382 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (320 * 1024)
383 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
384 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
385 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
386 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (256 * 1024)
388 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
393 * ========================
394 * PLL/Clocks configuration
395 * ========================
397 #define CONFIG_QCA_PLL QCA_PLL_PRESET_400_400_200
399 #if defined(CONFIG_FOR_DLINK_DIR505_A1) ||\
400 defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
402 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x20000
403 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
405 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
407 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000
408 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
410 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
411 defined(CONFIG_FOR_MESH_POTATO_V2)
413 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
414 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
418 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
419 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
423 #endif /* _AP121_H */