2 * This file contains the configuration parameters for the AP121 (AR9331) board.
8 #include <configs/ar7240.h>
12 * FLASH and environment organization
14 #define CFG_MAX_FLASH_BANKS 1
15 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
18 * We boot from this flash
20 #define CFG_FLASH_BASE 0x9F000000
21 #ifdef COMPRESSED_UBOOT
22 #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
23 #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
27 * The following #defines are needed to get flash environment right
29 #define CFG_MONITOR_BASE TEXT_BASE
30 #define CFG_MONITOR_LEN (192 << 10)
35 #undef CONFIG_BOOTARGS
37 #if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \
38 defined(CONFIG_FOR_TPLINK_WR720N_V3) || \
39 defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
40 defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \
41 defined(CONFIG_FOR_TPLINK_MR10U_V1) || \
42 defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
43 defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
44 defined(CONFIG_FOR_TPLINK_MR13U_V1)
46 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
48 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
50 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)"
52 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
54 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
56 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
58 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)"
63 * Other env default values
65 #undef CONFIG_BOOTFILE
66 #define CONFIG_BOOTFILE "firmware.bin"
68 #undef CONFIG_LOADADDR
69 #define CONFIG_LOADADDR 0x80800000
71 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
72 #define CFG_LOAD_ADDR 0x9F080000
73 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
74 #define CFG_LOAD_ADDR 0x9F050000
76 #define CFG_LOAD_ADDR 0x9F020000
79 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
80 #define CONFIG_BOOTCOMMAND "bootm 0x9F080000"
81 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
82 #define CONFIG_BOOTCOMMAND "bootm 0x9F050000"
84 #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
87 #define CONFIG_IPADDR 192.168.1.1
88 #define CONFIG_SERVERIP 192.168.1.2
92 #undef CPU_PLL_CONFIG_VAL1
93 #undef CPU_CLK_CONTROL_VAL2
95 // CPU-RAM-AHB frequency setting
96 #define CFG_PLL_FREQ CFG_PLL_400_400_200
99 * MIPS32 24K Processor Core Family Software User's Manual
101 * 6.2.9 Count Register (CP0 Register 9, Select 0)
102 * The Count register acts as a timer, incrementing at a constant
103 * rate, whether or not an instruction is executed, retired, or
104 * any forward progress is made through the pipeline. The counter
105 * increments every other clock, if the DC bit in the Cause register
108 * Since the count is incremented every other tick, divide by 2
109 * XXX derive this from CFG_PLL_FREQ
114 * CPU_PLL_DITHER_FRAC_VAL
116 * Value written into CPU PLL Dither FRAC Register (PLL_DITHER_FRAC)
118 * bits 0..9 NFRAC_MAX => 1000 (0x3E8)
119 * bits 10..13 NFRAC_MIN => 0 (minimum value is used)
120 * bits 20..29 NFRAC_STEP => 1
123 #define CPU_PLL_DITHER_FRAC_VAL 0x001003e8
126 * CPU_PLL_SETTLE_TIME_VAL
128 * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2)
130 * bits 0..11 SETTLE_TIME => 580 (0x352)
133 #if CONFIG_40MHZ_XTAL_SUPPORT
134 #define CPU_PLL_SETTLE_TIME_VAL 0x00000550
136 #define CPU_PLL_SETTLE_TIME_VAL 0x00000352
140 * CPU_CLK_CONTROL_VAL1
141 * CPU_CLK_CONTROL_VAL2
143 * Values written into CPU Clock Control Register CLOCK_CONTROL
144 * with PLL bypass disabled
146 * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0)
147 * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
148 * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
149 * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
154 * CPU_PLL_CONFIG_VAL1
155 * CPU_PLL_CONFIG_VAL2
157 * In CPU_PLL_CONFIG_VAL1 bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
158 * In CPU_PLL_CONFIG_VAL2 bit 30 is unset
160 * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG)
162 * bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20)
163 * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at valuse different than 1 (maybe need to change other dividers?)]
164 * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values]
165 * bits 23..25 (3bit) OUTDIV (Define the ratio betwee VCO output and PLL output => 1 (0x1)
166 * VCOOUT * (1/2^OUTDIV) = PLLOUT)
170 * = PLL CALCULATION (guess) =============
171 * PLL = (25 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz
173 * PLL = (40 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz
175 * CPU = PLL / CPU_POST_DIV
176 * DDR = PLL / DDR_POST_DIV
177 * AHB = PLL / AHB_POST_DIV
184 * Value written into SPI Control (SPI_CONTROL) register
186 * bits 0..5 (6bit) CLOCK_DIVIDER (Specifies the clock divider setting. Actual clock frequency would be (AHB_CLK / ((CLOCK_DIVIDER+1)*2)) )
187 * bits 6 (1bit) REMAP_DISABLE (Remaps 4 MB space over unless explicitly disabled by setting this bit to 1. If set to 1, 16 MB is accessible.)
191 #if (CFG_PLL_FREQ == CFG_PLL_400_400_200)
193 #define CFG_HZ (400000000LU/2)
195 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
196 #define CPU_CLK_CONTROL_VAL1 0x00018004
197 #define CPU_CLK_CONTROL_VAL2 0x00008000
199 #if CONFIG_40MHZ_XTAL_SUPPORT
200 // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz)
204 #define CPU_PLL_CONFIG_VAL1 0x40815000
205 #define CPU_PLL_CONFIG_VAL2 0x00815000
207 // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz)
211 #define CPU_PLL_CONFIG_VAL1 0x40818000
212 #define CPU_PLL_CONFIG_VAL2 0x00818000
215 // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
216 #define AR7240_SPI_CONTROL 0x42
218 #elif (CFG_PLL_FREQ == CFG_PLL_412_412_206)
220 #define CFG_HZ (412500000LU/2)
222 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
223 #define CPU_CLK_CONTROL_VAL1 0x00018004
224 #define CPU_CLK_CONTROL_VAL2 0x00008000
226 // DIV_INT = 33 (25 MHz * 33/2 = 412,5 MHz)
230 #define CPU_PLL_CONFIG_VAL1 0x40818400
231 #define CPU_PLL_CONFIG_VAL2 0x00818400
233 // CLOCK_DIVIDER = 2 (SPI clock = 206,25 / 6 ~ 34,4 MHz)
234 #define AR7240_SPI_CONTROL 0x42
236 #elif (CFG_PLL_FREQ == CFG_PLL_425_425_212)
238 #define CFG_HZ (425000000LU/2)
240 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
241 #define CPU_CLK_CONTROL_VAL1 0x00018004
242 #define CPU_CLK_CONTROL_VAL2 0x00008000
244 // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz)
248 #define CPU_PLL_CONFIG_VAL1 0x40818800
249 #define CPU_PLL_CONFIG_VAL2 0x00818800
251 // CLOCK_DIVIDER = 2 (SPI clock = 212,5 / 6 ~ 35,4 MHz)
252 #define AR7240_SPI_CONTROL 0x42
254 #elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
256 #define CFG_HZ (437500000LU/2)
258 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
259 #define CPU_CLK_CONTROL_VAL1 0x00018004
260 #define CPU_CLK_CONTROL_VAL2 0x00008000
262 // DIV_INT = 35 (25 MHz * 35/2 = 437,5 MHz)
266 #define CPU_PLL_CONFIG_VAL1 0x40818C00
267 #define CPU_PLL_CONFIG_VAL2 0x00818C00
269 // CLOCK_DIVIDER = 2 (SPI clock = 218,75 / 6 ~ 36,5 MHz)
270 #define AR7240_SPI_CONTROL 0x42
273 #elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
275 #define CFG_HZ (450000000LU/2)
277 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
278 #define CPU_CLK_CONTROL_VAL1 0x00018004
279 #define CPU_CLK_CONTROL_VAL2 0x00008000
281 // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz)
285 #define CPU_PLL_CONFIG_VAL1 0x40819000
286 #define CPU_PLL_CONFIG_VAL2 0x00819000
288 // CLOCK_DIVIDER = 3 (SPI clock = 225 / 6 ~ 37,5 MHz)
289 #define AR7240_SPI_CONTROL 0x42
291 #elif (CFG_PLL_FREQ == CFG_PLL_462_462_231)
293 #define CFG_HZ (462500000LU/2)
295 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
296 #define CPU_CLK_CONTROL_VAL1 0x00018004
297 #define CPU_CLK_CONTROL_VAL2 0x00008000
299 // DIV_INT = 37 (25 MHz * 37/2 = 462,5 MHz)
303 #define CPU_PLL_CONFIG_VAL1 0x40819400
304 #define CPU_PLL_CONFIG_VAL2 0x00819400
306 // CLOCK_DIVIDER = 3 (SPI clock = 231,25 / 6 ~ 38,5 MHz)
307 #define AR7240_SPI_CONTROL 0x42
309 #elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
311 #define CFG_HZ (475000000LU/2)
313 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
314 #define CPU_CLK_CONTROL_VAL1 0x00018004
315 #define CPU_CLK_CONTROL_VAL2 0x00008000
317 // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz)
321 #define CPU_PLL_CONFIG_VAL1 0x40819800
322 #define CPU_PLL_CONFIG_VAL2 0x00819800
324 // CLOCK_DIVIDER = 3 (SPI clock = 237,5 / 6 ~ 39,6 MHz)
325 #define AR7240_SPI_CONTROL 0x42
327 #elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
329 #define CFG_HZ (487500000LU/2)
331 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
332 #define CPU_CLK_CONTROL_VAL1 0x00018004
333 #define CPU_CLK_CONTROL_VAL2 0x00008000
335 // DIV_INT = 39 (25 MHz * 39/2 = 487,5 MHz)
339 #define CPU_PLL_CONFIG_VAL1 0x40819C00
340 #define CPU_PLL_CONFIG_VAL2 0x00819C00
342 // CLOCK_DIVIDER = 3 (SPI clock = 243,75 / 8 ~ 30,5 MHz)
343 #define AR7240_SPI_CONTROL 0x43
346 #elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
348 #define CFG_HZ (500000000LU/2)
350 // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
351 #define CPU_CLK_CONTROL_VAL1 0x00018004
352 #define CPU_CLK_CONTROL_VAL2 0x00008000
354 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz)
358 #define CPU_PLL_CONFIG_VAL1 0x4081A000
359 #define CPU_PLL_CONFIG_VAL2 0x0081A000
361 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
362 #define AR7240_SPI_CONTROL 0x43
364 #elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
366 #define CFG_HZ (500000000LU/2)
368 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
369 #define CPU_CLK_CONTROL_VAL1 0x00018404
370 #define CPU_CLK_CONTROL_VAL2 0x00008400
372 // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz)
376 #define CPU_PLL_CONFIG_VAL1 0x4081A000
377 #define CPU_PLL_CONFIG_VAL2 0x0081A000
379 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
380 #define AR7240_SPI_CONTROL 0x43
382 #elif (CFG_PLL_FREQ == CFG_PLL_562_281_140)
384 #define CFG_HZ (562500000LU/2)
386 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
387 #define CPU_CLK_CONTROL_VAL1 0x00018404
388 #define CPU_CLK_CONTROL_VAL2 0x00018400
390 // DIV_INT = 45 (25 MHz * 45/2 = 562,5 MHz)
394 #define CPU_PLL_CONFIG_VAL1 0x4081B400
395 #define CPU_PLL_CONFIG_VAL2 0x0081B400
397 // CLOCK_DIVIDER = 1 (SPI clock = 140,625 / 4 ~ 35,2 MHz)
398 #define AR7240_SPI_CONTROL 0x41
400 #elif (CFG_PLL_FREQ == CFG_PLL_525_262_131)
402 #define CFG_HZ (525000000LU/2)
404 // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
405 #define CPU_CLK_CONTROL_VAL1 0x00018404
406 #define CPU_CLK_CONTROL_VAL2 0x00018400
408 // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz)
412 #define CPU_PLL_CONFIG_VAL1 0x4081A800
413 #define CPU_PLL_CONFIG_VAL2 0x0081A800
415 // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz)
416 #define AR7240_SPI_CONTROL 0x41
421 * Cache lock for stack
423 #define CFG_INIT_SP_OFFSET 0x1000
426 * Address and size of Primary Environment Sector
428 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
429 #define CFG_ENV_IS_IN_FLASH 1
430 #undef CFG_ENV_IS_NOWHERE
432 #undef CFG_ENV_IS_IN_FLASH
433 #define CFG_ENV_IS_NOWHERE 1
436 #define CFG_ENV_ADDR 0x9F040000
437 #define CFG_ENV_SIZE 0x10000
442 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
443 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_DATE | CFG_CMD_IMI )
444 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
445 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_RUN | CFG_CMD_DATE | CFG_CMD_IMI | CFG_CMD_SNTP)
447 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_PING )
450 // Enable NetConsole and custom NetConsole port
451 #define CONFIG_NETCONSOLE
452 #define CONFIG_NETCONSOLE_PORT 6666
454 /* DDR init values */
455 #if CONFIG_40MHZ_XTAL_SUPPORT
456 #define CFG_DDR_REFRESH_VAL 0x4270
458 #define CFG_DDR_REFRESH_VAL 0x4186
461 #define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
462 #define CFG_DDR_MODE_VAL_INIT 0x133
464 #ifdef LOW_DRIVE_STRENGTH
465 #define CFG_DDR_EXT_MODE_VAL 0x2
467 #define CFG_DDR_EXT_MODE_VAL 0x0
470 #define CFG_DDR_MODE_VAL 0x33
471 #define CFG_DDR_TRTW_VAL 0x1f
472 #define CFG_DDR_TWTR_VAL 0x1e
474 //#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0
475 #define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1
476 #define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff
477 #define CFG_DDR_TAP0_VAL 0x8
478 #define CFG_DDR_TAP1_VAL 0x9
480 /* DDR2 Init values */
481 #define CFG_DDR2_EXT_MODE_VAL 0x402
483 #define CONFIG_NET_MULTI
485 /* choose eth1 first for tftpboot interface added by ZJin, 110328 */
486 #define CONFIG_AG7240_SPEPHY
489 * Web Failsafe configuration
491 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
493 // U-Boot partition size and offset
494 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
496 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
497 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024)
498 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
499 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (256 * 1024)
501 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024)
504 // Firmware partition offset
505 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
506 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x80000
507 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
508 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000
510 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
513 // ART partition size and offset
514 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
515 #define WEBFAILSAFE_UPLOAD_ART_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x10000
518 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
520 // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
521 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
522 // D-Link DIR-505: 64k(U-Boot),64k(ART),64k(MAC),64k(NVRAM),256k(Language)
523 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (512 * 1024)
524 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
525 // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART)
526 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
528 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
529 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
532 // progress state info
533 #define WEBFAILSAFE_PROGRESS_START 0
534 #define WEBFAILSAFE_PROGRESS_TIMEOUT 1
535 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
536 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
537 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
540 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
541 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
542 #define WEBFAILSAFE_UPGRADE_TYPE_ART 2
544 /*-----------------------------------------------------------------------*/
546 #define CFG_ATHRS26_PHY 1
547 #define CFG_AG7240_NMACS 2
548 #define CFG_MII0_RMII 1
549 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
552 #define milisecdelay(_x) udelay((_x) * 1000)
554 /* MAC address, model and PIN number offsets in FLASH */
555 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
556 // DIR-505 has two MAC addresses inside dedicated MAC partition
557 // They are stored in plain text... TODO: read/write MAC stored as plain text
558 //#define OFFSET_MAC_DATA_BLOCK 0x020000
559 //#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
560 //#define OFFSET_MAC_ADDRESS 0x000004
561 //#define OFFSET_MAC_ADDRESS2 0x000016
562 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
563 #define OFFSET_MAC_DATA_BLOCK 0xFF0000
564 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
565 #define OFFSET_MAC_ADDRESS 0x000000 // Carambola 2 has two MAC addresses at the beginning of ART partition
566 #define OFFSET_MAC_ADDRESS2 0x000006
568 #define OFFSET_MAC_DATA_BLOCK 0x010000
569 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
570 #define OFFSET_MAC_ADDRESS 0x00FC00
573 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
574 !defined(CONFIG_FOR_DLINK_DIR505_A1)
575 #define OFFSET_ROUTER_MODEL 0x00FD00
578 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \
579 defined(CONFIG_FOR_TPLINK_WR740N_V4) || \
580 defined(CONFIG_FOR_TPLINK_MR3220_V2) || \
581 defined(CONFIG_FOR_TPLINK_WR710N_V1)
582 #define OFFSET_PIN_NUMBER 0x00FE00
585 #include <cmd_confdefs.h>
587 #endif /* __CONFIG_H */