u-boot/include/cmd_qcaclk.h

   1 /*
   2  * Commands related with PLL/clocks settings
   3  * for Qualcomm/Atheros WiSoCs
   4  *
   5  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #ifndef _CMD_QCACLK_H_
  11 #define _CMD_QCACLK_H_
  12
  13 #include <soc/qca_soc_common.h>
  14 #if (SOC_TYPE & QCA_AR933X_SOC)
  15         #include <soc/ar933x_pll_init.h>
  16 #else
  17         #include <soc/qca95xx_pll_init.h>
  18 #endif
  19
  20 #ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
  21
  22         #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET
  23                 #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET"
  24         #endif
  25
  26         #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE
  27                 #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE"
  28         #endif
  29
  30         #if (SOC_TYPE & QCA_AR933X_SOC)
  31 typedef struct {
  32         u32 cpu_pll_cfg;
  33         u32 cpu_clk_ctrl;
  34         u32 cpu_pll_dit;
  35 } pll_regs;
  36         #else
  37 typedef struct {
  38         u32 cpu_pll_cfg;
  39         u32 ddr_pll_cfg;
  40         u32 cpu_ddr_clk_ctrl;
  41         u32 cpu_pll_dit;
  42         u32 ddr_pll_dit;
  43 } pll_regs;
  44         #endif /* SOC_TYPE & QCA_AR933X_SOC */
  45
  46 typedef struct {
  47         u32 spi_ctrl;
  48         pll_regs regs;
  49 } clk_cfg_flash;
  50
  51 /*
  52  * Contains:
  53  * 1. CPU, RAM, AHB and SPI clocks [MHz]
  54  * 2. Target SPI_CONTROL register value
  55  * 3. Target PLL related register values,
  56  *    for 25 and 40 MHz XTAL types
  57  */
  58 typedef struct {
  59         u16 cpu_clk;
  60         u16 ddr_clk;
  61         u16 ahb_clk;
  62         u8  spi_clk;
  63
  64         u32 spi_ctrl;
  65
  66         pll_regs xtal_25mhz;
  67         pll_regs xtal_40mhz;
  68 } clk_profile;
  69
  70 static const clk_profile clk_profiles[] = {
  71         #if (SOC_TYPE & QCA_AR933X_SOC)
  72         {
  73                 /* Tested! */
  74                 100, 100, 50, 12,
  75                 _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
  76                 {
  77                         _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1),
  78                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
  79                         _ar933x_cpu_pll_dither_frac_reg_val(0)
  80                 }, {
  81                         _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1),
  82                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
  83                         _ar933x_cpu_pll_dither_frac_reg_val(0)
  84                 },
  85         },
  86         {
  87                 /* Tested! */
  88                 100, 100, 100, 25,
  89                 _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
  90                 {
  91                         _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
  92                         _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
  93                         _ar933x_cpu_pll_dither_frac_reg_val(0)
  94                 }, {
  95                         _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
  96                         _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
  97                         _ar933x_cpu_pll_dither_frac_reg_val(0)
  98                 },
  99         },
 100         {
 101                 /* Tested! */
 102                 150, 150, 150, 25,
 103                 _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
 104                 {
 105                         _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
 106                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
 107                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 108                 }, {
 109                         _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
 110                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
 111                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 112                 },
 113         },
 114         {
 115                 /* Tested! */
 116                 160, 160, 80, 20,
 117                 _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
 118                 {
 119                         _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
 120                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
 121                         _ar933x_cpu_pll_dither_frac_reg_val(615)
 122                 }, {
 123                         _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1),
 124                         _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
 125                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 126                 },
 127         },
 128         {
 129                 /* Tested! */
 130                 200, 200, 100, 25,
 131                 _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
 132                 {
 133                         _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
 134                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 135                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 136                 }, {
 137                         _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2),
 138                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 139                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 140                 },
 141         },
 142         {
 143                 /* Tested! */
 144                 200, 200, 200, 25,
 145                 _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
 146                 {
 147                         _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
 148                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
 149                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 150                 }, {
 151                         _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2),
 152                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
 153                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 154                 },
 155         },
 156         {
 157                 /* Tested! */
 158                 300, 300, 150, 25,
 159                 _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
 160                 {
 161                         _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
 162                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 163                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 164                 }, {
 165                         _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
 166                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 167                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 168                 },
 169         },
 170         {
 171                 /* Tested! */
 172                 350, 350, 175, 29,
 173                 _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
 174                 {
 175                         _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
 176                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 177                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 178                 }, {
 179                         _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1),
 180                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 181                         _ar933x_cpu_pll_dither_frac_reg_val(512)
 182                 },
 183         },
 184         {
 185                 /* Tested! */
 186                 400, 400, 200, 25,
 187                 _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
 188                 {
 189                         _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
 190                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 191                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 192                 }, {
 193                         _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
 194                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 195                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 196                 },
 197         },
 198         {
 199                 /* Tested! */
 200                 500, 500, 250, 25,
 201                 _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
 202                 {
 203                         _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
 204                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 205                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 206                 }, {
 207                         _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
 208                         _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
 209                         _ar933x_cpu_pll_dither_frac_reg_val(0)
 210                 },
 211         },
 212         #else
 213         {
 214                 25, 25, 12, 1,
 215                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 216                 {
 217                         _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0),
 218                         _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0),
 219                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 220                         _qca95xx_cpu_pll_dither_reg_val(0),
 221                         _qca95xx_ddr_pll_dither_reg_val(0)
 222                 }, {
 223                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 224                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 225                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1),
 226                         _qca95xx_cpu_pll_dither_reg_val(0),
 227                         _qca95xx_ddr_pll_dither_reg_val(0)
 228                 },
 229         }, {
 230                 25, 25, 25, 3,
 231                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 232                 {
 233                         _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0),
 234                         _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0),
 235                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 236                         _qca95xx_cpu_pll_dither_reg_val(0),
 237                         _qca95xx_ddr_pll_dither_reg_val(0)
 238                 }, {
 239                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 240                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 241                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1),
 242                         _qca95xx_cpu_pll_dither_reg_val(0),
 243                         _qca95xx_ddr_pll_dither_reg_val(0)
 244                 },
 245         }, {
 246                 50, 50, 25, 3,
 247                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 248                 {
 249                         _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0),
 250                         _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
 251                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 252                         _qca95xx_cpu_pll_dither_reg_val(0),
 253                         _qca95xx_ddr_pll_dither_reg_val(0)
 254                 }, {
 255                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 256                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 257                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 258                         _qca95xx_cpu_pll_dither_reg_val(0),
 259                         _qca95xx_ddr_pll_dither_reg_val(0)
 260                 },
 261         }, {
 262                 50, 50, 50, 6,
 263                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 264                 {
 265                         _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0),
 266                         _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
 267                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 268                         _qca95xx_cpu_pll_dither_reg_val(0),
 269                         _qca95xx_ddr_pll_dither_reg_val(0)
 270                 }, {
 271                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 272                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 273                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
 274                         _qca95xx_cpu_pll_dither_reg_val(0),
 275                         _qca95xx_ddr_pll_dither_reg_val(0)
 276                 },
 277         }, {
 278                 75, 75, 25, 3,
 279                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 280                 {
 281                         _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
 282                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 283                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
 284                         _qca95xx_cpu_pll_dither_reg_val(0),
 285                         _qca95xx_ddr_pll_dither_reg_val(0)
 286                 }, {
 287                         _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
 288                         _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
 289                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
 290                         _qca95xx_cpu_pll_dither_reg_val(0),
 291                         _qca95xx_ddr_pll_dither_reg_val(0)
 292                 },
 293         }, {
 294                 75, 75, 50, 6,
 295                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 296                 {
 297                         _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
 298                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 299                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
 300                         _qca95xx_cpu_pll_dither_reg_val(0),
 301                         _qca95xx_ddr_pll_dither_reg_val(0)
 302                 }, {
 303                         _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
 304                         _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
 305                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
 306                         _qca95xx_cpu_pll_dither_reg_val(0),
 307                         _qca95xx_ddr_pll_dither_reg_val(0)
 308                 },
 309         }, {
 310                 75, 75, 75, 9,
 311                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 312                 {
 313                         _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
 314                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 315                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
 316                         _qca95xx_cpu_pll_dither_reg_val(0),
 317                         _qca95xx_ddr_pll_dither_reg_val(0)
 318                 }, {
 319                         _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0),
 320                         _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
 321                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
 322                         _qca95xx_cpu_pll_dither_reg_val(0),
 323                         _qca95xx_ddr_pll_dither_reg_val(0)
 324                 },
 325         }, {
 326                 100, 100, 25, 3,
 327                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 328                 {
 329                         _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
 330                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 331                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
 332                         _qca95xx_cpu_pll_dither_reg_val(0),
 333                         _qca95xx_ddr_pll_dither_reg_val(0)
 334                 }, {
 335                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 336                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 337                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
 338                         _qca95xx_cpu_pll_dither_reg_val(0),
 339                         _qca95xx_ddr_pll_dither_reg_val(0)
 340                 },
 341         }, {
 342                 100, 100, 50, 6,
 343                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 344                 {
 345                         _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
 346                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 347                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 348                         _qca95xx_cpu_pll_dither_reg_val(0),
 349                         _qca95xx_ddr_pll_dither_reg_val(0)
 350                 }, {
 351                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 352                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 353                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 354                         _qca95xx_cpu_pll_dither_reg_val(0),
 355                         _qca95xx_ddr_pll_dither_reg_val(0)
 356                 },
 357         }, {
 358                 100, 100, 100, 12,
 359                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 360                 {
 361                         _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0),
 362                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 363                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 364                         _qca95xx_cpu_pll_dither_reg_val(0),
 365                         _qca95xx_ddr_pll_dither_reg_val(0)
 366                 }, {
 367                         _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0),
 368                         _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0),
 369                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 370                         _qca95xx_cpu_pll_dither_reg_val(0),
 371                         _qca95xx_ddr_pll_dither_reg_val(0)
 372                 },
 373         }, {
 374                 125, 50, 25, 3,
 375                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 376                 {
 377                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 378                         _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
 379                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 380                         _qca95xx_cpu_pll_dither_reg_val(0),
 381                         _qca95xx_ddr_pll_dither_reg_val(0)
 382                 }, {
 383                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 384                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 385                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 386                         _qca95xx_cpu_pll_dither_reg_val(0),
 387                         _qca95xx_ddr_pll_dither_reg_val(0)
 388                 },
 389         }, {
 390                 125, 50, 50, 6,
 391                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 392                 {
 393                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 394                         _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
 395                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 396                         _qca95xx_cpu_pll_dither_reg_val(0),
 397                         _qca95xx_ddr_pll_dither_reg_val(0)
 398                 }, {
 399                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 400                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 401                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
 402                         _qca95xx_cpu_pll_dither_reg_val(0),
 403                         _qca95xx_ddr_pll_dither_reg_val(0)
 404                 },
 405         }, {
 406                 125, 62, 25, 3,
 407                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 408                 {
 409                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 410                         _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
 411                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1),
 412                         _qca95xx_cpu_pll_dither_reg_val(0),
 413                         _qca95xx_ddr_pll_dither_reg_val(0)
 414                 }, {
 415                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 416                         _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
 417                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1),
 418                         _qca95xx_cpu_pll_dither_reg_val(0),
 419                         _qca95xx_ddr_pll_dither_reg_val(0)
 420                 },
 421         }, {
 422                 125, 62, 50, 6,
 423                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 424                 {
 425                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 426                         _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0),
 427                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
 428                         _qca95xx_cpu_pll_dither_reg_val(0),
 429                         _qca95xx_ddr_pll_dither_reg_val(0)
 430                 }, {
 431                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 432                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 433                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1),
 434                         _qca95xx_cpu_pll_dither_reg_val(0),
 435                         _qca95xx_ddr_pll_dither_reg_val(0)
 436                 },
 437         }, {
 438                 125, 62, 62, 7,
 439                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 440                 {
 441                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 442                         _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
 443                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
 444                         _qca95xx_cpu_pll_dither_reg_val(0),
 445                         _qca95xx_ddr_pll_dither_reg_val(0)
 446                 }, {
 447                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 448                         _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
 449                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1),
 450                         _qca95xx_cpu_pll_dither_reg_val(0),
 451                         _qca95xx_ddr_pll_dither_reg_val(0)
 452                 },
 453         }, {
 454                 125, 100, 25, 3,
 455                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 456                 {
 457                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 458                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 459                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
 460                         _qca95xx_cpu_pll_dither_reg_val(0),
 461                         _qca95xx_ddr_pll_dither_reg_val(0)
 462                 }, {
 463                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 464                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 465                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1),
 466                         _qca95xx_cpu_pll_dither_reg_val(0),
 467                         _qca95xx_ddr_pll_dither_reg_val(0)
 468                 },
 469         }, {
 470                 125, 100, 50, 6,
 471                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 472                 {
 473                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 474                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 475                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 476                         _qca95xx_cpu_pll_dither_reg_val(0),
 477                         _qca95xx_ddr_pll_dither_reg_val(0)
 478                 }, {
 479                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 480                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 481                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1),
 482                         _qca95xx_cpu_pll_dither_reg_val(0),
 483                         _qca95xx_ddr_pll_dither_reg_val(0)
 484                 },
 485         }, {
 486                 125, 100, 62, 7,
 487                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 488                 {
 489                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 490                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 491                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
 492                         _qca95xx_cpu_pll_dither_reg_val(0),
 493                         _qca95xx_ddr_pll_dither_reg_val(0)
 494                 }, {
 495                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 496                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 497                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 0),
 498                         _qca95xx_cpu_pll_dither_reg_val(0),
 499                         _qca95xx_ddr_pll_dither_reg_val(0)
 500                 },
 501         }, {
 502                 125, 100, 100, 12,
 503                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 504                 {
 505                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 506                         _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0),
 507                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 508                         _qca95xx_cpu_pll_dither_reg_val(0),
 509                         _qca95xx_ddr_pll_dither_reg_val(0)
 510                 }, {
 511                         _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0),
 512                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 513                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1),
 514                         _qca95xx_cpu_pll_dither_reg_val(0),
 515                         _qca95xx_ddr_pll_dither_reg_val(0)
 516                 },
 517         }, {
 518                 150, 150, 75, 9,
 519                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 520                 {
 521                         _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
 522                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 523                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 524                         _qca95xx_cpu_pll_dither_reg_val(0),
 525                         _qca95xx_ddr_pll_dither_reg_val(0)
 526                 }, {
 527                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 528                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 529                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 530                         _qca95xx_cpu_pll_dither_reg_val(0),
 531                         _qca95xx_ddr_pll_dither_reg_val(0)
 532                 },
 533         }, {
 534                 150, 150, 100, 12,
 535                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 536                 {
 537                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 538                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 539                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
 540                         _qca95xx_cpu_pll_dither_reg_val(0),
 541                         _qca95xx_ddr_pll_dither_reg_val(0)
 542                 }, {
 543                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 544                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 545                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
 546                         _qca95xx_cpu_pll_dither_reg_val(0),
 547                         _qca95xx_ddr_pll_dither_reg_val(0)
 548                 },
 549         }, {
 550                 150, 150, 150, 18,
 551                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 552                 {
 553                         _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0),
 554                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 555                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 556                         _qca95xx_cpu_pll_dither_reg_val(0),
 557                         _qca95xx_ddr_pll_dither_reg_val(0)
 558                 }, {
 559                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 560                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 561                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
 562                         _qca95xx_cpu_pll_dither_reg_val(0),
 563                         _qca95xx_ddr_pll_dither_reg_val(0)
 564                 },
 565         }, {
 566                 160, 160, 80, 10,
 567                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 568                 {
 569                         _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0),
 570                         _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0),
 571                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 572                         _qca95xx_cpu_pll_dither_reg_val(0),
 573                         _qca95xx_ddr_pll_dither_reg_val(0)
 574                 }, {
 575                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0),
 576                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0),
 577                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 578                         _qca95xx_cpu_pll_dither_reg_val(0),
 579                         _qca95xx_ddr_pll_dither_reg_val(0)
 580                 },
 581         }, {
 582                 170, 170, 85, 10,
 583                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 584                 {
 585                         _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0),
 586                         _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0),
 587                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1),
 588                         _qca95xx_cpu_pll_dither_reg_val(0),
 589                         _qca95xx_ddr_pll_dither_reg_val(0)
 590                 }, {
 591                         _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0),
 592                         _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0),
 593                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 594                         _qca95xx_cpu_pll_dither_reg_val(0),
 595                         _qca95xx_ddr_pll_dither_reg_val(0)
 596                 },
 597         }, {
 598                 180, 180, 90, 11,
 599                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 600                 {
 601                         _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0),
 602                         _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0),
 603                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 604                         _qca95xx_cpu_pll_dither_reg_val(0),
 605                         _qca95xx_ddr_pll_dither_reg_val(0)
 606                 }, {
 607                         _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0),
 608                         _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0),
 609                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 610                         _qca95xx_cpu_pll_dither_reg_val(0),
 611                         _qca95xx_ddr_pll_dither_reg_val(0)
 612                 },
 613         }, {
 614                 200, 200, 100, 12,
 615                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 616                 {
 617                         _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
 618                         _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
 619                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 620                         _qca95xx_cpu_pll_dither_reg_val(0),
 621                         _qca95xx_ddr_pll_dither_reg_val(0)
 622                 }, {
 623                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 624                         _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
 625                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 626                         _qca95xx_cpu_pll_dither_reg_val(0),
 627                         _qca95xx_ddr_pll_dither_reg_val(0)
 628                 }
 629         }, {
 630                 200, 200, 150, 18,
 631                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 632                 {
 633                         _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
 634                         _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0),
 635                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 636                         _qca95xx_cpu_pll_dither_reg_val(0),
 637                         _qca95xx_ddr_pll_dither_reg_val(0)
 638                 }, {
 639                         _qca95xx_cpu_pll_cfg_reg_val(5,  1, 1, 0, 0),
 640                         _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0),
 641                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 642                         _qca95xx_cpu_pll_dither_reg_val(0),
 643                         _qca95xx_ddr_pll_dither_reg_val(0)
 644                 }
 645         }, {
 646                 200, 200, 200, 25,
 647                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 648                 {
 649                         _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0),
 650                         _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
 651                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 652                         _qca95xx_cpu_pll_dither_reg_val(0),
 653                         _qca95xx_ddr_pll_dither_reg_val(0)
 654                 }, {
 655                         _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0),
 656                         _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
 657                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 658                         _qca95xx_cpu_pll_dither_reg_val(0),
 659                         _qca95xx_ddr_pll_dither_reg_val(0)
 660                 }
 661         }, {
 662                 300, 200, 100, 12,
 663                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 664                 {
 665                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 666                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 667                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 668                         _qca95xx_cpu_pll_dither_reg_val(0),
 669                         _qca95xx_ddr_pll_dither_reg_val(0)
 670                 }, {
 671                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 672                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 673                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 674                         _qca95xx_cpu_pll_dither_reg_val(0),
 675                         _qca95xx_ddr_pll_dither_reg_val(0)
 676                 }
 677         }, {
 678                 300, 200, 150, 18,
 679                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 680                 {
 681                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 682                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 683                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
 684                         _qca95xx_cpu_pll_dither_reg_val(0),
 685                         _qca95xx_ddr_pll_dither_reg_val(0)
 686                 }, {
 687                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 688                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 689                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
 690                         _qca95xx_cpu_pll_dither_reg_val(0),
 691                         _qca95xx_ddr_pll_dither_reg_val(0)
 692                 }
 693         }, {
 694                 300, 200, 200, 25,
 695                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 696                 {
 697                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 698                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 699                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 700                         _qca95xx_cpu_pll_dither_reg_val(0),
 701                         _qca95xx_ddr_pll_dither_reg_val(0)
 702                 }, {
 703                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 704                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 705                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 706                         _qca95xx_cpu_pll_dither_reg_val(0),
 707                         _qca95xx_ddr_pll_dither_reg_val(0)
 708                 }
 709         }, {
 710                 300, 300, 100, 12,
 711                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 712                 {
 713                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 714                         _qca95xx_ddr_pll_cfg_reg_val(4,  1, 1, 0, 0),
 715                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 716                         _qca95xx_cpu_pll_dither_reg_val(0),
 717                         _qca95xx_ddr_pll_dither_reg_val(0)
 718                 }, {
 719                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 720                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
 721                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 722                         _qca95xx_cpu_pll_dither_reg_val(0),
 723                         _qca95xx_ddr_pll_dither_reg_val(0)
 724                 }
 725         }, {
 726                 300, 300, 150, 18,
 727                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 728                 {
 729                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 730                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 731                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 732                         _qca95xx_cpu_pll_dither_reg_val(0),
 733                         _qca95xx_ddr_pll_dither_reg_val(0)
 734                 }, {
 735                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 736                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 737                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 738                         _qca95xx_cpu_pll_dither_reg_val(0),
 739                         _qca95xx_ddr_pll_dither_reg_val(0)
 740                 },
 741         }, {
 742                 300, 300, 200, 25,
 743                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 744                 {
 745                         _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0),
 746                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 747                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 748                         _qca95xx_cpu_pll_dither_reg_val(0),
 749                         _qca95xx_ddr_pll_dither_reg_val(0)
 750                 }, {
 751                         _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0),
 752                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 753                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 754                         _qca95xx_cpu_pll_dither_reg_val(0),
 755                         _qca95xx_ddr_pll_dither_reg_val(0)
 756                 },
 757         }, {
 758                 350, 350, 175, 21,
 759                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 760                 {
 761                         _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0),
 762                         _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0),
 763                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 764                         _qca95xx_cpu_pll_dither_reg_val(0),
 765                         _qca95xx_ddr_pll_dither_reg_val(0)
 766                 }, {
 767                         _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0),
 768                         _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0),
 769                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 770                         _qca95xx_cpu_pll_dither_reg_val(0),
 771                         _qca95xx_ddr_pll_dither_reg_val(0)
 772                 },
 773         }, {
 774                 360, 360, 180, 22,
 775                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 776                 {
 777                         _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0),
 778                         _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0),
 779                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
 780                         _qca95xx_cpu_pll_dither_reg_val(0),
 781                         _qca95xx_ddr_pll_dither_reg_val(0)
 782                 }, {
 783                         _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0),
 784                         _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0),
 785                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 786                         _qca95xx_cpu_pll_dither_reg_val(0),
 787                         _qca95xx_ddr_pll_dither_reg_val(0)
 788                 },
 789         }, {
 790                 380, 380, 190, 23,
 791                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 792                 {
 793                         _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0),
 794                         _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0),
 795                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 796                         _qca95xx_cpu_pll_dither_reg_val(0),
 797                         _qca95xx_ddr_pll_dither_reg_val(0)
 798                 }, {
 799                         _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0),
 800                         _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0),
 801                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 802                         _qca95xx_cpu_pll_dither_reg_val(0),
 803                         _qca95xx_ddr_pll_dither_reg_val(0)
 804                 },
 805         }, {
 806                 400, 200, 100, 12,
 807                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 808                 {
 809                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 810                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 811                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 812                         _qca95xx_cpu_pll_dither_reg_val(0),
 813                         _qca95xx_ddr_pll_dither_reg_val(0)
 814                 }, {
 815                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 816                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 817                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 818                         _qca95xx_cpu_pll_dither_reg_val(0),
 819                         _qca95xx_ddr_pll_dither_reg_val(0)
 820                 },
 821         }, {
 822                 400, 200, 150, 18,
 823                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 824                 {
 825                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 826                         _qca95xx_ddr_pll_cfg_reg_val(6,  1, 1, 0, 0),
 827                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
 828                         _qca95xx_cpu_pll_dither_reg_val(0),
 829                         _qca95xx_ddr_pll_dither_reg_val(0)
 830                 }, {
 831                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 832                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 833                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
 834                         _qca95xx_cpu_pll_dither_reg_val(0),
 835                         _qca95xx_ddr_pll_dither_reg_val(0)
 836                 },
 837         }, {
 838                 400, 200, 200, 25,
 839                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 840                 {
 841                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 842                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 843                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 844                         _qca95xx_cpu_pll_dither_reg_val(0),
 845                         _qca95xx_ddr_pll_dither_reg_val(0)
 846                 }, {
 847                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 848                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 849                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 850                         _qca95xx_cpu_pll_dither_reg_val(0),
 851                         _qca95xx_ddr_pll_dither_reg_val(0)
 852                 },
 853         }, {
 854                 400, 300, 100, 12,
 855                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 856                 {
 857                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 858                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 859                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
 860                         _qca95xx_cpu_pll_dither_reg_val(0),
 861                         _qca95xx_ddr_pll_dither_reg_val(0)
 862                 }, {
 863                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 864                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 865                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
 866                         _qca95xx_cpu_pll_dither_reg_val(0),
 867                         _qca95xx_ddr_pll_dither_reg_val(0)
 868                 },
 869         }, {
 870                 400, 300, 150, 18,
 871                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 872                 {
 873                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 874                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 875                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 876                         _qca95xx_cpu_pll_dither_reg_val(0),
 877                         _qca95xx_ddr_pll_dither_reg_val(0)
 878                 }, {
 879                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 880                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 881                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 882                         _qca95xx_cpu_pll_dither_reg_val(0),
 883                         _qca95xx_ddr_pll_dither_reg_val(0)
 884                 },
 885         }, {
 886                 400, 300, 200, 25,
 887                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 888                 {
 889                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 890                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 891                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
 892                         _qca95xx_cpu_pll_dither_reg_val(0),
 893                         _qca95xx_ddr_pll_dither_reg_val(0)
 894                 }, {
 895                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 896                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 897                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
 898                         _qca95xx_cpu_pll_dither_reg_val(0),
 899                         _qca95xx_ddr_pll_dither_reg_val(0)
 900                 },
 901         }, {
 902                 400, 300, 300, 25,
 903                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
 904                 {
 905                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 906                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 907                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 908                         _qca95xx_cpu_pll_dither_reg_val(0),
 909                         _qca95xx_ddr_pll_dither_reg_val(0)
 910                 }, {
 911                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 912                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 913                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 914                         _qca95xx_cpu_pll_dither_reg_val(0),
 915                         _qca95xx_ddr_pll_dither_reg_val(0)
 916                 },
 917         }, {
 918                 400, 400, 200, 25,
 919                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 920                 {
 921                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 922                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
 923                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 924                         _qca95xx_cpu_pll_dither_reg_val(0),
 925                         _qca95xx_ddr_pll_dither_reg_val(0)
 926                 }, {
 927                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 928                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
 929                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 930                         _qca95xx_cpu_pll_dither_reg_val(0),
 931                         _qca95xx_ddr_pll_dither_reg_val(0)
 932                 },
 933         }, {
 934                 400, 400, 300, 25,
 935                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
 936                 {
 937                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
 938                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
 939                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 940                         _qca95xx_cpu_pll_dither_reg_val(0),
 941                         _qca95xx_ddr_pll_dither_reg_val(0)
 942                 }, {
 943                         _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
 944                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
 945                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
 946                         _qca95xx_cpu_pll_dither_reg_val(0),
 947                         _qca95xx_ddr_pll_dither_reg_val(0)
 948                 },
 949         }, {
 950                 500, 200, 100, 12,
 951                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 952                 {
 953                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
 954                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 955                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 956                         _qca95xx_cpu_pll_dither_reg_val(0),
 957                         _qca95xx_ddr_pll_dither_reg_val(0)
 958                 }, {
 959                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
 960                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 961                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
 962                         _qca95xx_cpu_pll_dither_reg_val(0),
 963                         _qca95xx_ddr_pll_dither_reg_val(0)
 964                 },
 965         }, {
 966                 500, 200, 150, 18,
 967                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 968                 {
 969                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
 970                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
 971                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
 972                         _qca95xx_cpu_pll_dither_reg_val(0),
 973                         _qca95xx_ddr_pll_dither_reg_val(0)
 974                 }, {
 975                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
 976                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
 977                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
 978                         _qca95xx_cpu_pll_dither_reg_val(0),
 979                         _qca95xx_ddr_pll_dither_reg_val(0)
 980                 },
 981         }, {
 982                 500, 200, 200, 25,
 983                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
 984                 {
 985                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
 986                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
 987                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 988                         _qca95xx_cpu_pll_dither_reg_val(0),
 989                         _qca95xx_ddr_pll_dither_reg_val(0)
 990                 }, {
 991                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
 992                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
 993                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
 994                         _qca95xx_cpu_pll_dither_reg_val(0),
 995                         _qca95xx_ddr_pll_dither_reg_val(0)
 996                 },
 997         }, {
 998                 500, 300, 100, 12,
 999                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1000                 {
1001                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1002                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1003                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1004                         _qca95xx_cpu_pll_dither_reg_val(0),
1005                         _qca95xx_ddr_pll_dither_reg_val(0)
1006                 }, {
1007                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1008                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1009                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1010                         _qca95xx_cpu_pll_dither_reg_val(0),
1011                         _qca95xx_ddr_pll_dither_reg_val(0)
1012                 },
1013         }, {
1014                 500, 300, 150, 18,
1015                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1016                 {
1017                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1018                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1019                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1020                         _qca95xx_cpu_pll_dither_reg_val(0),
1021                         _qca95xx_ddr_pll_dither_reg_val(0)
1022                 }, {
1023                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1024                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1025                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1026                         _qca95xx_cpu_pll_dither_reg_val(0),
1027                         _qca95xx_ddr_pll_dither_reg_val(0)
1028                 },
1029         }, {
1030                 500, 300, 200, 25,
1031                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1032                 {
1033                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1034                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1035                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1036                         _qca95xx_cpu_pll_dither_reg_val(0),
1037                         _qca95xx_ddr_pll_dither_reg_val(0)
1038                 }, {
1039                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1040                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1041                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1042                         _qca95xx_cpu_pll_dither_reg_val(0),
1043                         _qca95xx_ddr_pll_dither_reg_val(0)
1044                 },
1045         }, {
1046                 500, 300, 250, 25,
1047                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1048                 {
1049                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1050                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1051                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1052                         _qca95xx_cpu_pll_dither_reg_val(0),
1053                         _qca95xx_ddr_pll_dither_reg_val(0)
1054                 }, {
1055                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1056                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1057                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1058                         _qca95xx_cpu_pll_dither_reg_val(0),
1059                         _qca95xx_ddr_pll_dither_reg_val(0)
1060                 },
1061         }, {
1062                 500, 300, 300, 25,
1063                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1064                 {
1065                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1066                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1067                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1068                         _qca95xx_cpu_pll_dither_reg_val(0),
1069                         _qca95xx_ddr_pll_dither_reg_val(0)
1070                 }, {
1071                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1072                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1073                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1074                         _qca95xx_cpu_pll_dither_reg_val(0),
1075                         _qca95xx_ddr_pll_dither_reg_val(0)
1076                 },
1077         }, {
1078                 500, 400, 100, 12,
1079                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1080                 {
1081                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1082                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1083                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1084                         _qca95xx_cpu_pll_dither_reg_val(0),
1085                         _qca95xx_ddr_pll_dither_reg_val(0)
1086                 }, {
1087                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1088                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1089                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1090                         _qca95xx_cpu_pll_dither_reg_val(0),
1091                         _qca95xx_ddr_pll_dither_reg_val(0)
1092                 },
1093         }, {
1094                 500, 400, 200, 25,
1095                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1096                 {
1097                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1098                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1099                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1100                         _qca95xx_cpu_pll_dither_reg_val(0),
1101                         _qca95xx_ddr_pll_dither_reg_val(0)
1102                 }, {
1103                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1104                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1105                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1106                         _qca95xx_cpu_pll_dither_reg_val(0),
1107                         _qca95xx_ddr_pll_dither_reg_val(0)
1108                 },
1109         }, {
1110                 500, 400, 250, 25,
1111                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1112                 {
1113                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1114                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1115                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1116                         _qca95xx_cpu_pll_dither_reg_val(0),
1117                         _qca95xx_ddr_pll_dither_reg_val(0)
1118                 }, {
1119                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1120                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1121                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1122                         _qca95xx_cpu_pll_dither_reg_val(0),
1123                         _qca95xx_ddr_pll_dither_reg_val(0)
1124                 },
1125         }, {
1126                 500, 500, 100, 12,
1127                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1128                 {
1129                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1130                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1131                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
1132                         _qca95xx_cpu_pll_dither_reg_val(0),
1133                         _qca95xx_ddr_pll_dither_reg_val(0)
1134                 }, {
1135                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1136                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1137                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
1138                         _qca95xx_cpu_pll_dither_reg_val(0),
1139                         _qca95xx_ddr_pll_dither_reg_val(0)
1140                 },
1141         }, {
1142                 500, 500, 150, 18,
1143                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1144                 {
1145                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1146                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1147                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
1148                         _qca95xx_cpu_pll_dither_reg_val(0),
1149                         _qca95xx_ddr_pll_dither_reg_val(0)
1150                 }, {
1151                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1152                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1153                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
1154                         _qca95xx_cpu_pll_dither_reg_val(0),
1155                         _qca95xx_ddr_pll_dither_reg_val(0)
1156                 },
1157         }, {
1158                 500, 500, 200, 25,
1159                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1160                 {
1161                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1162                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1163                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1164                         _qca95xx_cpu_pll_dither_reg_val(0),
1165                         _qca95xx_ddr_pll_dither_reg_val(0)
1166                 }, {
1167                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1168                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1169                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1170                         _qca95xx_cpu_pll_dither_reg_val(0),
1171                         _qca95xx_ddr_pll_dither_reg_val(0)
1172                 },
1173         }, {
1174                 500, 500, 250, 25,
1175                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1176                 {
1177                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1178                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1179                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1180                         _qca95xx_cpu_pll_dither_reg_val(0),
1181                         _qca95xx_ddr_pll_dither_reg_val(0)
1182                 }, {
1183                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1184                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1185                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1186                         _qca95xx_cpu_pll_dither_reg_val(0),
1187                         _qca95xx_ddr_pll_dither_reg_val(0)
1188                 },
1189         }, {
1190                 500, 500, 300, 25,
1191                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1192                 {
1193                         _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
1194                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1195                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1196                         _qca95xx_cpu_pll_dither_reg_val(0),
1197                         _qca95xx_ddr_pll_dither_reg_val(0)
1198                 }, {
1199                         _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
1200                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1201                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1202                         _qca95xx_cpu_pll_dither_reg_val(0),
1203                         _qca95xx_ddr_pll_dither_reg_val(0)
1204                 },
1205         }, {
1206                 550, 200, 100, 12,
1207                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1208                 {
1209                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1210                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1211                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
1212                         _qca95xx_cpu_pll_dither_reg_val(0),
1213                         _qca95xx_ddr_pll_dither_reg_val(0)
1214                 }, {
1215                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1216                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1217                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
1218                         _qca95xx_cpu_pll_dither_reg_val(0),
1219                         _qca95xx_ddr_pll_dither_reg_val(0)
1220                 },
1221         }, {
1222                 550, 200, 150, 18,
1223                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1224                 {
1225                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1226                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1227                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
1228                         _qca95xx_cpu_pll_dither_reg_val(0),
1229                         _qca95xx_ddr_pll_dither_reg_val(0)
1230                 }, {
1231                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1232                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1233                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
1234                         _qca95xx_cpu_pll_dither_reg_val(0),
1235                         _qca95xx_ddr_pll_dither_reg_val(0)
1236                 },
1237         }, {
1238                 550, 200, 200, 25,
1239                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1240                 {
1241                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1242                         _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0),
1243                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1244                         _qca95xx_cpu_pll_dither_reg_val(0),
1245                         _qca95xx_ddr_pll_dither_reg_val(0)
1246                 }, {
1247                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1248                         _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0),
1249                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1250                         _qca95xx_cpu_pll_dither_reg_val(0),
1251                         _qca95xx_ddr_pll_dither_reg_val(0)
1252                 },
1253         }, {
1254                 550, 300, 100, 12,
1255                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1256                 {
1257                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1258                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1259                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1260                         _qca95xx_cpu_pll_dither_reg_val(0),
1261                         _qca95xx_ddr_pll_dither_reg_val(0)
1262                 }, {
1263                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1264                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1265                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1266                         _qca95xx_cpu_pll_dither_reg_val(0),
1267                         _qca95xx_ddr_pll_dither_reg_val(0)
1268                 },
1269         }, {
1270                 550, 300, 150, 18,
1271                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1272                 {
1273                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1274                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1275                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1276                         _qca95xx_cpu_pll_dither_reg_val(0),
1277                         _qca95xx_ddr_pll_dither_reg_val(0)
1278                 }, {
1279                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1280                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1281                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1282                         _qca95xx_cpu_pll_dither_reg_val(0),
1283                         _qca95xx_ddr_pll_dither_reg_val(0)
1284                 },
1285         }, {
1286                 550, 300, 200, 25,
1287                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1288                 {
1289                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1290                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1291                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1292                         _qca95xx_cpu_pll_dither_reg_val(0),
1293                         _qca95xx_ddr_pll_dither_reg_val(0)
1294                 }, {
1295                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1296                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1297                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1298                         _qca95xx_cpu_pll_dither_reg_val(0),
1299                         _qca95xx_ddr_pll_dither_reg_val(0)
1300                 },
1301         }, {
1302                 550, 300, 275, 27,
1303                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1304                 {
1305                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1306                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1307                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1308                         _qca95xx_cpu_pll_dither_reg_val(0),
1309                         _qca95xx_ddr_pll_dither_reg_val(0)
1310                 }, {
1311                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1312                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1313                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0),
1314                         _qca95xx_cpu_pll_dither_reg_val(0),
1315                         _qca95xx_ddr_pll_dither_reg_val(0)
1316                 },
1317         }, {
1318                 550, 300, 300, 25,
1319                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1320                 {
1321                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1322                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1323                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1324                         _qca95xx_cpu_pll_dither_reg_val(0),
1325                         _qca95xx_ddr_pll_dither_reg_val(0)
1326                 }, {
1327                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1328                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1329                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1330                         _qca95xx_cpu_pll_dither_reg_val(0),
1331                         _qca95xx_ddr_pll_dither_reg_val(0)
1332                 },
1333         }, {
1334                 550, 375, 250, 25,
1335                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1336                 {
1337                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1338                         _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0),
1339                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1340                         _qca95xx_cpu_pll_dither_reg_val(0),
1341                         _qca95xx_ddr_pll_dither_reg_val(0)
1342                 }, {
1343                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1344                         _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0),
1345                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1346                         _qca95xx_cpu_pll_dither_reg_val(0),
1347                         _qca95xx_ddr_pll_dither_reg_val(0)
1348                 },
1349         }, {
1350                 550, 400, 200, 25,
1351                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1352                 {
1353                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1354                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1355                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1356                         _qca95xx_cpu_pll_dither_reg_val(0),
1357                         _qca95xx_ddr_pll_dither_reg_val(0)
1358                 }, {
1359                         _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
1360                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1361                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1362                         _qca95xx_cpu_pll_dither_reg_val(0),
1363                         _qca95xx_ddr_pll_dither_reg_val(0)
1364                 },
1365         }, {
1366                 560, 450, 225, 28,
1367                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1368                 {
1369                         _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
1370                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1371                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1372                         _qca95xx_cpu_pll_dither_reg_val(26),
1373                         _qca95xx_ddr_pll_dither_reg_val(0)
1374                 }, {
1375                         _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0),
1376                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1377                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1378                         _qca95xx_cpu_pll_dither_reg_val(0),
1379                         _qca95xx_ddr_pll_dither_reg_val(0)
1380                 },
1381         }, {
1382                 600, 200, 100, 12,
1383                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1384                 {
1385                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1386                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1387                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1388                         _qca95xx_cpu_pll_dither_reg_val(0),
1389                         _qca95xx_ddr_pll_dither_reg_val(0)
1390                 }, {
1391                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1392                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1393                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1394                         _qca95xx_cpu_pll_dither_reg_val(0),
1395                         _qca95xx_ddr_pll_dither_reg_val(0)
1396                 },
1397         }, {
1398                 600, 200, 150, 18,
1399                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1400                 {
1401                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1402                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1403                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1404                         _qca95xx_cpu_pll_dither_reg_val(0),
1405                         _qca95xx_ddr_pll_dither_reg_val(0)
1406                 }, {
1407                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1408                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1409                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1410                         _qca95xx_cpu_pll_dither_reg_val(0),
1411                         _qca95xx_ddr_pll_dither_reg_val(0)
1412                 },
1413         }, {
1414                 600, 200, 200, 25,
1415                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1416                 {
1417                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1418                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1419                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1420                         _qca95xx_cpu_pll_dither_reg_val(0),
1421                         _qca95xx_ddr_pll_dither_reg_val(0)
1422                 }, {
1423                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1424                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1425                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1426                         _qca95xx_cpu_pll_dither_reg_val(0),
1427                         _qca95xx_ddr_pll_dither_reg_val(0)
1428                 },
1429         }, {
1430                 600, 300, 100, 12,
1431                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1432                 {
1433                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1434                         _qca95xx_ddr_pll_cfg_reg_val(4,  1, 1, 0, 0),
1435                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1436                         _qca95xx_cpu_pll_dither_reg_val(0),
1437                         _qca95xx_ddr_pll_dither_reg_val(0)
1438                 }, {
1439                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1440                         _qca95xx_ddr_pll_cfg_reg_val(5,  2, 1, 0, 0),
1441                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1442                         _qca95xx_cpu_pll_dither_reg_val(0),
1443                         _qca95xx_ddr_pll_dither_reg_val(0)
1444                 },
1445         }, {
1446                 600, 300, 150, 18,
1447                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1448                 {
1449                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1450                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1451                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1452                         _qca95xx_cpu_pll_dither_reg_val(0),
1453                         _qca95xx_ddr_pll_dither_reg_val(0)
1454                 }, {
1455                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1456                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1457                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1458                         _qca95xx_cpu_pll_dither_reg_val(0),
1459                         _qca95xx_ddr_pll_dither_reg_val(0)
1460                 },
1461         }, {
1462                 600, 300, 200, 25,
1463                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1464                 {
1465                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1466                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1467                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1468                         _qca95xx_cpu_pll_dither_reg_val(0),
1469                         _qca95xx_ddr_pll_dither_reg_val(0)
1470                 }, {
1471                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1472                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1473                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1474                         _qca95xx_cpu_pll_dither_reg_val(0),
1475                         _qca95xx_ddr_pll_dither_reg_val(0)
1476                 },
1477         }, {
1478                 600, 300, 250, 25,
1479                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1480                 {
1481                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1482                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1483                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1484                         _qca95xx_cpu_pll_dither_reg_val(0),
1485                         _qca95xx_ddr_pll_dither_reg_val(0)
1486                 }, {
1487                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1488                         _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
1489                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
1490                         _qca95xx_cpu_pll_dither_reg_val(0),
1491                         _qca95xx_ddr_pll_dither_reg_val(0)
1492                 },
1493         }, {
1494                 600, 300, 300, 25,
1495                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1496                 {
1497                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1498                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1499                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1500                         _qca95xx_cpu_pll_dither_reg_val(0),
1501                         _qca95xx_ddr_pll_dither_reg_val(0)
1502                 }, {
1503                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1504                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1505                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1506                         _qca95xx_cpu_pll_dither_reg_val(0),
1507                         _qca95xx_ddr_pll_dither_reg_val(0)
1508                 },
1509         }, {
1510                 600, 400, 100, 12,
1511                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1512                 {
1513                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1514                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1515                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1516                         _qca95xx_cpu_pll_dither_reg_val(0),
1517                         _qca95xx_ddr_pll_dither_reg_val(0)
1518                 }, {
1519                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1520                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1521                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1522                         _qca95xx_cpu_pll_dither_reg_val(0),
1523                         _qca95xx_ddr_pll_dither_reg_val(0)
1524                 },
1525         }, {
1526                 600, 400, 150, 18,
1527                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1528                 {
1529                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1530                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1531                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1532                         _qca95xx_cpu_pll_dither_reg_val(0),
1533                         _qca95xx_ddr_pll_dither_reg_val(0)
1534                 }, {
1535                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1536                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1537                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1538                         _qca95xx_cpu_pll_dither_reg_val(0),
1539                         _qca95xx_ddr_pll_dither_reg_val(0)
1540                 },
1541         }, {
1542                 600, 400, 200, 25,
1543                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1544                 {
1545                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1546                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1547                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1548                         _qca95xx_cpu_pll_dither_reg_val(0),
1549                         _qca95xx_ddr_pll_dither_reg_val(0)
1550                 }, {
1551                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1552                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1553                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1554                         _qca95xx_cpu_pll_dither_reg_val(0),
1555                         _qca95xx_ddr_pll_dither_reg_val(0)
1556                 },
1557         }, {
1558                 600, 400, 300, 25,
1559                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1560                 {
1561                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1562                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
1563                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1564                         _qca95xx_cpu_pll_dither_reg_val(0),
1565                         _qca95xx_ddr_pll_dither_reg_val(0)
1566                 }, {
1567                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1568                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1569                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1570                         _qca95xx_cpu_pll_dither_reg_val(0),
1571                         _qca95xx_ddr_pll_dither_reg_val(0)
1572                 },
1573         }, {
1574                 600, 450, 100, 12,
1575                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1576                 {
1577                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1578                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1579                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
1580                         _qca95xx_cpu_pll_dither_reg_val(0),
1581                         _qca95xx_ddr_pll_dither_reg_val(0)
1582                 }, {
1583                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1584                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1585                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
1586                         _qca95xx_cpu_pll_dither_reg_val(0),
1587                         _qca95xx_ddr_pll_dither_reg_val(0)
1588                 },
1589         }, {
1590                 600, 450, 150, 18,
1591                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1592                 {
1593                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1594                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1595                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1596                         _qca95xx_cpu_pll_dither_reg_val(0),
1597                         _qca95xx_ddr_pll_dither_reg_val(0)
1598                 }, {
1599                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1600                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1601                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1602                         _qca95xx_cpu_pll_dither_reg_val(0),
1603                         _qca95xx_ddr_pll_dither_reg_val(0)
1604                 },
1605         }, {
1606                 600, 450, 200, 25,
1607                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1608                 {
1609                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1610                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1611                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1612                         _qca95xx_cpu_pll_dither_reg_val(0),
1613                         _qca95xx_ddr_pll_dither_reg_val(0)
1614                 }, {
1615                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1616                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1617                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1618                         _qca95xx_cpu_pll_dither_reg_val(0),
1619                         _qca95xx_ddr_pll_dither_reg_val(0)
1620                 },
1621         }, {
1622                 600, 450, 225, 28,
1623                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1624                 {
1625                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1626                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1627                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1628                         _qca95xx_cpu_pll_dither_reg_val(0),
1629                         _qca95xx_ddr_pll_dither_reg_val(0)
1630                 }, {
1631                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1632                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1633                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1634                         _qca95xx_cpu_pll_dither_reg_val(0),
1635                         _qca95xx_ddr_pll_dither_reg_val(0)
1636                 },
1637         }, {
1638                 600, 450, 300, 25,
1639                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1640                 {
1641                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1642                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
1643                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1644                         _qca95xx_cpu_pll_dither_reg_val(0),
1645                         _qca95xx_ddr_pll_dither_reg_val(0)
1646                 }, {
1647                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1648                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
1649                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1650                         _qca95xx_cpu_pll_dither_reg_val(0),
1651                         _qca95xx_ddr_pll_dither_reg_val(0)
1652                 },
1653         }, {
1654                 600, 500, 100, 12,
1655                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1656                 {
1657                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1658                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1659                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
1660                         _qca95xx_cpu_pll_dither_reg_val(0),
1661                         _qca95xx_ddr_pll_dither_reg_val(0)
1662                 }, {
1663                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1664                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1665                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
1666                         _qca95xx_cpu_pll_dither_reg_val(0),
1667                         _qca95xx_ddr_pll_dither_reg_val(0)
1668                 },
1669         }, {
1670                 600, 500, 150, 18,
1671                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1672                 {
1673                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1674                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1675                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1676                         _qca95xx_cpu_pll_dither_reg_val(0),
1677                         _qca95xx_ddr_pll_dither_reg_val(0)
1678                 }, {
1679                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1680                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1681                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1682                         _qca95xx_cpu_pll_dither_reg_val(0),
1683                         _qca95xx_ddr_pll_dither_reg_val(0)
1684                 },
1685         }, {
1686                 600, 500, 200, 25,
1687                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1688                 {
1689                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1690                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1691                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1692                         _qca95xx_cpu_pll_dither_reg_val(0),
1693                         _qca95xx_ddr_pll_dither_reg_val(0)
1694                 }, {
1695                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1696                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1697                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1698                         _qca95xx_cpu_pll_dither_reg_val(0),
1699                         _qca95xx_ddr_pll_dither_reg_val(0)
1700                 },
1701         }, {
1702                 600, 500, 250, 25,
1703                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1704                 {
1705                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1706                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1707                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1708                         _qca95xx_cpu_pll_dither_reg_val(0),
1709                         _qca95xx_ddr_pll_dither_reg_val(0)
1710                 }, {
1711                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1712                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1713                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1714                         _qca95xx_cpu_pll_dither_reg_val(0),
1715                         _qca95xx_ddr_pll_dither_reg_val(0)
1716                 },
1717         }, {
1718                 600, 500, 300, 25,
1719                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1720                 {
1721                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1722                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
1723                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1724                         _qca95xx_cpu_pll_dither_reg_val(0),
1725                         _qca95xx_ddr_pll_dither_reg_val(0)
1726                 }, {
1727                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1728                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
1729                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1730                         _qca95xx_cpu_pll_dither_reg_val(0),
1731                         _qca95xx_ddr_pll_dither_reg_val(0)
1732                 },
1733         }, {
1734                 600, 550, 100, 12,
1735                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1736                 {
1737                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1738                         _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
1739                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
1740                         _qca95xx_cpu_pll_dither_reg_val(0),
1741                         _qca95xx_ddr_pll_dither_reg_val(0)
1742                 }, {
1743                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1744                         _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
1745                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
1746                         _qca95xx_cpu_pll_dither_reg_val(0),
1747                         _qca95xx_ddr_pll_dither_reg_val(0)
1748                 },
1749         }, {
1750                 600, 550, 150, 18,
1751                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1752                 {
1753                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1754                         _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
1755                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1756                         _qca95xx_cpu_pll_dither_reg_val(0),
1757                         _qca95xx_ddr_pll_dither_reg_val(0)
1758                 }, {
1759                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1760                         _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
1761                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
1762                         _qca95xx_cpu_pll_dither_reg_val(0),
1763                         _qca95xx_ddr_pll_dither_reg_val(0)
1764                 },
1765         }, {
1766                 600, 550, 200, 25,
1767                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1768                 {
1769                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1770                         _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
1771                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1772                         _qca95xx_cpu_pll_dither_reg_val(0),
1773                         _qca95xx_ddr_pll_dither_reg_val(0)
1774                 }, {
1775                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1776                         _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
1777                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
1778                         _qca95xx_cpu_pll_dither_reg_val(0),
1779                         _qca95xx_ddr_pll_dither_reg_val(0)
1780                 },
1781         }, {
1782                 600, 550, 275, 27,
1783                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1784                 {
1785                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1786                         _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
1787                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1788                         _qca95xx_cpu_pll_dither_reg_val(0),
1789                         _qca95xx_ddr_pll_dither_reg_val(0)
1790                 }, {
1791                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1792                         _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
1793                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1794                         _qca95xx_cpu_pll_dither_reg_val(0),
1795                         _qca95xx_ddr_pll_dither_reg_val(0)
1796                 },
1797         }, {
1798                 600, 550, 300, 25,
1799                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1800                 {
1801                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1802                         _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
1803                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1804                         _qca95xx_cpu_pll_dither_reg_val(0),
1805                         _qca95xx_ddr_pll_dither_reg_val(0)
1806                 }, {
1807                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1808                         _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
1809                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
1810                         _qca95xx_cpu_pll_dither_reg_val(0),
1811                         _qca95xx_ddr_pll_dither_reg_val(0)
1812                 },
1813         }, {
1814                 600, 600, 100, 12,
1815                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1816                 {
1817                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1818                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1819                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1),
1820                         _qca95xx_cpu_pll_dither_reg_val(0),
1821                         _qca95xx_ddr_pll_dither_reg_val(0)
1822                 }, {
1823                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1824                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1825                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1),
1826                         _qca95xx_cpu_pll_dither_reg_val(0),
1827                         _qca95xx_ddr_pll_dither_reg_val(0)
1828                 },
1829         }, {
1830                 600, 600, 150, 18,
1831                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1832                 {
1833                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1834                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1835                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1836                         _qca95xx_cpu_pll_dither_reg_val(0),
1837                         _qca95xx_ddr_pll_dither_reg_val(0)
1838                 }, {
1839                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1840                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1841                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
1842                         _qca95xx_cpu_pll_dither_reg_val(0),
1843                         _qca95xx_ddr_pll_dither_reg_val(0)
1844                 },
1845         }, {
1846                 600, 600, 200, 25,
1847                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1848                 {
1849                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1850                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1851                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1852                         _qca95xx_cpu_pll_dither_reg_val(0),
1853                         _qca95xx_ddr_pll_dither_reg_val(0)
1854                 }, {
1855                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1856                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1857                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1858                         _qca95xx_cpu_pll_dither_reg_val(0),
1859                         _qca95xx_ddr_pll_dither_reg_val(0)
1860                 },
1861         }, {
1862                 600, 600, 250, 25,
1863                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
1864                 {
1865                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1866                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
1867                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1868                         _qca95xx_cpu_pll_dither_reg_val(0),
1869                         _qca95xx_ddr_pll_dither_reg_val(0)
1870                 }, {
1871                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1872                         _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
1873                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
1874                         _qca95xx_cpu_pll_dither_reg_val(0),
1875                         _qca95xx_ddr_pll_dither_reg_val(0)
1876                 },
1877         }, {
1878                 600, 600, 300, 25,
1879                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1880                 {
1881                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1882                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1883                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1884                         _qca95xx_cpu_pll_dither_reg_val(0),
1885                         _qca95xx_ddr_pll_dither_reg_val(0)
1886                 }, {
1887                         _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
1888                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1889                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1890                         _qca95xx_cpu_pll_dither_reg_val(0),
1891                         _qca95xx_ddr_pll_dither_reg_val(0)
1892                 },
1893         }, {
1894                 620, 200, 100, 12,
1895                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1896                 {
1897                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1898                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1899                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1900                         _qca95xx_cpu_pll_dither_reg_val(52),
1901                         _qca95xx_ddr_pll_dither_reg_val(0)
1902                 }, {
1903                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1904                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1905                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1906                         _qca95xx_cpu_pll_dither_reg_val(0),
1907                         _qca95xx_ddr_pll_dither_reg_val(0)
1908                 },
1909         }, {
1910                 620, 200, 150, 18,
1911                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1912                 {
1913                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1914                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1915                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
1916                         _qca95xx_cpu_pll_dither_reg_val(52),
1917                         _qca95xx_ddr_pll_dither_reg_val(0)
1918                 }, {
1919                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1920                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1921                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
1922                         _qca95xx_cpu_pll_dither_reg_val(0),
1923                         _qca95xx_ddr_pll_dither_reg_val(0)
1924                 },
1925         }, {
1926                 620, 200, 200, 25,
1927                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1928                 {
1929                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1930                         _qca95xx_ddr_pll_cfg_reg_val(8,  1, 1, 0, 0),
1931                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1932                         _qca95xx_cpu_pll_dither_reg_val(52),
1933                         _qca95xx_ddr_pll_dither_reg_val(0)
1934                 }, {
1935                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1936                         _qca95xx_ddr_pll_cfg_reg_val(5,  1, 1, 0, 0),
1937                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1938                         _qca95xx_cpu_pll_dither_reg_val(0),
1939                         _qca95xx_ddr_pll_dither_reg_val(0)
1940                 },
1941         }, {
1942                 620, 300, 100, 12,
1943                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1944                 {
1945                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1946                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1947                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1948                         _qca95xx_cpu_pll_dither_reg_val(52),
1949                         _qca95xx_ddr_pll_dither_reg_val(0)
1950                 }, {
1951                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1952                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1953                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
1954                         _qca95xx_cpu_pll_dither_reg_val(0),
1955                         _qca95xx_ddr_pll_dither_reg_val(0)
1956                 },
1957         }, {
1958                 620, 300, 150, 18,
1959                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1960                 {
1961                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1962                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1963                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1964                         _qca95xx_cpu_pll_dither_reg_val(52),
1965                         _qca95xx_ddr_pll_dither_reg_val(0)
1966                 }, {
1967                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1968                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
1969                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
1970                         _qca95xx_cpu_pll_dither_reg_val(0),
1971                         _qca95xx_ddr_pll_dither_reg_val(0)
1972                 },
1973         }, {
1974                 620, 300, 200, 25,
1975                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
1976                 {
1977                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1978                         _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
1979                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1980                         _qca95xx_cpu_pll_dither_reg_val(52),
1981                         _qca95xx_ddr_pll_dither_reg_val(0)
1982                 }, {
1983                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
1984                         _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
1985                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
1986                         _qca95xx_cpu_pll_dither_reg_val(0),
1987                         _qca95xx_ddr_pll_dither_reg_val(0)
1988                 },
1989         }, {
1990                 620, 300, 300, 25,
1991                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
1992                 {
1993                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
1994                         _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
1995                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
1996                         _qca95xx_cpu_pll_dither_reg_val(52),
1997                         _qca95xx_ddr_pll_dither_reg_val(0)
1998                 }, {
1999                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2000                         _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
2001                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
2002                         _qca95xx_cpu_pll_dither_reg_val(0),
2003                         _qca95xx_ddr_pll_dither_reg_val(0)
2004                 },
2005         }, {
2006                 620, 400, 100, 12,
2007                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2008                 {
2009                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2010                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2011                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
2012                         _qca95xx_cpu_pll_dither_reg_val(52),
2013                         _qca95xx_ddr_pll_dither_reg_val(0)
2014                 }, {
2015                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2016                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
2017                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
2018                         _qca95xx_cpu_pll_dither_reg_val(0),
2019                         _qca95xx_ddr_pll_dither_reg_val(0)
2020                 },
2021         }, {
2022                 620, 400, 155, 19,
2023                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2024                 {
2025                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2026                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2027                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
2028                         _qca95xx_cpu_pll_dither_reg_val(52),
2029                         _qca95xx_ddr_pll_dither_reg_val(0)
2030                 }, {
2031                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2032                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
2033                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
2034                         _qca95xx_cpu_pll_dither_reg_val(0),
2035                         _qca95xx_ddr_pll_dither_reg_val(0)
2036                 },
2037         }, {
2038                 620, 400, 200, 25,
2039                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2040                 {
2041                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2042                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2043                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2044                         _qca95xx_cpu_pll_dither_reg_val(52),
2045                         _qca95xx_ddr_pll_dither_reg_val(0)
2046                 }, {
2047                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2048                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
2049                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2050                         _qca95xx_cpu_pll_dither_reg_val(0),
2051                         _qca95xx_ddr_pll_dither_reg_val(0)
2052                 },
2053         }, {
2054                 620, 400, 310, 25,
2055                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
2056                 {
2057                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2058                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2059                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
2060                         _qca95xx_cpu_pll_dither_reg_val(52),
2061                         _qca95xx_ddr_pll_dither_reg_val(0)
2062                 }, {
2063                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2064                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
2065                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
2066                         _qca95xx_cpu_pll_dither_reg_val(0),
2067                         _qca95xx_ddr_pll_dither_reg_val(0)
2068                 },
2069         }, {
2070                 620, 500, 100, 12,
2071                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2072                 {
2073                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2074                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2075                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
2076                         _qca95xx_cpu_pll_dither_reg_val(52),
2077                         _qca95xx_ddr_pll_dither_reg_val(0)
2078                 }, {
2079                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2080                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2081                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
2082                         _qca95xx_cpu_pll_dither_reg_val(0),
2083                         _qca95xx_ddr_pll_dither_reg_val(0)
2084                 },
2085         }, {
2086                 620, 500, 155, 19,
2087                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2088                 {
2089                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2090                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2091                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
2092                         _qca95xx_cpu_pll_dither_reg_val(52),
2093                         _qca95xx_ddr_pll_dither_reg_val(0)
2094                 }, {
2095                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2096                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2097                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
2098                         _qca95xx_cpu_pll_dither_reg_val(0),
2099                         _qca95xx_ddr_pll_dither_reg_val(0)
2100                 },
2101         }, {
2102                 620, 500, 166, 20,
2103                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2104                 {
2105                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2106                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2107                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
2108                         _qca95xx_cpu_pll_dither_reg_val(52),
2109                         _qca95xx_ddr_pll_dither_reg_val(0)
2110                 }, {
2111                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2112                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2113                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
2114                         _qca95xx_cpu_pll_dither_reg_val(0),
2115                         _qca95xx_ddr_pll_dither_reg_val(0)
2116                 },
2117         }, {
2118                 620, 500, 206, 25,
2119                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2120                 {
2121                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2122                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2123                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
2124                         _qca95xx_cpu_pll_dither_reg_val(52),
2125                         _qca95xx_ddr_pll_dither_reg_val(0)
2126                 }, {
2127                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2128                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2129                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
2130                         _qca95xx_cpu_pll_dither_reg_val(0),
2131                         _qca95xx_ddr_pll_dither_reg_val(0)
2132                 },
2133         }, {
2134                 620, 500, 250, 25,
2135                 _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
2136                 {
2137                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2138                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2139                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2140                         _qca95xx_cpu_pll_dither_reg_val(52),
2141                         _qca95xx_ddr_pll_dither_reg_val(0)
2142                 }, {
2143                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2144                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2145                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2146                         _qca95xx_cpu_pll_dither_reg_val(0),
2147                         _qca95xx_ddr_pll_dither_reg_val(0)
2148                 },
2149         }, {
2150                 620, 500, 310, 25,
2151                 _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
2152                 {
2153                         _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
2154                         _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
2155                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
2156                         _qca95xx_cpu_pll_dither_reg_val(52),
2157                         _qca95xx_ddr_pll_dither_reg_val(0)
2158                 }, {
2159                         _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
2160                         _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
2161                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
2162                         _qca95xx_cpu_pll_dither_reg_val(0),
2163                         _qca95xx_ddr_pll_dither_reg_val(0)
2164                 },
2165         }, {
2166                 650, 400, 200, 25,
2167                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2168                 {
2169                         _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
2170                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2171                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2172                         _qca95xx_cpu_pll_dither_reg_val(0),
2173                         _qca95xx_ddr_pll_dither_reg_val(0)
2174                 }, {
2175                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
2176                         _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
2177                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2178                         _qca95xx_cpu_pll_dither_reg_val(16),
2179                         _qca95xx_ddr_pll_dither_reg_val(0)
2180                 },
2181         }, {
2182                 650, 420, 210, 26,
2183                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2184                 {
2185                         _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
2186                         _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
2187                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2188                         _qca95xx_cpu_pll_dither_reg_val(0),
2189                         _qca95xx_ddr_pll_dither_reg_val(820)
2190                 }, {
2191                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
2192                         _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0),
2193                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2194                         _qca95xx_cpu_pll_dither_reg_val(16),
2195                         _qca95xx_ddr_pll_dither_reg_val(0)
2196                 },
2197         }, {
2198                 650, 450, 225, 28,
2199                 _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
2200                 {
2201                         _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
2202                         _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
2203                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2204                         _qca95xx_cpu_pll_dither_reg_val(0),
2205                         _qca95xx_ddr_pll_dither_reg_val(0)
2206                 }, {
2207                         _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
2208                         _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
2209                         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
2210                         _qca95xx_cpu_pll_dither_reg_val(16),
2211                         _qca95xx_ddr_pll_dither_reg_val(0)
2212                 },
2213         },
2214         #endif /* SOC_TYPE & QCA_AR933X_SOC */
2215 };
2216
2217 /* Number of all profiles */
2218 static u32 clk_profiles_cnt = sizeof(clk_profiles) / sizeof(clk_profile);
2219
2220 #endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */
2221
2222 #endif /* _CMD_QCACLK_H_ */