2 * vim: tabstop=8 : noexpandtab
6 * Copyright (c) 2013 Qualcomm Atheros, Inc.
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
25 * Set everything to zero. The corresponding header will
26 * undef and re-define the appropriate ones
28 #define is_ar7100() (0)
31 #define is_ar7240() (0)
32 #define is_ar7241() (0)
33 #define is_ar7242() (0)
35 #define is_ar9330() (0)
36 #define is_ar933x() (0)
37 #define is_hornet() (0)
39 #define is_ar934x() (0)
42 #define is_qca955x() (0)
45 #define is_qca953x() (0)
48 #define is_qca956x() (0)
50 #define ATH_CONSOLE_BAUD 115200
52 #define AR7240_REV_1_2 0xc2
54 #ifdef CONFIG_ATH_EMULATION
70 #ifdef CONFIG_ATHRS16_PHY
76 #ifdef CONFIG_ATHRS17_PHY
82 #ifdef CONFIG_ATHR_8033_PHY
89 #define is_vir_phy() 1
91 #define is_vir_phy() 0
94 #ifdef CFG_ATHRS27_PHY
100 #define ath_arch_init_irq() /* nothing */
104 int ath_uart_freq(void);
106 typedef unsigned int ath_reg_t;
108 #ifdef COMPRESSED_UBOOT
111 # define prmsg printf
114 #endif /* __ASSEMBLY__ */
116 #define ath_reg_rd(_phys) (*(volatile ath_reg_t *)KSEG1ADDR(_phys))
118 #define ath_reg_wr_nf(_phys, _val) \
119 ((*(volatile ath_reg_t *)KSEG1ADDR(_phys)) = (_val))
121 #define ath_reg_wr(_phys, _val) do { \
122 ath_reg_wr_nf(_phys, _val); \
126 #define ath_reg_rmw_set(_reg, _mask) do { \
127 ath_reg_wr((_reg), (ath_reg_rd((_reg)) | (_mask))); \
128 ath_reg_rd((_reg)); \
131 #define ath_reg_rmw_clear(_reg, _mask) do { \
132 ath_reg_wr((_reg), (ath_reg_rd((_reg)) & ~(_mask))); \
133 ath_reg_rd((_reg)); \
136 #define ath_uart_rd(y) ath_reg_rd((ATH_UART_BASE+y))
137 #define ath_uart_wr(x, z) ath_reg_wr((ATH_UART_BASE+x), z)
141 #define OFS_RCV_BUFFER (0 * REG_OFFSET)
142 #define OFS_TRANS_HOLD (0 * REG_OFFSET)
143 #define OFS_SEND_BUFFER (0 * REG_OFFSET)
144 #define OFS_INTR_ENABLE (1 * REG_OFFSET)
145 #define OFS_INTR_ID (2 * REG_OFFSET)
146 #define OFS_DATA_FORMAT (3 * REG_OFFSET)
147 #define OFS_LINE_CONTROL (3 * REG_OFFSET)
148 #define OFS_MODEM_CONTROL (4 * REG_OFFSET)
149 #define OFS_RS232_OUTPUT (4 * REG_OFFSET)
150 #define OFS_LINE_STATUS (5 * REG_OFFSET)
151 #define OFS_MODEM_STATUS (6 * REG_OFFSET)
152 #define OFS_RS232_INPUT (6 * REG_OFFSET)
153 #define OFS_SCRATCH_PAD (7 * REG_OFFSET)
155 #define OFS_DIVISOR_LSB (0 * REG_OFFSET)
156 #define OFS_DIVISOR_MSB (1 * REG_OFFSET)
159 * PLL Config for different CPU/DDR/AHB frequencies
161 #define CFG_PLL_720_600_200 0x01
162 #define CFG_PLL_720_680_240 0x02
163 #define CFG_PLL_720_600_240 0x03
164 #define CFG_PLL_680_680_226 0x04
165 #define CFG_PLL_720_600_300 0x05
166 #define CFG_PLL_400_400_200 0x06
167 #define CFG_PLL_560_450_220 0x07
168 #define CFG_PLL_550_400_200 0x08
169 #define CFG_PLL_550_600_200 0x09
170 #define CFG_PLL_600_600_200 0x0a
171 #define CFG_PLL_750_400_250 0x0b
172 #define CFG_PLL_800_400_266 0x0c
173 #define CFG_PLL_750_667_250 0x0d
174 #define CFG_PLL_800_600_266 0x0e
175 #define CFG_PLL_800_667_266 0x0f
176 #define CFG_PLL_810_700_270 0x10
177 #define CFG_PLL_810_666_270 0x11
178 #define CFG_PLL_775_650_258 0x12
179 #define CFG_PLL_650_400_200 0x13
180 #define CFG_PLL_650_600_200 0x14
182 #define UBOOT_SIZE (256 * 1024)
183 #define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE)
184 #define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20)
185 #define PLL_MAGIC 0xaabbccdd
186 #define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12)
187 #define SRIF_PLL_MAGIC 0x73726966 /* srif */
191 #if defined(CONFIG_MACH_AR724x)
193 #elif defined(CONFIG_MACH_AR933x)
195 #elif defined(CONFIG_MACH_AR934x)
197 #elif defined(CONFIG_MACH_QCA955x)
199 #elif defined(CONFIG_MACH_QCA953x)
201 #elif defined(CONFIG_MACH_QCA956x)
204 # error "Building U-Boot for unknown device"
209 #define ATH_MEM_SDRAM 1
210 #define ATH_MEM_DDR1 2
211 #define ATH_MEM_DDR2 3
213 * GPIO Access & Control
215 void ath_gpio_init(void);
216 void ath_gpio_down(void);
217 void ath_gpio_up(void);
219 void ath_gpio_irq_init(int);
221 * GPIO Helper Functions
223 void ath_gpio_enable_slic(void);
225 /* enable UART block, takes away GPIO 10 and 9 */
226 void ath_gpio_enable_uart(void);
228 /* enable STEREO block, takes away GPIO 11,8,7, and 6 */
229 void ath_gpio_enable_stereo(void);
231 /* allow CS0/CS1 to be controlled via SPI register, takes away GPIO0/GPIO1 */
232 void ath_gpio_enable_spi_cs1_cs0(void);
234 /* allow GPIO0/GPIO1 to be used as SCL/SDA for software based i2c */
235 void ath_gpio_enable_i2c_on_gpio_0_1(void);
238 * GPIO General Functions
240 void ath_gpio_drive_low(unsigned int mask);
241 void ath_gpio_drive_high(unsigned int mask);
243 unsigned int ath_gpio_float_high_test(unsigned int mask);
245 /* Functions to access SPI through software. Example:
247 * ath_spi_down(); ---------------------- disable others from accessing SPI bus taking semaphore
248 * ath_spi_enable_soft_access(); -------- disable HW control of SPI
250 * <board specific chip select routine>
252 * <read/write SPI using using custom routine or general purposeflash routines
253 * Custom routine may use:
255 * ath_spi_raw_output_u8(unsigned char)
256 * ath_spi_raw_output_u32(unsigned int)
257 * ath_spi_raw_input_u32()
259 * General purpose flash routines:
260 * ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
261 * ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
262 * ath_spi_flash_sector_erase(unsigned int addr);
265 * <board specific chip deselect routine>
267 * ath_spi_disable_soft_acess(); ------- enable HW control of SPI bus
268 * ath_spi_up(); ----------------------- enable others to access SPI bus releasing semaphore
270 void ath_spi_init(void);
271 void ath_spi_down(void);
272 void ath_spi_up(void);
275 ath_spi_enable_soft_access(void)
277 ath_reg_wr_nf(ATH_SPI_FS, 1);
281 ath_spi_disable_soft_access(void)
283 ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_DIS);
284 ath_reg_wr_nf(ATH_SPI_FS, 0);
287 void ath_spi_raw_output_u8(unsigned char val);
288 void ath_spi_raw_output_u32(unsigned int val);
289 unsigned int ath_spi_raw_input_u8(void);
290 unsigned int ath_spi_raw_input_u32(void);
292 void ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
293 void ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
294 void ath_spi_flash_sector_erase(unsigned int addr);
297 * Allow access to cs0-2 when GPIO Function enables cs0-2 through SPI register.
300 ath_spi_enable_cs0(void)
304 ath_spi_enable_soft_access();
305 cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
306 ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_0 | cs);
310 ath_spi_enable_cs1(void)
313 #if defined(CONFIG_MACH_AR934x) || \
314 defined(CONFIG_MACH_QCA955x)
317 ath_spi_enable_soft_access();
318 cs = ath_reg_rd(ATH_SPI_WRITE) & ATH_SPI_CS_DIS;
319 ath_reg_wr_nf(ATH_SPI_WRITE, cs | ATH_SPI_CLK_HIGH);
320 cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
321 ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs | ATH_SPI_CLK_HIGH);
322 ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
325 ath_spi_enable_soft_access();
326 cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
327 ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
332 ath_spi_disable_cs(void)
334 unsigned int cs = ath_reg_rd(ATH_SPI_WRITE) | ATH_SPI_CS_DIS;
335 ath_reg_wr_nf(ATH_SPI_WRITE, cs);
336 ath_spi_disable_soft_access();
341 * Example usage to access BOOT flash
344 ath_spi_flash_cs0_sector_erase(unsigned int addr)
346 ath_spi_enable_cs0();
347 ath_spi_flash_sector_erase(addr);
348 ath_spi_disable_cs();
352 ath_spi_flash_cs0_write_page(unsigned int addr, unsigned char *data, int len)
354 ath_spi_enable_cs0();
355 ath_spi_flash_write_page(addr, data, len);
356 ath_spi_disable_cs();
359 #endif /* __ASSEMBLY__ */
362 #endif /* _ATHEROS_H */