2 * Atheros AR933x SOC registers definitions
4 * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2008-2010 Atheros Communications Inc.
7 * SPDX-License-Identifier:GPL-2.0
16 #define _BIT(_x) (1 << (_x))
17 #define _BITS(_start, _bits) (((1UL << (_bits)) - 1) << _start)
22 #define DDR_BASE_REG 0x00000000
23 #define APB_BASE_REG 0x18000000
24 #define ETH0_AHB_BASE_REG 0x19000000
25 #define ETH1_AHB_BASE_REG 0x1A000000
26 #define USB_AHB_BASE_REG 0x1B000000
27 #define FLASH_BASE_REG 0x1F000000
32 #define DDR_CTRL_BASE_REG APB_BASE_REG + 0x00000000
33 #define UART_BASE_REG APB_BASE_REG + 0x00020000
34 #define USB_CONFIG_BASE_REG APB_BASE_REG + 0x00030000
35 #define GPIO_BASE_REG APB_BASE_REG + 0x00040000
36 #define PLL_BASE_REG APB_BASE_REG + 0x00050000
37 #define RESET_BASE_REG APB_BASE_REG + 0x00060000
38 #define GMAC_BASE_REG APB_BASE_REG + 0x00070000
39 #define SLIC_BASE_REG APB_BASE_REG + 0x00090000
40 #define RTC_BASE_REG APB_BASE_REG + 0x00107000
45 #define DDR_CONFIG_REG DDR_CTRL_BASE_REG + 0x00
46 #define DDR_CONFIG2_REG DDR_CTRL_BASE_REG + 0x04
47 #define DDR_MODE_REG DDR_CTRL_BASE_REG + 0x08
48 #define DDR_EXTENDED_MODE_REG DDR_CTRL_BASE_REG + 0x0C
49 #define DDR_CONTROL_REG DDR_CTRL_BASE_REG + 0x10
50 #define DDR_REFRESH_REG DDR_CTRL_BASE_REG + 0x14
51 #define DDR_RD_DATA_THIS_CYCLE_REG DDR_CTRL_BASE_REG + 0x18
52 #define DDR_TAP_CONTROL_0_REG DDR_CTRL_BASE_REG + 0x1C
53 #define DDR_TAP_CONTROL_1_REG DDR_CTRL_BASE_REG + 0x20
54 #define DDR_WB_FLUSH_GE0_REG DDR_CTRL_BASE_REG + 0x7C
55 #define DDR_WB_FLUSH_GE1_REG DDR_CTRL_BASE_REG + 0x80
56 #define DDR_WB_FLUSH_USB_REG DDR_CTRL_BASE_REG + 0x84
57 #define DDR_DDR2_CONFIG_REG DDR_CTRL_BASE_REG + 0x8C
58 #define DDR_EMR2_REG DDR_CTRL_BASE_REG + 0x90
59 #define DDR_EMR3_REG DDR_CTRL_BASE_REG + 0x94
60 #define DDR_BURST_REG DDR_CTRL_BASE_REG + 0x98
65 #define AHB_MASTER_TOUT_MAX_REG APB_BASE_REG + 0x9C
66 #define AHB_MASTER_TOUT_CURRENT_REG APB_BASE_REG + 0xA0
67 #define AHB_MASTER_TOUT_SLV_ADDR_REG APB_BASE_REG + 0xA4
72 #define UART_DATA_REG UART_BASE_REG + 0x00
73 #define UART_CS_REG UART_BASE_REG + 0x04
74 #define UART_CLOCK_REG UART_BASE_REG + 0x08
75 #define UART_INT_REG UART_BASE_REG + 0x0C
76 #define UART_INT_EN_REG UART_BASE_REG + 0x10
79 * UART registers _BIT fields
81 #define UART_CS_PAR_MODE_SHIFT 0
82 #define UART_CS_PAR_MODE_MASK _BITS(UART_CS_PAR_MODE_SHIFT, 2)
83 #define UART_CS_PAR_MODE_NO_VAL 0x0
84 #define UART_CS_PAR_MODE_ODD_VAL 0x2
85 #define UART_CS_PAR_MODE_OVEN_VAL 0x3
87 #define UART_CS_IFACE_MODE_SHIFT 2
88 #define UART_CS_IFACE_MODE_MASK _BITS(UART_CS_IFACE_MODE_SHIFT, 2)
89 #define UART_CS_IFACE_MODE_DISABLE_VAL 0x0
90 #define UART_CS_IFACE_MODE_DTE_VAL 0x1
91 #define UART_CS_IFACE_MODE_DCE_VAL 0x2
93 #define UART_CS_FLOW_MODE_SHIFT 4
94 #define UART_CS_FLOW_MODE_MASK _BITS(UART_CS_FLOW_MODE_SHIFT, 2)
95 #define UART_CS_FLOW_MODE_NO_VAL 0x0
96 #define UART_CS_FLOW_MODE_HW_VAL 0x2
97 #define UART_CS_FLOW_MODE_INV_VAL 0x3
99 #define UART_CS_DMA_EN_SHIFT 6
100 #define UART_CS_DMA_EN_MASK (1 << UART_CS_DMA_EN_SHIFT)
101 #define UART_CS_RX_READY_ORIDE_SHIFT 7
102 #define UART_CS_RX_READY_ORIDE_MASK (1 << UART_CS_RX_READY_ORIDE_SHIFT)
103 #define UART_CS_TX_READY_ORIDE_SHIFT 8
104 #define UART_CS_TX_READY_ORIDE_MASK (1 << UART_CS_TX_READY_ORIDE_SHIFT)
105 #define UART_CS_TX_READY_SHIFT 9
106 #define UART_CS_TX_READY_MASK (1 << UART_CS_TX_READY_SHIFT)
107 #define UART_CS_RX_BREAK_SHIFT 10
108 #define UART_CS_RX_BREAK_MASK (1 << UART_CS_RX_BREAK_SHIFT)
109 #define UART_CS_TX_BREAK_SHIFT 11
110 #define UART_CS_TX_BREAK_MASK (1 << UART_CS_TX_BREAK_SHIFT)
111 #define UART_CS_HOST_INT_SHIFT 12
112 #define UART_CS_HOST_INT_MASK (1 << UART_CS_HOST_INT_SHIFT)
113 #define UART_CS_HOST_INT_EN_SHIFT 13
114 #define UART_CS_HOST_INT_EN_MASK (1 << UART_CS_HOST_INT_EN_SHIFT)
115 #define UART_CS_TX_BUSY_SHIFT 14
116 #define UART_CS_TX_BUSY_MASK (1 << UART_CS_TX_BUSY_SHIFT)
117 #define UART_CS_RX_BUSY_SHIFT 15
118 #define UART_CS_RX_BUSY_MASK (1 << UART_CS_RX_BUSY_SHIFT)
120 #define UART_RX_CSR_SHIFT 8
121 #define UART_RX_CSR_MASK (1 << UART_RX_CSR_SHIFT)
122 #define UART_TX_CSR_SHIFT 9
123 #define UART_TX_CSR_MASK (1 << UART_TX_CSR_SHIFT)
124 #define UART_TX_RX_DATA_SHIFT 0
125 #define UART_TX_RX_DATA_MASK _BITS(UART_TX_RX_DATA_SHIFT, 8)
126 #define UART_CLOCK_SCALE_SHIFT 16
127 #define UART_CLOCK_SCALE_MASK _BITS(UART_CLOCK_SCALE_SHIFT, 8)
128 #define UART_CLOCK_STEP_SHIFT 0
129 #define UART_CLOCK_STEP_MASK _BITS(UART_CLOCK_STEP_SHIFT, 16)
131 #define UART_CLOCK_SCALE_MAX_VAL 0xFF
132 #define UART_CLOCK_STEP_MAX_VAL 0xFFFF
137 #define GPIO_COUNT 30
138 #define GPIO_OE_REG GPIO_BASE_REG + 0x00
139 #define GPIO_IN_REG GPIO_BASE_REG + 0x04
140 #define GPIO_OUT_REG GPIO_BASE_REG + 0x08
141 #define GPIO_SET_REG GPIO_BASE_REG + 0x0C
142 #define GPIO_CLEAR_REG GPIO_BASE_REG + 0x10
143 #define GPIO_INT_ENABLE_REG GPIO_BASE_REG + 0x14
144 #define GPIO_INT_TYPE_REG GPIO_BASE_REG + 0x18
145 #define GPIO_INT_POLARITY_REG GPIO_BASE_REG + 0x1C
146 #define GPIO_INT_PENDING_REG GPIO_BASE_REG + 0x20
147 #define GPIO_INT_MASK_REG GPIO_BASE_REG + 0x24
148 #define GPIO_FUNCTION_1_REG GPIO_BASE_REG + 0x28
149 #define GPIO_IN_ETH_SWITCH_LED_REG GPIO_BASE_REG + 0x2C
150 #define GPIO_FUNCTION_2_REG GPIO_BASE_REG + 0x30
153 * GPIO registers _BIT fields
155 #define _GPIO_X_MASK(_gpio) (1 << _gpio)
156 #define GPIO0 _GPIO_X_MASK(0)
157 #define GPIO1 _GPIO_X_MASK(1)
158 #define GPIO2 _GPIO_X_MASK(2)
159 #define GPIO3 _GPIO_X_MASK(3)
160 #define GPIO4 _GPIO_X_MASK(4)
161 #define GPIO5 _GPIO_X_MASK(5)
162 #define GPIO6 _GPIO_X_MASK(6)
163 #define GPIO7 _GPIO_X_MASK(7)
164 #define GPIO8 _GPIO_X_MASK(8)
165 #define GPIO9 _GPIO_X_MASK(9)
166 #define GPIO10 _GPIO_X_MASK(10)
167 #define GPIO11 _GPIO_X_MASK(11)
168 #define GPIO12 _GPIO_X_MASK(12)
169 #define GPIO13 _GPIO_X_MASK(13)
170 #define GPIO14 _GPIO_X_MASK(14)
171 #define GPIO15 _GPIO_X_MASK(15)
172 #define GPIO16 _GPIO_X_MASK(16)
173 #define GPIO17 _GPIO_X_MASK(17)
174 #define GPIO18 _GPIO_X_MASK(18)
175 #define GPIO19 _GPIO_X_MASK(19)
176 #define GPIO20 _GPIO_X_MASK(20)
177 #define GPIO21 _GPIO_X_MASK(21)
178 #define GPIO22 _GPIO_X_MASK(22)
179 #define GPIO23 _GPIO_X_MASK(23)
180 #define GPIO24 _GPIO_X_MASK(24)
181 #define GPIO25 _GPIO_X_MASK(25)
182 #define GPIO26 _GPIO_X_MASK(26)
183 #define GPIO27 _GPIO_X_MASK(27)
184 #define GPIO28 _GPIO_X_MASK(28)
185 #define GPIO29 _GPIO_X_MASK(29)
187 #define GPIO_FUNCTION_1_EJTAG_DIS_SHIFT 0
188 #define GPIO_FUNCTION_1_EJTAG_DIS_MASK (1 << GPIO_FUNCTION_1_EJTAG_DIS_SHIFT)
189 #define GPIO_FUNCTION_1_UART_EN_SHIFT 1
190 #define GPIO_FUNCTION_1_UART_EN_MASK (1 << GPIO_FUNCTION_1_UART_EN_SHIFT)
191 #define GPIO_FUNCTION_1_UART_RTS_CTS_EN_SHIFT 2
192 #define GPIO_FUNCTION_1_UART_RTS_CTS_EN_MASK (1 << GPIO_FUNCTION_1_UART_RTS_CTS_EN_SHIFT)
195 * PLL control registers
197 #define CPU_PLL_CONFIG_REG PLL_BASE_REG + 0x00
198 #define CPU_PLL_CONFIG2_REG PLL_BASE_REG + 0x04
199 #define CPU_CLOCK_CONTROL_REG PLL_BASE_REG + 0x08
200 #define CPU_PLL_DITHER_FRAC_REG PLL_BASE_REG + 0x10
201 #define CPU_PLL_DITHER_REG PLL_BASE_REG + 0x14
202 #define ETHSW_CLOCK_CONTROL_REG PLL_BASE_REG + 0x24
203 #define ETH_XMII_CONTROL_REG PLL_BASE_REG + 0x2C
204 #define USB_SUSPEND_REG PLL_BASE_REG + 0x40
205 #define WLAN_CLOCK_CONTROL_REG PLL_BASE_REG + 0x44
206 #define CPU_PLL_CONTROL_2_REG RTC_BASE_REG + 0x3C
209 * CPU PLL configuration (CPU_PLL_CONFIG) register _BIT fields
211 #define CPU_PLL_CONFIG_DIV_INT_SHIFT 10
212 #define CPU_PLL_CONFIG_DIV_INT_MASK _BITS(CPU_PLL_CONFIG_DIV_INT_SHIFT, 6)
213 #define CPU_PLL_CONFIG_REFDIV_SHIFT 16
214 #define CPU_PLL_CONFIG_REFDIV_MASK _BITS(CPU_PLL_CONFIG_REFDIV_SHIFT, 5)
215 #define CPU_PLL_CONFIG_RANGE_SHIFT 21
216 #define CPU_PLL_CONFIG_RANGE_MASK (1 << CPU_PLL_CONFIG_RANGE_SHIFT)
217 #define CPU_PLL_CONFIG_OUTDIV_SHIFT 23
218 #define CPU_PLL_CONFIG_OUTDIV_MASK _BITS(CPU_PLL_CONFIG_OUTDIV_SHIFT, 3)
219 #define CPU_PLL_CONFIG_CPU_PLLPWD_SHIFT 30
220 #define CPU_PLL_CONFIG_CPU_PLLPWD_MASK (1 << CPU_PLL_CONFIG_CPU_PLLPWD_SHIFT)
221 #define CPU_PLL_CONFIG_UPDATING_SHIFT 31
222 #define CPU_PLL_CONFIG_UPDATING_MASK (1 << CPU_PLL_CONFIG_UPDATING_SHIFT)
225 * Clock configuration (CPU_CLOCK_CONTROL) register _BIT fields
227 #define CPU_CLOCK_CONTROL_BYPASS_SHIFT 2
228 #define CPU_CLOCK_CONTROL_BYPASS_MASK (1 << CPU_CLOCK_CONTROL_BYPASS_SHIFT)
229 #define CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT 5
230 #define CPU_CLOCK_CONTROL_CPU_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT, 2)
231 #define CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT 10
232 #define CPU_CLOCK_CONTROL_DDR_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT, 2)
233 #define CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT 15
234 #define CPU_CLOCK_CONTROL_AHB_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT, 2)
237 * Helper macros for PLL and clock configuration
240 * TODO: remove them from board config file
241 #define CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv, pllpwd) \
242 ( ((0x3F & divint) << 10) | \
243 ((0x1F & refdiv) << 16) | \
244 ((0x1 & range) << 21) | \
245 ((0x7 & outdiv) << 23) | \
246 ((0x1 & pllpwd) << 30) )
248 #define CPU_CLOCK_CONTROL_VAL(bypass, cpudiv, ddrdiv, ahbdiv) \
249 ( ((0x1 & bypass) << 2) | \
250 ((0x3 & (cpudiv - 1)) << 5) | \
251 ((0x3 & (ddrdiv - 1)) << 10) | \
252 ((0x3 & (ahbdiv - 1)) << 15) )
256 * Reset control registers
258 #define RESET_REG RESET_BASE_REG + 0x1C
259 #define BOOTSTRAP_STATUS_REG RESET_BASE_REG + 0xAC
260 #define USB_PHY_RESET_CONTROL_REG RESET_BASE_REG + 0xB0
263 * Bootstrap (BOOT_STRAP) register _BIT fields
265 #define BOOTSTRAP_SEL_25_40M_SHIFT 0
266 #define BOOTSTRAP_SEL_25_40M_MASK (1 << BOOTSTRAP_SEL_25_40M_SHIFT)
267 #define BOOTSTRAP_BOOT_FROM_SPI_SHIFT 1
268 #define BOOTSTRAP_BOOT_FROM_SPI_MASK (1 << BOOTSTRAP_BOOT_FROM_SPI_SHIFT)
269 #define BOOTSTRAP_EEPBUSY_SHIFT 4
270 #define BOOTSTRAP_EEPBUSY_MASK (1 << BOOTSTRAP_EEPBUSY_SHIFT)
271 #define BOOTSTRAP_MEM_TYPE_SHIFT 12
272 #define BOOTSTRAP_MEM_TYPE_MASK _BITS(BOOTSTRAP_MEM_TYPE_SHIFT, 2)
277 #define BOOTSTRAP_MEM_TYPE_SDRAM_VAL 0x0
278 #define BOOTSTRAP_MEM_TYPE_DDR1_VAL 0x1
279 #define BOOTSTRAP_MEM_TYPE_DDR2_VAL 0x2
282 * Reset (RST_RESET) register _BIT fields
284 #define RESET_I2S_RESET_SHIFT 0
285 #define RESET_I2S_RESET_MASK (1 << RESET_I2S_RESET_SHIFT)
286 #define RESET_MBOX_RESET_SHIFT 1
287 #define RESET_MBOX_RESET_MASK (1 << RESET_MBOX_RESET_SHIFT)
288 #define RESET_USB_SUSPEND_OVERRIDE_SHIFT 3
289 #define RESET_USB_SUSPEND_OVERRIDE_MASK (1 << RESET_USB_SUSPEND_OVERRIDE_SHIFT)
290 #define RESET_USB_PHY_RESET_SHIFT 4
291 #define RESET_USB_PHY_RESET_MASK (1 << RESET_USB_PHY_RESET_SHIFT)
292 #define RESET_USB_HOST_RESET_SHIFT 5
293 #define RESET_USB_HOST_RESET_MASK (1 << RESET_USB_HOST_RESET_SHIFT)
294 #define RESET_ETH_SWITCH_RESET_SHIFT 8
295 #define RESET_ETH_SWITCH_RESET_MASK (1 << RESET_ETH_SWITCH_RESET_SHIFT)
296 #define RESET_GE0_MAC_RESET_SHIFT 9
297 #define RESET_GE0_MAC_RESET_MASK (1 << RESET_GE0_MAC_RESET_SHIFT)
298 #define RESET_WLAN_RESET_SHIFT 11
299 #define RESET_WLAN_RESET_MASK (1 << RESET_WLAN_RESET_SHIFT)
300 #define RESET_GE1_MAC_RESET_SHIFT 13
301 #define RESET_GE1_MAC_RESET_MASK (1 << RESET_GE1_MAC_RESET_SHIFT)
302 #define RESET_SWITCH_ANALOG_RESET_SHIFT 14
303 #define RESET_SWITCH_ANALOG_RESET_MASK (1 << RESET_SWITCH_ANALOG_RESET_SHIFT)
304 #define RESET_DDR_RESET_SHIFT 16
305 #define RESET_DDR_RESET_MASK (1 << RESET_DDR_RESET_SHIFT)
306 #define RESET_CPU_COLD_RESET_SHIFT 20
307 #define RESET_CPU_COLD_RESET_MASK (1 << RESET_CPU_COLD_RESET_SHIFT)
308 #define RESET_CPU_NMI_SHIFT 21
309 #define RESET_CPU_NMI_MASK (1 << RESET_CPU_NMI_SHIFT)
310 #define RESET_GE0_MDIO_RESET_SHIFT 22
311 #define RESET_GE0_MDIO_RESET_MASK (1 << RESET_GE0_MDIO_RESET_SHIFT)
312 #define RESET_GE1_MDIO_RESET_SHIFT 23
313 #define RESET_GE1_MDIO_RESET_MASK (1 << RESET_GE1_MDIO_RESET_SHIFT)
314 #define RESET_FULL_CHIP_RESET_SHIFT 24
315 #define RESET_FULL_CHIP_RESET_MASK (1 << RESET_FULL_CHIP_RESET_SHIFT)
316 #define RESET_EXTERNAL_RESET_SHIFT 28
317 #define RESET_EXTERNAL_RESET_MASK (1 << RESET_EXTERNAL_RESET_SHIFT)
320 * RTC interface registers
322 #define RTC_RESET_REG RTC_BASE_REG + 0x40
323 #define RTC_STATUS_REG RTC_BASE_REG + 0x44
324 #define RTC_FORCE_DERIVED_REG RTC_BASE_REG + 0x48
325 #define RTC_FORCE_WAKE_REG RTC_BASE_REG + 0x4C
326 #define RTC_INT_CAUSE_REG RTC_BASE_REG + 0x50
327 #define RTC_INT_CAUSE_CLEAR_REG RTC_BASE_REG + 0x50
328 #define RTC_INT_ENABLE_REG RTC_BASE_REG + 0x54
329 #define RTC_INT_MASK_REG RTC_BASE_REG + 0x58
332 * RTC sleep status (RTC_STATUS) register _BIT fields
334 #define RTC_STATUS_SHUDOWN_SHIFT 0
335 #define RTC_STATUS_SHUDOWN_MASK (1 << RTC_STATUS_SHUDOWN_SHIFT)
336 #define RTC_STATUS_ON_SHIFT 1
337 #define RTC_STATUS_ON_MASK (1 << RTC_STATUS_ON_SHIFT)
338 #define RTC_STATUS_SLEEP_SHIFT 2
339 #define RTC_STATUS_SLEEP_MASK (1 << RTC_STATUS_SLEEP_SHIFT)
340 #define RTC_STATUS_WAKEUP_SHIFT 3
341 #define RTC_STATUS_WAKEUP_MASK (1 << RTC_STATUS_WAKEUP_SHIFT)
342 #define RTC_STATUS_COLD_RESET_SHIFT 4
343 #define RTC_STATUS_COLD_RESET_MASK (1 << RTC_STATUS_COLD_RESET_SHIFT)
344 #define RTC_STATUS_PLL_CHANGING_SHIFT 5
345 #define RTC_STATUS_PLL_CHANGING_MASK (1 << RTC_STATUS_PLL_CHANGING_SHIFT)
348 * SPI serial flash registers
350 #define SPI_FUNCTION_SELECT_REG FLASH_BASE_REG + 0x0
351 #define SPI_CONTROL_REG FLASH_BASE_REG + 0x4
352 #define SPI_IO_CONTROL_REG FLASH_BASE_REG + 0x8
353 #define SPI_READ_DATA_REG FLASH_BASE_REG + 0xC
356 struct ar933x_spi_flash_regs {
363 struct ar933x_reset1_regs {
365 u32 general_timer0_reload;
366 u32 watchdog_timer_control;
368 u32 misc_interrupt_mask;
369 u32 global_interrupt_mask;
373 struct ar933x_reset2_regs {
376 u32 general_timer1_reload;
378 u32 general_timer2_reload;
380 u32 general_timer3_reload;
382 u32 usb_phy_reset_control;
385 extern const struct ar933x_spi_flash_regs *ar933x_spi_flash;
386 extern const struct ar933x_reset1_regs *ar933x_reset1;
387 extern const struct ar933x_reset2_regs *ar933x_reset2;
389 extern int ar933x_40MHz_xtal(void);
390 #endif /* !__ASSEMBLY__ */
393 * Read, write, set and clear macros
395 #define ar933x_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
396 #define ar933x_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
398 #define ar933x_reg_read_set(_addr, _mask) \
399 ar933x_reg_write((_addr), (ar933x_reg_read((_addr)) | (_mask)))
401 #define ar933x_reg_read_clear(_addr, _mask) \
402 ar933x_reg_write((_addr), (ar933x_reg_read((_addr)) & ~(_mask)))
404 #endif /* _AR933X_H_ */