2 * Atheros AR924X series processor SOC registers
\r
4 * (C) Copyright 2008 Atheros Communications, Inc.
\r
6 * This program is free software; you can redistribute it and/or
\r
7 * modify it under the terms of the GNU General Public License as
\r
8 * published by the Free Software Foundation; either version 2 of
\r
9 * the License, or (at your option) any later version.
\r
11 * This program is distributed in the hope that it will be useful,
\r
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 * GNU General Public License for more details.
\r
16 * You should have received a copy of the GNU General Public License
\r
17 * along with this program; if not, write to the Free Software
\r
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
\r
22 #ifndef _AR934X_SOC_H
\r
23 #define _AR934X_SOC_H
\r
25 // 32'h0000 (CPU_PLL_CONFIG)
\r
26 #define CPU_PLL_CONFIG_UPDATING_MSB 31
\r
27 #define CPU_PLL_CONFIG_UPDATING_LSB 31
\r
28 #define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
\r
29 #define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
\r
30 #define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
\r
31 #define CPU_PLL_CONFIG_UPDATING_RESET 1
\r
32 #define CPU_PLL_CONFIG_PLLPWD_MSB 30
\r
33 #define CPU_PLL_CONFIG_PLLPWD_LSB 30
\r
34 #define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
\r
35 #define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
\r
36 #define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
\r
37 #define CPU_PLL_CONFIG_PLLPWD_RESET 1
\r
38 #define CPU_PLL_CONFIG_SPARE_MSB 29
\r
39 #define CPU_PLL_CONFIG_SPARE_LSB 22
\r
40 #define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
\r
41 #define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
\r
42 #define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
\r
43 #define CPU_PLL_CONFIG_SPARE_RESET 0
\r
44 #define CPU_PLL_CONFIG_OUTDIV_MSB 21
\r
45 #define CPU_PLL_CONFIG_OUTDIV_LSB 19
\r
46 #define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
\r
47 #define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
\r
48 #define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
\r
49 #define CPU_PLL_CONFIG_OUTDIV_RESET 0
\r
50 #define CPU_PLL_CONFIG_RANGE_MSB 18
\r
51 #define CPU_PLL_CONFIG_RANGE_LSB 17
\r
52 #define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
\r
53 #define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
\r
54 #define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
\r
55 #define CPU_PLL_CONFIG_RANGE_RESET 3
\r
56 #define CPU_PLL_CONFIG_REFDIV_MSB 16
\r
57 #define CPU_PLL_CONFIG_REFDIV_LSB 12
\r
58 #define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
\r
59 #define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
\r
60 #define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
\r
61 #define CPU_PLL_CONFIG_REFDIV_RESET 2
\r
62 #define CPU_PLL_CONFIG_NINT_MSB 11
\r
63 #define CPU_PLL_CONFIG_NINT_LSB 6
\r
64 #define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
\r
65 #define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
\r
66 #define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
\r
67 #define CPU_PLL_CONFIG_NINT_RESET 20
\r
68 #define CPU_PLL_CONFIG_NFRAC_MSB 5
\r
69 #define CPU_PLL_CONFIG_NFRAC_LSB 0
\r
70 #define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
\r
71 #define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
\r
72 #define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
\r
73 #define CPU_PLL_CONFIG_NFRAC_RESET 16
\r
74 #define CPU_PLL_CONFIG_ADDRESS 0x0000
\r
75 #define CPU_PLL_CONFIG_OFFSET 0x0000
\r
76 // SW modifiable bits
\r
77 #define CPU_PLL_CONFIG_SW_MASK 0xffffffff
\r
78 // bits defined at reset
\r
79 #define CPU_PLL_CONFIG_RSTMASK 0xffffffff
\r
80 // reset value (ignore bits undefined at reset)
\r
81 #define CPU_PLL_CONFIG_RESET 0xc0062510
\r
83 // 32'h0004 (DDR_PLL_CONFIG)
\r
84 #define DDR_PLL_CONFIG_UPDATING_MSB 31
\r
85 #define DDR_PLL_CONFIG_UPDATING_LSB 31
\r
86 #define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
\r
87 #define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
\r
88 #define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
\r
89 #define DDR_PLL_CONFIG_UPDATING_RESET 1
\r
90 #define DDR_PLL_CONFIG_PLLPWD_MSB 30
\r
91 #define DDR_PLL_CONFIG_PLLPWD_LSB 30
\r
92 #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
\r
93 #define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
\r
94 #define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
\r
95 #define DDR_PLL_CONFIG_PLLPWD_RESET 1
\r
96 #define DDR_PLL_CONFIG_SPARE_MSB 29
\r
97 #define DDR_PLL_CONFIG_SPARE_LSB 26
\r
98 #define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
\r
99 #define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
\r
100 #define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
\r
101 #define DDR_PLL_CONFIG_SPARE_RESET 0
\r
102 #define DDR_PLL_CONFIG_OUTDIV_MSB 25
\r
103 #define DDR_PLL_CONFIG_OUTDIV_LSB 23
\r
104 #define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
\r
105 #define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
\r
106 #define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
\r
107 #define DDR_PLL_CONFIG_OUTDIV_RESET 0
\r
108 #define DDR_PLL_CONFIG_RANGE_MSB 22
\r
109 #define DDR_PLL_CONFIG_RANGE_LSB 21
\r
110 #define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
\r
111 #define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
\r
112 #define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
\r
113 #define DDR_PLL_CONFIG_RANGE_RESET 3
\r
114 #define DDR_PLL_CONFIG_REFDIV_MSB 20
\r
115 #define DDR_PLL_CONFIG_REFDIV_LSB 16
\r
116 #define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
\r
117 #define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
\r
118 #define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
\r
119 #define DDR_PLL_CONFIG_REFDIV_RESET 2
\r
120 #define DDR_PLL_CONFIG_NINT_MSB 15
\r
121 #define DDR_PLL_CONFIG_NINT_LSB 10
\r
122 #define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
\r
123 #define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
\r
124 #define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
\r
125 #define DDR_PLL_CONFIG_NINT_RESET 20
\r
126 #define DDR_PLL_CONFIG_NFRAC_MSB 9
\r
127 #define DDR_PLL_CONFIG_NFRAC_LSB 0
\r
128 #define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
\r
129 #define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
\r
130 #define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
\r
131 #define DDR_PLL_CONFIG_NFRAC_RESET 512
\r
132 #define DDR_PLL_CONFIG_ADDRESS 0x0004
\r
133 #define DDR_PLL_CONFIG_OFFSET 0x0004
\r
134 // SW modifiable bits
\r
135 #define DDR_PLL_CONFIG_SW_MASK 0xffffffff
\r
136 // bits defined at reset
\r
137 #define DDR_PLL_CONFIG_RSTMASK 0xffffffff
\r
138 // reset value (ignore bits undefined at reset)
\r
139 #define DDR_PLL_CONFIG_RESET 0xc0625200
\r
141 // 32'h0008 (CPU_DDR_CLOCK_CONTROL)
\r
142 #define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
\r
143 #define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
\r
144 #define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
\r
145 #define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
\r
146 #define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
\r
147 #define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0
\r
148 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
\r
149 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
\r
150 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
\r
151 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
\r
152 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
\r
153 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1
\r
154 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
\r
155 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
\r
156 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
\r
157 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
\r
158 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
\r
159 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0
\r
160 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
\r
161 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
\r
162 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
\r
163 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
\r
164 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
\r
165 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0
\r
166 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21
\r
167 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21
\r
168 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000
\r
169 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB)
\r
170 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK)
\r
171 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 1
\r
172 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20
\r
173 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20
\r
174 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000
\r
175 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB)
\r
176 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK)
\r
177 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 1
\r
178 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
\r
179 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
\r
180 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
\r
181 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
\r
182 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
\r
183 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0
\r
184 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
\r
185 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
\r
186 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
\r
187 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
\r
188 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
\r
189 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0
\r
190 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
\r
191 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
\r
192 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
\r
193 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
\r
194 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
\r
195 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0
\r
196 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
\r
197 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
\r
198 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
\r
199 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
\r
200 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
\r
201 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1
\r
202 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
\r
203 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
\r
204 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
\r
205 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
\r
206 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
\r
207 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1
\r
208 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
\r
209 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
\r
210 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
\r
211 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
\r
212 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
\r
213 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1
\r
214 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
\r
215 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
\r
216 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
\r
217 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
\r
218 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
\r
219 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0
\r
220 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
\r
221 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
\r
222 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
\r
223 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
\r
224 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
\r
225 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0
\r
226 #define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x0008
\r
227 #define CPU_DDR_CLOCK_CONTROL_OFFSET 0x0008
\r
228 // SW modifiable bits
\r
229 #define CPU_DDR_CLOCK_CONTROL_SW_MASK 0xffffffff
\r
230 // bits defined at reset
\r
231 #define CPU_DDR_CLOCK_CONTROL_RSTMASK 0xffffffff
\r
232 // reset value (ignore bits undefined at reset)
\r
233 #define CPU_DDR_CLOCK_CONTROL_RESET 0x0130001c
\r
235 // 32'h000c (CPU_SYNC)
\r
236 #define CPU_SYNC_LENGTH_MSB 19
\r
237 #define CPU_SYNC_LENGTH_LSB 16
\r
238 #define CPU_SYNC_LENGTH_MASK 0x000f0000
\r
239 #define CPU_SYNC_LENGTH_GET(x) (((x) & CPU_SYNC_LENGTH_MASK) >> CPU_SYNC_LENGTH_LSB)
\r
240 #define CPU_SYNC_LENGTH_SET(x) (((x) << CPU_SYNC_LENGTH_LSB) & CPU_SYNC_LENGTH_MASK)
\r
241 #define CPU_SYNC_LENGTH_RESET 0
\r
242 #define CPU_SYNC_PATTERN_MSB 15
\r
243 #define CPU_SYNC_PATTERN_LSB 0
\r
244 #define CPU_SYNC_PATTERN_MASK 0x0000ffff
\r
245 #define CPU_SYNC_PATTERN_GET(x) (((x) & CPU_SYNC_PATTERN_MASK) >> CPU_SYNC_PATTERN_LSB)
\r
246 #define CPU_SYNC_PATTERN_SET(x) (((x) << CPU_SYNC_PATTERN_LSB) & CPU_SYNC_PATTERN_MASK)
\r
247 #define CPU_SYNC_PATTERN_RESET 65535
\r
248 #define CPU_SYNC_ADDRESS 0x000c
\r
249 #define CPU_SYNC_OFFSET 0x000c
\r
250 // SW modifiable bits
\r
251 #define CPU_SYNC_SW_MASK 0x000fffff
\r
252 // bits defined at reset
\r
253 #define CPU_SYNC_RSTMASK 0xffffffff
\r
254 // reset value (ignore bits undefined at reset)
\r
255 #define CPU_SYNC_RESET 0x0000ffff
\r
257 // 32'h0010 (PCIE_PLL_CONFIG)
\r
258 #define PCIE_PLL_CONFIG_UPDATING_MSB 31
\r
259 #define PCIE_PLL_CONFIG_UPDATING_LSB 31
\r
260 #define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000
\r
261 #define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
\r
262 #define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
\r
263 #define PCIE_PLL_CONFIG_UPDATING_RESET 0
\r
264 #define PCIE_PLL_CONFIG_PLLPWD_MSB 30
\r
265 #define PCIE_PLL_CONFIG_PLLPWD_LSB 30
\r
266 #define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000
\r
267 #define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
\r
268 #define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
\r
269 #define PCIE_PLL_CONFIG_PLLPWD_RESET 1
\r
270 #define PCIE_PLL_CONFIG_BYPASS_MSB 16
\r
271 #define PCIE_PLL_CONFIG_BYPASS_LSB 16
\r
272 #define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000
\r
273 #define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
\r
274 #define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
\r
275 #define PCIE_PLL_CONFIG_BYPASS_RESET 1
\r
276 #define PCIE_PLL_CONFIG_REFDIV_MSB 14
\r
277 #define PCIE_PLL_CONFIG_REFDIV_LSB 10
\r
278 #define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00
\r
279 #define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
\r
280 #define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
\r
281 #define PCIE_PLL_CONFIG_REFDIV_RESET 1
\r
282 #define PCIE_PLL_CONFIG_ADDRESS 0x0010
\r
283 #define PCIE_PLL_CONFIG_OFFSET 0x0010
\r
284 // SW modifiable bits
\r
285 #define PCIE_PLL_CONFIG_SW_MASK 0xc0017c00
\r
286 // bits defined at reset
\r
287 #define PCIE_PLL_CONFIG_RSTMASK 0xffffffff
\r
288 // reset value (ignore bits undefined at reset)
\r
289 #define PCIE_PLL_CONFIG_RESET 0x40010400
\r
291 // 32'h0014 (PCIE_PLL_DITHER_DIV_MAX)
\r
292 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31
\r
293 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31
\r
294 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000
\r
295 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
\r
296 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
\r
297 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 1
\r
298 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30
\r
299 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30
\r
300 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000
\r
301 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
\r
302 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
\r
303 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 1
\r
304 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20
\r
305 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15
\r
306 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000
\r
307 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
\r
308 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
\r
309 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 19
\r
310 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14
\r
311 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1
\r
312 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe
\r
313 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
\r
314 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
\r
315 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 16383
\r
316 #define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x0014
\r
317 #define PCIE_PLL_DITHER_DIV_MAX_OFFSET 0x0014
\r
318 // SW modifiable bits
\r
319 #define PCIE_PLL_DITHER_DIV_MAX_SW_MASK 0xc01ffffe
\r
320 // bits defined at reset
\r
321 #define PCIE_PLL_DITHER_DIV_MAX_RSTMASK 0xffffffff
\r
322 // reset value (ignore bits undefined at reset)
\r
323 #define PCIE_PLL_DITHER_DIV_MAX_RESET 0xc009fffe
\r
325 // 32'h0018 (PCIE_PLL_DITHER_DIV_MIN)
\r
326 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20
\r
327 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15
\r
328 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000
\r
329 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
\r
330 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
\r
331 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 19
\r
332 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14
\r
333 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1
\r
334 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe
\r
335 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
\r
336 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
\r
337 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 14749
\r
338 #define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x0018
\r
339 #define PCIE_PLL_DITHER_DIV_MIN_OFFSET 0x0018
\r
340 // SW modifiable bits
\r
341 #define PCIE_PLL_DITHER_DIV_MIN_SW_MASK 0x001ffffe
\r
342 // bits defined at reset
\r
343 #define PCIE_PLL_DITHER_DIV_MIN_RSTMASK 0xffffffff
\r
344 // reset value (ignore bits undefined at reset)
\r
345 #define PCIE_PLL_DITHER_DIV_MIN_RESET 0x0009f33a
\r
347 // 32'h001c (PCIE_PLL_DITHER_STEP)
\r
348 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31
\r
349 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28
\r
350 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000
\r
351 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
\r
352 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
\r
353 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0
\r
354 #define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24
\r
355 #define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15
\r
356 #define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000
\r
357 #define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
\r
358 #define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
\r
359 #define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0
\r
360 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14
\r
361 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1
\r
362 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe
\r
363 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
\r
364 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
\r
365 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 10
\r
366 #define PCIE_PLL_DITHER_STEP_ADDRESS 0x001c
\r
367 #define PCIE_PLL_DITHER_STEP_OFFSET 0x001c
\r
368 // SW modifiable bits
\r
369 #define PCIE_PLL_DITHER_STEP_SW_MASK 0xf1fffffe
\r
370 // bits defined at reset
\r
371 #define PCIE_PLL_DITHER_STEP_RSTMASK 0xffffffff
\r
372 // reset value (ignore bits undefined at reset)
\r
373 #define PCIE_PLL_DITHER_STEP_RESET 0x00000014
\r
375 // 32'h0020 (LDO_POWER_CONTROL)
\r
376 #define LDO_POWER_CONTROL_PKG_SEL_MSB 5
\r
377 #define LDO_POWER_CONTROL_PKG_SEL_LSB 5
\r
378 #define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020
\r
379 #define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
\r
380 #define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
\r
381 #define LDO_POWER_CONTROL_PKG_SEL_RESET 0
\r
382 #define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4
\r
383 #define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4
\r
384 #define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010
\r
385 #define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
\r
386 #define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
\r
387 #define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0
\r
388 #define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3
\r
389 #define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3
\r
390 #define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008
\r
391 #define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
\r
392 #define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
\r
393 #define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0
\r
394 #define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2
\r
395 #define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1
\r
396 #define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006
\r
397 #define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
\r
398 #define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
\r
399 #define LDO_POWER_CONTROL_CPU_REFSEL_RESET 3
\r
400 #define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0
\r
401 #define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0
\r
402 #define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001
\r
403 #define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
\r
404 #define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
\r
405 #define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0
\r
406 #define LDO_POWER_CONTROL_ADDRESS 0x0020
\r
407 #define LDO_POWER_CONTROL_OFFSET 0x0020
\r
408 // SW modifiable bits
\r
409 #define LDO_POWER_CONTROL_SW_MASK 0x0000003f
\r
410 // bits defined at reset
\r
411 #define LDO_POWER_CONTROL_RSTMASK 0xffffffff
\r
412 // reset value (ignore bits undefined at reset)
\r
413 #define LDO_POWER_CONTROL_RESET 0x00000006
\r
415 // 32'h0024 (SWITCH_CLOCK_SPARE)
\r
416 #define SWITCH_CLOCK_SPARE_SPARE_MSB 31
\r
417 #define SWITCH_CLOCK_SPARE_SPARE_LSB 12
\r
418 #define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000
\r
419 #define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
\r
420 #define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
\r
421 #define SWITCH_CLOCK_SPARE_SPARE_RESET 0
\r
422 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
\r
423 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
\r
424 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
\r
425 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
\r
426 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
\r
427 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 5
\r
428 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
\r
429 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
\r
430 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
\r
431 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
\r
432 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
\r
433 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0
\r
434 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6
\r
435 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6
\r
436 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040
\r
437 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB)
\r
438 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK)
\r
439 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0
\r
440 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5
\r
441 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5
\r
442 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020
\r
443 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)
\r
444 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)
\r
445 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 1
\r
446 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4
\r
447 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4
\r
448 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010
\r
449 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)
\r
450 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)
\r
451 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 1
\r
452 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3
\r
453 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3
\r
454 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008
\r
455 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)
\r
456 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)
\r
457 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0
\r
458 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2
\r
459 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2
\r
460 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004
\r
461 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB)
\r
462 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK)
\r
463 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0
\r
464 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1
\r
465 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1
\r
466 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002
\r
467 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)
\r
468 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)
\r
469 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0
\r
470 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0
\r
471 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0
\r
472 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001
\r
473 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)
\r
474 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)
\r
475 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 1
\r
476 #define SWITCH_CLOCK_SPARE_ADDRESS 0x0024
\r
477 #define SWITCH_CLOCK_SPARE_OFFSET 0x0024
\r
478 // SW modifiable bits
\r
479 #define SWITCH_CLOCK_SPARE_SW_MASK 0xffffffff
\r
480 // bits defined at reset
\r
481 #define SWITCH_CLOCK_SPARE_RSTMASK 0xffffffff
\r
482 // reset value (ignore bits undefined at reset)
\r
483 #define SWITCH_CLOCK_SPARE_RESET 0x00000531
\r
485 // 32'h0028 (CURRENT_PCIE_PLL_DITHER)
\r
486 #define CURRENT_PCIE_PLL_DITHER_INT_MSB 20
\r
487 #define CURRENT_PCIE_PLL_DITHER_INT_LSB 15
\r
488 #define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000
\r
489 #define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)
\r
490 #define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)
\r
491 #define CURRENT_PCIE_PLL_DITHER_INT_RESET 1
\r
492 #define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13
\r
493 #define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0
\r
494 #define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff
\r
495 #define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)
\r
496 #define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)
\r
497 #define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0
\r
498 #define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x0028
\r
499 #define CURRENT_PCIE_PLL_DITHER_OFFSET 0x0028
\r
500 // SW modifiable bits
\r
501 #define CURRENT_PCIE_PLL_DITHER_SW_MASK 0x001fbfff
\r
502 // bits defined at reset
\r
503 #define CURRENT_PCIE_PLL_DITHER_RSTMASK 0xffffffff
\r
504 // reset value (ignore bits undefined at reset)
\r
505 #define CURRENT_PCIE_PLL_DITHER_RESET 0x00008000
\r
507 // 32'h002c (ETH_XMII)
\r
508 #define ETH_XMII_TX_INVERT_MSB 31
\r
509 #define ETH_XMII_TX_INVERT_LSB 31
\r
510 #define ETH_XMII_TX_INVERT_MASK 0x80000000
\r
511 #define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
\r
512 #define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
\r
513 #define ETH_XMII_TX_INVERT_RESET 0
\r
514 #define ETH_XMII_GIGE_QUAD_MSB 30
\r
515 #define ETH_XMII_GIGE_QUAD_LSB 30
\r
516 #define ETH_XMII_GIGE_QUAD_MASK 0x40000000
\r
517 #define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
\r
518 #define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
\r
519 #define ETH_XMII_GIGE_QUAD_RESET 0
\r
520 #define ETH_XMII_RX_DELAY_MSB 29
\r
521 #define ETH_XMII_RX_DELAY_LSB 28
\r
522 #define ETH_XMII_RX_DELAY_MASK 0x30000000
\r
523 #define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
\r
524 #define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
\r
525 #define ETH_XMII_RX_DELAY_RESET 0
\r
526 #define ETH_XMII_TX_DELAY_MSB 27
\r
527 #define ETH_XMII_TX_DELAY_LSB 26
\r
528 #define ETH_XMII_TX_DELAY_MASK 0x0c000000
\r
529 #define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
\r
530 #define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
\r
531 #define ETH_XMII_TX_DELAY_RESET 0
\r
532 #define ETH_XMII_GIGE_MSB 25
\r
533 #define ETH_XMII_GIGE_LSB 25
\r
534 #define ETH_XMII_GIGE_MASK 0x02000000
\r
535 #define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
\r
536 #define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
\r
537 #define ETH_XMII_GIGE_RESET 0
\r
538 #define ETH_XMII_OFFSET_PHASE_MSB 24
\r
539 #define ETH_XMII_OFFSET_PHASE_LSB 24
\r
540 #define ETH_XMII_OFFSET_PHASE_MASK 0x01000000
\r
541 #define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
\r
542 #define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
\r
543 #define ETH_XMII_OFFSET_PHASE_RESET 0
\r
544 #define ETH_XMII_OFFSET_COUNT_MSB 23
\r
545 #define ETH_XMII_OFFSET_COUNT_LSB 16
\r
546 #define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000
\r
547 #define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
\r
548 #define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
\r
549 #define ETH_XMII_OFFSET_COUNT_RESET 0
\r
550 #define ETH_XMII_PHASE1_COUNT_MSB 15
\r
551 #define ETH_XMII_PHASE1_COUNT_LSB 8
\r
552 #define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00
\r
553 #define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
\r
554 #define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
\r
555 #define ETH_XMII_PHASE1_COUNT_RESET 1
\r
556 #define ETH_XMII_PHASE0_COUNT_MSB 7
\r
557 #define ETH_XMII_PHASE0_COUNT_LSB 0
\r
558 #define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff
\r
559 #define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
\r
560 #define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
\r
561 #define ETH_XMII_PHASE0_COUNT_RESET 1
\r
562 #define ETH_XMII_ADDRESS 0x002c
\r
563 #define ETH_XMII_OFFSET 0x002c
\r
564 // SW modifiable bits
\r
565 #define ETH_XMII_SW_MASK 0xffffffff
\r
566 // bits defined at reset
\r
567 #define ETH_XMII_RSTMASK 0xffffffff
\r
568 // reset value (ignore bits undefined at reset)
\r
569 #define ETH_XMII_RESET 0x00000101
\r
571 // 32'h0030 (AUDIO_PLL_CONFIG)
\r
572 #define AUDIO_PLL_CONFIG_UPDATING_MSB 31
\r
573 #define AUDIO_PLL_CONFIG_UPDATING_LSB 31
\r
574 #define AUDIO_PLL_CONFIG_UPDATING_MASK 0x80000000
\r
575 #define AUDIO_PLL_CONFIG_UPDATING_GET(x) (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB)
\r
576 #define AUDIO_PLL_CONFIG_UPDATING_SET(x) (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK)
\r
577 #define AUDIO_PLL_CONFIG_UPDATING_RESET 1
\r
578 #define AUDIO_PLL_CONFIG_EXT_DIV_MSB 14
\r
579 #define AUDIO_PLL_CONFIG_EXT_DIV_LSB 12
\r
580 #define AUDIO_PLL_CONFIG_EXT_DIV_MASK 0x00007000
\r
581 #define AUDIO_PLL_CONFIG_EXT_DIV_GET(x) (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB)
\r
582 #define AUDIO_PLL_CONFIG_EXT_DIV_SET(x) (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK)
\r
583 #define AUDIO_PLL_CONFIG_EXT_DIV_RESET 1
\r
584 #define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB 9
\r
585 #define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB 7
\r
586 #define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK 0x00000380
\r
587 #define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB)
\r
588 #define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK)
\r
589 #define AUDIO_PLL_CONFIG_POSTPLLDIV_RESET 1
\r
590 #define AUDIO_PLL_CONFIG_PLLPWD_MSB 5
\r
591 #define AUDIO_PLL_CONFIG_PLLPWD_LSB 5
\r
592 #define AUDIO_PLL_CONFIG_PLLPWD_MASK 0x00000020
\r
593 #define AUDIO_PLL_CONFIG_PLLPWD_GET(x) (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB)
\r
594 #define AUDIO_PLL_CONFIG_PLLPWD_SET(x) (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK)
\r
595 #define AUDIO_PLL_CONFIG_PLLPWD_RESET 1
\r
596 #define AUDIO_PLL_CONFIG_BYPASS_MSB 4
\r
597 #define AUDIO_PLL_CONFIG_BYPASS_LSB 4
\r
598 #define AUDIO_PLL_CONFIG_BYPASS_MASK 0x00000010
\r
599 #define AUDIO_PLL_CONFIG_BYPASS_GET(x) (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB)
\r
600 #define AUDIO_PLL_CONFIG_BYPASS_SET(x) (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK)
\r
601 #define AUDIO_PLL_CONFIG_BYPASS_RESET 1
\r
602 #define AUDIO_PLL_CONFIG_REFDIV_MSB 3
\r
603 #define AUDIO_PLL_CONFIG_REFDIV_LSB 0
\r
604 #define AUDIO_PLL_CONFIG_REFDIV_MASK 0x0000000f
\r
605 #define AUDIO_PLL_CONFIG_REFDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB)
\r
606 #define AUDIO_PLL_CONFIG_REFDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK)
\r
607 #define AUDIO_PLL_CONFIG_REFDIV_RESET 3
\r
608 #define AUDIO_PLL_CONFIG_ADDRESS 0x0030
\r
609 #define AUDIO_PLL_CONFIG_OFFSET 0x0030
\r
610 // SW modifiable bits
\r
611 #define AUDIO_PLL_CONFIG_SW_MASK 0x800073bf
\r
612 // bits defined at reset
\r
613 #define AUDIO_PLL_CONFIG_RSTMASK 0xffffffff
\r
614 // reset value (ignore bits undefined at reset)
\r
615 #define AUDIO_PLL_CONFIG_RESET 0x800010b3
\r
617 // 32'h0034 (AUDIO_PLL_MODULATION)
\r
618 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB 28
\r
619 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB 11
\r
620 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK 0x1ffff800
\r
621 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB)
\r
622 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK)
\r
623 #define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_RESET 84222
\r
624 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB 6
\r
625 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB 1
\r
626 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK 0x0000007e
\r
627 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB)
\r
628 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK)
\r
629 #define AUDIO_PLL_MODULATION_TGT_DIV_INT_RESET 20
\r
630 #define AUDIO_PLL_MODULATION_START_MSB 0
\r
631 #define AUDIO_PLL_MODULATION_START_LSB 0
\r
632 #define AUDIO_PLL_MODULATION_START_MASK 0x00000001
\r
633 #define AUDIO_PLL_MODULATION_START_GET(x) (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB)
\r
634 #define AUDIO_PLL_MODULATION_START_SET(x) (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK)
\r
635 #define AUDIO_PLL_MODULATION_START_RESET 0
\r
636 #define AUDIO_PLL_MODULATION_ADDRESS 0x0034
\r
637 #define AUDIO_PLL_MODULATION_OFFSET 0x0034
\r
638 // SW modifiable bits
\r
639 #define AUDIO_PLL_MODULATION_SW_MASK 0x1ffff87f
\r
640 // bits defined at reset
\r
641 #define AUDIO_PLL_MODULATION_RSTMASK 0xffffffff
\r
642 // reset value (ignore bits undefined at reset)
\r
643 #define AUDIO_PLL_MODULATION_RESET 0x0a47f028
\r
645 // 32'h0038 (AUDIO_PLL_MOD_STEP)
\r
646 #define AUDIO_PLL_MOD_STEP_FRAC_MSB 31
\r
647 #define AUDIO_PLL_MOD_STEP_FRAC_LSB 14
\r
648 #define AUDIO_PLL_MOD_STEP_FRAC_MASK 0xffffc000
\r
649 #define AUDIO_PLL_MOD_STEP_FRAC_GET(x) (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB)
\r
650 #define AUDIO_PLL_MOD_STEP_FRAC_SET(x) (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK)
\r
651 #define AUDIO_PLL_MOD_STEP_FRAC_RESET 1
\r
652 #define AUDIO_PLL_MOD_STEP_INT_MSB 13
\r
653 #define AUDIO_PLL_MOD_STEP_INT_LSB 4
\r
654 #define AUDIO_PLL_MOD_STEP_INT_MASK 0x00003ff0
\r
655 #define AUDIO_PLL_MOD_STEP_INT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB)
\r
656 #define AUDIO_PLL_MOD_STEP_INT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK)
\r
657 #define AUDIO_PLL_MOD_STEP_INT_RESET 0
\r
658 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB 3
\r
659 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB 0
\r
660 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK 0x0000000f
\r
661 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB)
\r
662 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK)
\r
663 #define AUDIO_PLL_MOD_STEP_UPDATE_CNT_RESET 0
\r
664 #define AUDIO_PLL_MOD_STEP_ADDRESS 0x0038
\r
665 #define AUDIO_PLL_MOD_STEP_OFFSET 0x0038
\r
666 // SW modifiable bits
\r
667 #define AUDIO_PLL_MOD_STEP_SW_MASK 0xffffffff
\r
668 // bits defined at reset
\r
669 #define AUDIO_PLL_MOD_STEP_RSTMASK 0xffffffff
\r
670 // reset value (ignore bits undefined at reset)
\r
671 #define AUDIO_PLL_MOD_STEP_RESET 0x00004000
\r
673 // 32'h003c (CURRENT_AUDIO_PLL_MODULATION)
\r
674 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB 27
\r
675 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB 10
\r
676 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK 0x0ffffc00
\r
677 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB)
\r
678 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK)
\r
679 #define CURRENT_AUDIO_PLL_MODULATION_FRAC_RESET 1
\r
680 #define CURRENT_AUDIO_PLL_MODULATION_INT_MSB 6
\r
681 #define CURRENT_AUDIO_PLL_MODULATION_INT_LSB 1
\r
682 #define CURRENT_AUDIO_PLL_MODULATION_INT_MASK 0x0000007e
\r
683 #define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB)
\r
684 #define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK)
\r
685 #define CURRENT_AUDIO_PLL_MODULATION_INT_RESET 0
\r
686 #define CURRENT_AUDIO_PLL_MODULATION_ADDRESS 0x003c
\r
687 #define CURRENT_AUDIO_PLL_MODULATION_OFFSET 0x003c
\r
688 // SW modifiable bits
\r
689 #define CURRENT_AUDIO_PLL_MODULATION_SW_MASK 0x0ffffc7e
\r
690 // bits defined at reset
\r
691 #define CURRENT_AUDIO_PLL_MODULATION_RSTMASK 0xffffffff
\r
692 // reset value (ignore bits undefined at reset)
\r
693 #define CURRENT_AUDIO_PLL_MODULATION_RESET 0x00000400
\r
695 #define RST_BOOTSTRAP_ADDRESS 0x180600b0
\r
697 // 32'h0040 (BB_PLL_CONFIG)
\r
698 #define BB_PLL_CONFIG_UPDATING_MSB 31
\r
699 #define BB_PLL_CONFIG_UPDATING_LSB 31
\r
700 #define BB_PLL_CONFIG_UPDATING_MASK 0x80000000
\r
701 #define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)
\r
702 #define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)
\r
703 #define BB_PLL_CONFIG_UPDATING_RESET 1
\r
704 #define BB_PLL_CONFIG_PLLPWD_MSB 30
\r
705 #define BB_PLL_CONFIG_PLLPWD_LSB 30
\r
706 #define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000
\r
707 #define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)
\r
708 #define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)
\r
709 #define BB_PLL_CONFIG_PLLPWD_RESET 1
\r
710 #define BB_PLL_CONFIG_SPARE_MSB 29
\r
711 #define BB_PLL_CONFIG_SPARE_LSB 29
\r
712 #define BB_PLL_CONFIG_SPARE_MASK 0x20000000
\r
713 #define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)
\r
714 #define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)
\r
715 #define BB_PLL_CONFIG_SPARE_RESET 0
\r
716 #define BB_PLL_CONFIG_REFDIV_MSB 28
\r
717 #define BB_PLL_CONFIG_REFDIV_LSB 24
\r
718 #define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000
\r
719 #define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)
\r
720 #define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)
\r
721 #define BB_PLL_CONFIG_REFDIV_RESET 1
\r
722 #define BB_PLL_CONFIG_NINT_MSB 21
\r
723 #define BB_PLL_CONFIG_NINT_LSB 16
\r
724 #define BB_PLL_CONFIG_NINT_MASK 0x003f0000
\r
725 #define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)
\r
726 #define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)
\r
727 #define BB_PLL_CONFIG_NINT_RESET 2
\r
728 #define BB_PLL_CONFIG_NFRAC_MSB 13
\r
729 #define BB_PLL_CONFIG_NFRAC_LSB 0
\r
730 #define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff
\r
731 #define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)
\r
732 #define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)
\r
733 #define BB_PLL_CONFIG_NFRAC_RESET 3276
\r
734 #define BB_PLL_CONFIG_ADDRESS 0x0040
\r
735 #define BB_PLL_CONFIG_OFFSET 0x0040
\r
736 // SW modifiable bits
\r
737 #define BB_PLL_CONFIG_SW_MASK 0xff3f3fff
\r
738 // bits defined at reset
\r
739 #define BB_PLL_CONFIG_RSTMASK 0xffffffff
\r
740 // reset value (ignore bits undefined at reset)
\r
741 #define BB_PLL_CONFIG_RESET 0xc1020ccc
\r
743 // 32'h0044 (DDR_PLL_DITHER)
\r
744 #define DDR_PLL_DITHER_DITHER_EN_MSB 31
\r
745 #define DDR_PLL_DITHER_DITHER_EN_LSB 31
\r
746 #define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
\r
747 #define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
\r
748 #define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
\r
749 #define DDR_PLL_DITHER_DITHER_EN_RESET 0
\r
750 #define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
\r
751 #define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
\r
752 #define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
\r
753 #define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
\r
754 #define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
\r
755 #define DDR_PLL_DITHER_UPDATE_COUNT_RESET 15
\r
756 #define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
\r
757 #define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
\r
758 #define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
\r
759 #define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
\r
760 #define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
\r
761 #define DDR_PLL_DITHER_NFRAC_STEP_RESET 1
\r
762 #define DDR_PLL_DITHER_NFRAC_MIN_MSB 19
\r
763 #define DDR_PLL_DITHER_NFRAC_MIN_LSB 10
\r
764 #define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00
\r
765 #define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
\r
766 #define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
\r
767 #define DDR_PLL_DITHER_NFRAC_MIN_RESET 25
\r
768 #define DDR_PLL_DITHER_NFRAC_MAX_MSB 9
\r
769 #define DDR_PLL_DITHER_NFRAC_MAX_LSB 0
\r
770 #define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff
\r
771 #define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
\r
772 #define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
\r
773 #define DDR_PLL_DITHER_NFRAC_MAX_RESET 1000
\r
774 #define DDR_PLL_DITHER_ADDRESS 0x0044
\r
775 #define DDR_PLL_DITHER_OFFSET 0x0044
\r
776 // SW modifiable bits
\r
777 #define DDR_PLL_DITHER_SW_MASK 0xffffffff
\r
778 // bits defined at reset
\r
779 #define DDR_PLL_DITHER_RSTMASK 0xffffffff
\r
780 // reset value (ignore bits undefined at reset)
\r
781 #define DDR_PLL_DITHER_RESET 0x781067e8
\r
783 // 32'h0048 (CPU_PLL_DITHER)
\r
784 #define CPU_PLL_DITHER_DITHER_EN_MSB 31
\r
785 #define CPU_PLL_DITHER_DITHER_EN_LSB 31
\r
786 #define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
\r
787 #define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
\r
788 #define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
\r
789 #define CPU_PLL_DITHER_DITHER_EN_RESET 0
\r
790 #define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23
\r
791 #define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
\r
792 #define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
\r
793 #define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
\r
794 #define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
\r
795 #define CPU_PLL_DITHER_UPDATE_COUNT_RESET 20
\r
796 #define CPU_PLL_DITHER_NFRAC_STEP_MSB 17
\r
797 #define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
\r
798 #define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
\r
799 #define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
\r
800 #define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
\r
801 #define CPU_PLL_DITHER_NFRAC_STEP_RESET 1
\r
802 #define CPU_PLL_DITHER_NFRAC_MIN_MSB 11
\r
803 #define CPU_PLL_DITHER_NFRAC_MIN_LSB 6
\r
804 #define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0
\r
805 #define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
\r
806 #define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
\r
807 #define CPU_PLL_DITHER_NFRAC_MIN_RESET 3
\r
808 #define CPU_PLL_DITHER_NFRAC_MAX_MSB 5
\r
809 #define CPU_PLL_DITHER_NFRAC_MAX_LSB 0
\r
810 #define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f
\r
811 #define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
\r
812 #define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
\r
813 #define CPU_PLL_DITHER_NFRAC_MAX_RESET 60
\r
814 #define CPU_PLL_DITHER_ADDRESS 0x0048
\r
815 #define CPU_PLL_DITHER_OFFSET 0x0048
\r
816 // SW modifiable bits
\r
817 #define CPU_PLL_DITHER_SW_MASK 0x80ffffff
\r
818 // bits defined at reset
\r
819 #define CPU_PLL_DITHER_RSTMASK 0xffffffff
\r
820 // reset value (ignore bits undefined at reset)
\r
821 #define CPU_PLL_DITHER_RESET 0x005010fc
\r
823 // 32'h1806001c (RST_RESET)
\r
824 #define RST_RESET_HOST_RESET_MSB 31
\r
825 #define RST_RESET_HOST_RESET_LSB 31
\r
826 #define RST_RESET_HOST_RESET_MASK 0x80000000
\r
827 #define RST_RESET_HOST_RESET_GET(x) (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)
\r
828 #define RST_RESET_HOST_RESET_SET(x) (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)
\r
829 #define RST_RESET_HOST_RESET_RESET 0
\r
830 #define RST_RESET_SLIC_RESET_MSB 30
\r
831 #define RST_RESET_SLIC_RESET_LSB 30
\r
832 #define RST_RESET_SLIC_RESET_MASK 0x40000000
\r
833 #define RST_RESET_SLIC_RESET_GET(x) (((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB)
\r
834 #define RST_RESET_SLIC_RESET_SET(x) (((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK)
\r
835 #define RST_RESET_SLIC_RESET_RESET 0
\r
836 #define RST_RESET_HDMA_RESET_MSB 29
\r
837 #define RST_RESET_HDMA_RESET_LSB 29
\r
838 #define RST_RESET_HDMA_RESET_MASK 0x20000000
\r
839 #define RST_RESET_HDMA_RESET_GET(x) (((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB)
\r
840 #define RST_RESET_HDMA_RESET_SET(x) (((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK)
\r
841 #define RST_RESET_HDMA_RESET_RESET 1
\r
842 #define RST_RESET_EXTERNAL_RESET_MSB 28
\r
843 #define RST_RESET_EXTERNAL_RESET_LSB 28
\r
844 #define RST_RESET_EXTERNAL_RESET_MASK 0x10000000
\r
845 #define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
\r
846 #define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
\r
847 #define RST_RESET_EXTERNAL_RESET_RESET 0
\r
848 #define RST_RESET_RTC_RESET_MSB 27
\r
849 #define RST_RESET_RTC_RESET_LSB 27
\r
850 #define RST_RESET_RTC_RESET_MASK 0x08000000
\r
851 #define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
\r
852 #define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
\r
853 #define RST_RESET_RTC_RESET_RESET 1
\r
854 #define RST_RESET_PCIEEP_RST_INT_MSB 26
\r
855 #define RST_RESET_PCIEEP_RST_INT_LSB 26
\r
856 #define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000
\r
857 #define RST_RESET_PCIEEP_RST_INT_GET(x) (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)
\r
858 #define RST_RESET_PCIEEP_RST_INT_SET(x) (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)
\r
859 #define RST_RESET_PCIEEP_RST_INT_RESET 0
\r
860 #define RST_RESET_CHKSUM_ACC_RESET_MSB 25
\r
861 #define RST_RESET_CHKSUM_ACC_RESET_LSB 25
\r
862 #define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000
\r
863 #define RST_RESET_CHKSUM_ACC_RESET_GET(x) (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB)
\r
864 #define RST_RESET_CHKSUM_ACC_RESET_SET(x) (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK)
\r
865 #define RST_RESET_CHKSUM_ACC_RESET_RESET 0
\r
866 #define RST_RESET_FULL_CHIP_RESET_MSB 24
\r
867 #define RST_RESET_FULL_CHIP_RESET_LSB 24
\r
868 #define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000
\r
869 #define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)
\r
870 #define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)
\r
871 #define RST_RESET_FULL_CHIP_RESET_RESET 0
\r
872 #define RST_RESET_GE1_MDIO_RESET_MSB 23
\r
873 #define RST_RESET_GE1_MDIO_RESET_LSB 23
\r
874 #define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000
\r
875 #define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
\r
876 #define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
\r
877 #define RST_RESET_GE1_MDIO_RESET_RESET 1
\r
878 #define RST_RESET_GE0_MDIO_RESET_MSB 22
\r
879 #define RST_RESET_GE0_MDIO_RESET_LSB 22
\r
880 #define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000
\r
881 #define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
\r
882 #define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
\r
883 #define RST_RESET_GE0_MDIO_RESET_RESET 1
\r
884 #define RST_RESET_CPU_NMI_MSB 21
\r
885 #define RST_RESET_CPU_NMI_LSB 21
\r
886 #define RST_RESET_CPU_NMI_MASK 0x00200000
\r
887 #define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
\r
888 #define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
\r
889 #define RST_RESET_CPU_NMI_RESET 0
\r
890 #define RST_RESET_CPU_COLD_RESET_MSB 20
\r
891 #define RST_RESET_CPU_COLD_RESET_LSB 20
\r
892 #define RST_RESET_CPU_COLD_RESET_MASK 0x00100000
\r
893 #define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
\r
894 #define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
\r
895 #define RST_RESET_CPU_COLD_RESET_RESET 0
\r
896 #define RST_RESET_HOST_RESET_INT_MSB 19
\r
897 #define RST_RESET_HOST_RESET_INT_LSB 19
\r
898 #define RST_RESET_HOST_RESET_INT_MASK 0x00080000
\r
899 #define RST_RESET_HOST_RESET_INT_GET(x) (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)
\r
900 #define RST_RESET_HOST_RESET_INT_SET(x) (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)
\r
901 #define RST_RESET_HOST_RESET_INT_RESET 0
\r
902 #define RST_RESET_PCIEEP_RESET_MSB 18
\r
903 #define RST_RESET_PCIEEP_RESET_LSB 18
\r
904 #define RST_RESET_PCIEEP_RESET_MASK 0x00040000
\r
905 #define RST_RESET_PCIEEP_RESET_GET(x) (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)
\r
906 #define RST_RESET_PCIEEP_RESET_SET(x) (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)
\r
907 #define RST_RESET_PCIEEP_RESET_RESET 0
\r
908 #define RST_RESET_UART1_RESET_MSB 17
\r
909 #define RST_RESET_UART1_RESET_LSB 17
\r
910 #define RST_RESET_UART1_RESET_MASK 0x00020000
\r
911 #define RST_RESET_UART1_RESET_GET(x) (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)
\r
912 #define RST_RESET_UART1_RESET_SET(x) (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)
\r
913 #define RST_RESET_UART1_RESET_RESET 0
\r
914 #define RST_RESET_DDR_RESET_MSB 16
\r
915 #define RST_RESET_DDR_RESET_LSB 16
\r
916 #define RST_RESET_DDR_RESET_MASK 0x00010000
\r
917 #define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
\r
918 #define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
\r
919 #define RST_RESET_DDR_RESET_RESET 0
\r
920 #define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15
\r
921 #define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15
\r
922 #define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000
\r
923 #define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
\r
924 #define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
\r
925 #define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0
\r
926 #define RST_RESET_NANDF_RESET_MSB 14
\r
927 #define RST_RESET_NANDF_RESET_LSB 14
\r
928 #define RST_RESET_NANDF_RESET_MASK 0x00004000
\r
929 #define RST_RESET_NANDF_RESET_GET(x) (((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB)
\r
930 #define RST_RESET_NANDF_RESET_SET(x) (((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK)
\r
931 #define RST_RESET_NANDF_RESET_RESET 1
\r
932 #define RST_RESET_GE1_MAC_RESET_MSB 13
\r
933 #define RST_RESET_GE1_MAC_RESET_LSB 13
\r
934 #define RST_RESET_GE1_MAC_RESET_MASK 0x00002000
\r
935 #define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
\r
936 #define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
\r
937 #define RST_RESET_GE1_MAC_RESET_RESET 1
\r
938 #define RST_RESET_ETH_SWITCH_ARESET_MSB 12
\r
939 #define RST_RESET_ETH_SWITCH_ARESET_LSB 12
\r
940 #define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000
\r
941 #define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB)
\r
942 #define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK)
\r
943 #define RST_RESET_ETH_SWITCH_ARESET_RESET 1
\r
944 #define RST_RESET_USB_PHY_ARESET_MSB 11
\r
945 #define RST_RESET_USB_PHY_ARESET_LSB 11
\r
946 #define RST_RESET_USB_PHY_ARESET_MASK 0x00000800
\r
947 #define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
\r
948 #define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
\r
949 #define RST_RESET_USB_PHY_ARESET_RESET 1
\r
950 #define RST_RESET_RESERVED_MSB 10
\r
951 #define RST_RESET_RESERVED_LSB 10
\r
952 #define RST_RESET_RESERVED_MASK 0x00000400
\r
953 #define RST_RESET_RESERVED_GET(x) (((x) & RST_RESET_RESERVED_MASK) >> RST_RESET_RESERVED_LSB)
\r
954 #define RST_RESET_RESERVED_SET(x) (((x) << RST_RESET_RESERVED_LSB) & RST_RESET_RESERVED_MASK)
\r
955 #define RST_RESET_RESERVED_RESET 1
\r
956 #define RST_RESET_GE0_MAC_RESET_MSB 9
\r
957 #define RST_RESET_GE0_MAC_RESET_LSB 9
\r
958 #define RST_RESET_GE0_MAC_RESET_MASK 0x00000200
\r
959 #define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
\r
960 #define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
\r
961 #define RST_RESET_GE0_MAC_RESET_RESET 1
\r
962 #define RST_RESET_ETH_SWITCH_RESET_MSB 8
\r
963 #define RST_RESET_ETH_SWITCH_RESET_LSB 8
\r
964 #define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100
\r
965 #define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB)
\r
966 #define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK)
\r
967 #define RST_RESET_ETH_SWITCH_RESET_RESET 1
\r
968 #define RST_RESET_PCIE_PHY_RESET_MSB 7
\r
969 #define RST_RESET_PCIE_PHY_RESET_LSB 7
\r
970 #define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080
\r
971 #define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
\r
972 #define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
\r
973 #define RST_RESET_PCIE_PHY_RESET_RESET 1
\r
974 #define RST_RESET_PCIE_RESET_MSB 6
\r
975 #define RST_RESET_PCIE_RESET_LSB 6
\r
976 #define RST_RESET_PCIE_RESET_MASK 0x00000040
\r
977 #define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
\r
978 #define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
\r
979 #define RST_RESET_PCIE_RESET_RESET 1
\r
980 #define RST_RESET_USB_HOST_RESET_MSB 5
\r
981 #define RST_RESET_USB_HOST_RESET_LSB 5
\r
982 #define RST_RESET_USB_HOST_RESET_MASK 0x00000020
\r
983 #define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
\r
984 #define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
\r
985 #define RST_RESET_USB_HOST_RESET_RESET 1
\r
986 #define RST_RESET_USB_PHY_RESET_MSB 4
\r
987 #define RST_RESET_USB_PHY_RESET_LSB 4
\r
988 #define RST_RESET_USB_PHY_RESET_MASK 0x00000010
\r
989 #define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
\r
990 #define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
\r
991 #define RST_RESET_USB_PHY_RESET_RESET 1
\r
992 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3
\r
993 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3
\r
994 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008
\r
995 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
\r
996 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
\r
997 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0
\r
998 #define RST_RESET_LUT_RESET_MSB 2
\r
999 #define RST_RESET_LUT_RESET_LSB 2
\r
1000 #define RST_RESET_LUT_RESET_MASK 0x00000004
\r
1001 #define RST_RESET_LUT_RESET_GET(x) (((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB)
\r
1002 #define RST_RESET_LUT_RESET_SET(x) (((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK)
\r
1003 #define RST_RESET_LUT_RESET_RESET 0
\r
1004 #define RST_RESET_MBOX_RESET_MSB 1
\r
1005 #define RST_RESET_MBOX_RESET_LSB 1
\r
1006 #define RST_RESET_MBOX_RESET_MASK 0x00000002
\r
1007 #define RST_RESET_MBOX_RESET_GET(x) (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)
\r
1008 #define RST_RESET_MBOX_RESET_SET(x) (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)
\r
1009 #define RST_RESET_MBOX_RESET_RESET 0
\r
1010 #define RST_RESET_I2S_RESET_MSB 0
\r
1011 #define RST_RESET_I2S_RESET_LSB 0
\r
1012 #define RST_RESET_I2S_RESET_MASK 0x00000001
\r
1013 #define RST_RESET_I2S_RESET_GET(x) (((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB)
\r
1014 #define RST_RESET_I2S_RESET_SET(x) (((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK)
\r
1015 #define RST_RESET_I2S_RESET_RESET 0
\r
1016 #define RST_RESET_ADDRESS 0x1806001c
\r
1017 #define RST_RESET_OFFSET 0x001c
\r
1018 // SW modifiable bits
\r
1019 #define RST_RESET_SW_MASK 0xffffffff
\r
1020 // bits defined at reset
\r
1021 #define RST_RESET_RSTMASK 0xffffffff
\r
1022 // reset value (ignore bits undefined at reset)
\r
1023 #define RST_RESET_RESET 0x28c07ff0
\r
1025 #define RST_MISC2_SPARE_MSB 31
\r
1026 #define RST_MISC2_SPARE_LSB 26
\r
1027 #define RST_MISC2_SPARE_MASK 0xfc000000
\r
1028 #define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB)
\r
1029 #define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK)
\r
1030 #define RST_MISC2_SPARE_RESET 0x0 // 0
\r
1031 #define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB 25
\r
1032 #define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB 25
\r
1033 #define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK 0x02000000
\r
1034 #define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB)
\r
1035 #define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK)
\r
1036 #define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET 0x0 // 0
\r
1037 #define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB 24
\r
1038 #define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB 24
\r
1039 #define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK 0x01000000
\r
1040 #define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB)
\r
1041 #define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK)
\r
1042 #define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET 0x0 // 0
\r
1043 #define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB 23
\r
1044 #define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB 23
\r
1045 #define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK 0x00800000
\r
1046 #define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB)
\r
1047 #define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK)
\r
1048 #define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET 0x0 // 0
\r
1049 #define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB 22
\r
1050 #define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB 22
\r
1051 #define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK 0x00400000
\r
1052 #define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB)
\r
1053 #define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK)
\r
1054 #define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET 0x0 // 0
\r
1055 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB 21
\r
1056 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB 21
\r
1057 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK 0x00200000
\r
1058 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB)
\r
1059 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK)
\r
1060 #define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET 0x0 // 0
\r
1061 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB 20
\r
1062 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB 20
\r
1063 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK 0x00100000
\r
1064 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB)
\r
1065 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK)
\r
1066 #define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET 0x0 // 0
\r
1067 #define RST_MISC2_PCIEEP_REGWR_EN_MSB 19
\r
1068 #define RST_MISC2_PCIEEP_REGWR_EN_LSB 19
\r
1069 #define RST_MISC2_PCIEEP_REGWR_EN_MASK 0x00080000
\r
1070 #define RST_MISC2_PCIEEP_REGWR_EN_GET(x) (((x) & RST_MISC2_PCIEEP_REGWR_EN_MASK) >> RST_MISC2_PCIEEP_REGWR_EN_LSB)
\r
1071 #define RST_MISC2_PCIEEP_REGWR_EN_SET(x) (((x) << RST_MISC2_PCIEEP_REGWR_EN_LSB) & RST_MISC2_PCIEEP_REGWR_EN_MASK)
\r
1072 #define RST_MISC2_PCIEEP_REGWR_EN_RESET 0x1 // 1
\r
1073 #define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18
\r
1074 #define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18
\r
1075 #define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000
\r
1076 #define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)
\r
1077 #define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)
\r
1078 #define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0
\r
1079 #define RST_MISC2_PCIEEP_RST_INT_MASK_MSB 17
\r
1080 #define RST_MISC2_PCIEEP_RST_INT_MASK_LSB 17
\r
1081 #define RST_MISC2_PCIEEP_RST_INT_MASK_MASK 0x00020000
\r
1082 #define RST_MISC2_PCIEEP_RST_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_RST_INT_MASK_MASK) >> RST_MISC2_PCIEEP_RST_INT_MASK_LSB)
\r
1083 #define RST_MISC2_PCIEEP_RST_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_RST_INT_MASK_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK_MASK)
\r
1084 #define RST_MISC2_PCIEEP_RST_INT_MASK_RESET 0x0 // 0
\r
1085 #define RST_MISC2_HOST_RESET_INT_MASK_MSB 16
\r
1086 #define RST_MISC2_HOST_RESET_INT_MASK_LSB 16
\r
1087 #define RST_MISC2_HOST_RESET_INT_MASK_MASK 0x00010000
\r
1088 #define RST_MISC2_HOST_RESET_INT_MASK_GET(x) (((x) & RST_MISC2_HOST_RESET_INT_MASK_MASK) >> RST_MISC2_HOST_RESET_INT_MASK_LSB)
\r
1089 #define RST_MISC2_HOST_RESET_INT_MASK_SET(x) (((x) << RST_MISC2_HOST_RESET_INT_MASK_LSB) & RST_MISC2_HOST_RESET_INT_MASK_MASK)
\r
1090 #define RST_MISC2_HOST_RESET_INT_MASK_RESET 0x0 // 0
\r
1091 #define RST_MISC2_CPU_HOST_WA_MSB 15
\r
1092 #define RST_MISC2_CPU_HOST_WA_LSB 15
\r
1093 #define RST_MISC2_CPU_HOST_WA_MASK 0x00008000
\r
1094 #define RST_MISC2_CPU_HOST_WA_GET(x) (((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB)
\r
1095 #define RST_MISC2_CPU_HOST_WA_SET(x) (((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK)
\r
1096 #define RST_MISC2_CPU_HOST_WA_RESET 0x0 // 0
\r
1097 #define RST_MISC2_PERSTN_EPPHY_MSB 14
\r
1098 #define RST_MISC2_PERSTN_EPPHY_LSB 14
\r
1099 #define RST_MISC2_PERSTN_EPPHY_MASK 0x00004000
\r
1100 #define RST_MISC2_PERSTN_EPPHY_GET(x) (((x) & RST_MISC2_PERSTN_EPPHY_MASK) >> RST_MISC2_PERSTN_EPPHY_LSB)
\r
1101 #define RST_MISC2_PERSTN_EPPHY_SET(x) (((x) << RST_MISC2_PERSTN_EPPHY_LSB) & RST_MISC2_PERSTN_EPPHY_MASK)
\r
1102 #define RST_MISC2_PERSTN_EPPHY_RESET 0x1 // 1
\r
1103 #define RST_MISC2_PERSTN_RCPHY_MSB 13
\r
1104 #define RST_MISC2_PERSTN_RCPHY_LSB 13
\r
1105 #define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000
\r
1106 #define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)
\r
1107 #define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)
\r
1108 #define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1
\r
1109 #define RST_MISC2_PCIEEP_LTSSM_STATE_MSB 12
\r
1110 #define RST_MISC2_PCIEEP_LTSSM_STATE_LSB 8
\r
1111 #define RST_MISC2_PCIEEP_LTSSM_STATE_MASK 0x00001f00
\r
1112 #define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x) (((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB)
\r
1113 #define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x) (((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK)
\r
1114 #define RST_MISC2_PCIEEP_LTSSM_STATE_RESET 0x0 // 0
\r
1115 #define RST_MISC2_PCIEEP_L2_INT_MASK_MSB 7
\r
1116 #define RST_MISC2_PCIEEP_L2_INT_MASK_LSB 7
\r
1117 #define RST_MISC2_PCIEEP_L2_INT_MASK_MASK 0x00000080
\r
1118 #define RST_MISC2_PCIEEP_L2_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L2_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L2_INT_MASK_LSB)
\r
1119 #define RST_MISC2_PCIEEP_L2_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L2_INT_MASK_LSB) & RST_MISC2_PCIEEP_L2_INT_MASK_MASK)
\r
1120 #define RST_MISC2_PCIEEP_L2_INT_MASK_RESET 0x0 // 0
\r
1121 #define RST_MISC2_PCIEEP_L1_INT_MASK_MSB 6
\r
1122 #define RST_MISC2_PCIEEP_L1_INT_MASK_LSB 6
\r
1123 #define RST_MISC2_PCIEEP_L1_INT_MASK_MASK 0x00000040
\r
1124 #define RST_MISC2_PCIEEP_L1_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L1_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L1_INT_MASK_LSB)
\r
1125 #define RST_MISC2_PCIEEP_L1_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L1_INT_MASK_LSB) & RST_MISC2_PCIEEP_L1_INT_MASK_MASK)
\r
1126 #define RST_MISC2_PCIEEP_L1_INT_MASK_RESET 0x0 // 0
\r
1127 #define RST_MISC2_PCIEEP_L0S_INT_MASK_MSB 5
\r
1128 #define RST_MISC2_PCIEEP_L0S_INT_MASK_LSB 5
\r
1129 #define RST_MISC2_PCIEEP_L0S_INT_MASK_MASK 0x00000020
\r
1130 #define RST_MISC2_PCIEEP_L0S_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L0S_INT_MASK_LSB)
\r
1131 #define RST_MISC2_PCIEEP_L0S_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_INT_MASK_LSB) & RST_MISC2_PCIEEP_L0S_INT_MASK_MASK)
\r
1132 #define RST_MISC2_PCIEEP_L0S_INT_MASK_RESET 0x0 // 0
\r
1133 #define RST_MISC2_PCIEEP_LINK_STATUS_MSB 4
\r
1134 #define RST_MISC2_PCIEEP_LINK_STATUS_LSB 4
\r
1135 #define RST_MISC2_PCIEEP_LINK_STATUS_MASK 0x00000010
\r
1136 #define RST_MISC2_PCIEEP_LINK_STATUS_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB)
\r
1137 #define RST_MISC2_PCIEEP_LINK_STATUS_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK)
\r
1138 #define RST_MISC2_PCIEEP_LINK_STATUS_RESET 0x0 // 0
\r
1139 #define RST_MISC2_RESERVED_MSB 3
\r
1140 #define RST_MISC2_RESERVED_LSB 1
\r
1141 #define RST_MISC2_RESERVED_MASK 0x0000000e
\r
1142 #define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB)
\r
1143 #define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK)
\r
1144 #define RST_MISC2_RESERVED_RESET 0x0 // 0
\r
1145 #define RST_MISC2_PCIEEP_CFG_DONE_MSB 0
\r
1146 #define RST_MISC2_PCIEEP_CFG_DONE_LSB 0
\r
1147 #define RST_MISC2_PCIEEP_CFG_DONE_MASK 0x00000001
\r
1148 #define RST_MISC2_PCIEEP_CFG_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB)
\r
1149 #define RST_MISC2_PCIEEP_CFG_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK)
\r
1150 #define RST_MISC2_PCIEEP_CFG_DONE_RESET 0x0 // 0
\r
1151 #define RST_MISC2_ADDRESS 0x180600bc
\r
1153 #define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
\r
1154 #define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
\r
1155 #define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
\r
1156 #define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
\r
1157 #define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
\r
1158 //#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 1'd0
\r
1159 #define DDR_CONFIG_OPEN_PAGE_MSB 30
\r
1160 #define DDR_CONFIG_OPEN_PAGE_LSB 30
\r
1161 #define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
\r
1162 #define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
\r
1163 #define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
\r
1164 //#define DDR_CONFIG_OPEN_PAGE_RESET 1'd1
\r
1165 #define DDR_CONFIG_CAS_LATENCY_MSB 29
\r
1166 #define DDR_CONFIG_CAS_LATENCY_LSB 27
\r
1167 #define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
\r
1168 #define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
\r
1169 #define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
\r
1170 //#define DDR_CONFIG_CAS_LATENCY_RESET 3'd6
\r
1171 #define DDR_CONFIG_TMRD_MSB 26
\r
1172 #define DDR_CONFIG_TMRD_LSB 23
\r
1173 #define DDR_CONFIG_TMRD_MASK 0x07800000
\r
1174 #define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
\r
1175 #define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
\r
1176 //#define DDR_CONFIG_TMRD_RESET 4'd15
\r
1177 #define DDR_CONFIG_TRFC_MSB 22
\r
1178 #define DDR_CONFIG_TRFC_LSB 17
\r
1179 #define DDR_CONFIG_TRFC_MASK 0x007e0000
\r
1180 #define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
\r
1181 #define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
\r
1182 //#define DDR_CONFIG_TRFC_RESET 6'd31
\r
1183 #define DDR_CONFIG_TRRD_MSB 16
\r
1184 #define DDR_CONFIG_TRRD_LSB 13
\r
1185 #define DDR_CONFIG_TRRD_MASK 0x0001e000
\r
1186 #define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
\r
1187 #define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
\r
1188 //#define DDR_CONFIG_TRRD_RESET 4'd4
\r
1189 #define DDR_CONFIG_TRP_MSB 12
\r
1190 #define DDR_CONFIG_TRP_LSB 9
\r
1191 #define DDR_CONFIG_TRP_MASK 0x00001e00
\r
1192 #define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
\r
1193 #define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
\r
1194 //#define DDR_CONFIG_TRP_RESET 4'd6
\r
1195 #define DDR_CONFIG_TRCD_MSB 8
\r
1196 #define DDR_CONFIG_TRCD_LSB 5
\r
1197 #define DDR_CONFIG_TRCD_MASK 0x000001e0
\r
1198 #define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
\r
1199 #define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
\r
1200 //#define DDR_CONFIG_TRCD_RESET 4'd6
\r
1201 #define DDR_CONFIG_TRAS_MSB 4
\r
1202 #define DDR_CONFIG_TRAS_LSB 0
\r
1203 #define DDR_CONFIG_TRAS_MASK 0x0000001f
\r
1204 #define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
\r
1205 #define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
\r
1206 //#define DDR_CONFIG_TRAS_RESET 5'd16
\r
1207 #define DDR_CONFIG_ADDRESS 0x18000000
\r
1209 // 32'h18000004 (DDR_CONFIG2)
\r
1210 #define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
\r
1211 #define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
\r
1212 #define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
\r
1213 #define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
\r
1214 #define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
\r
1215 //#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 1'd1
\r
1216 #define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
\r
1217 #define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
\r
1218 #define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
\r
1219 #define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
\r
1220 #define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
\r
1221 //#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 4'd6
\r
1222 #define DDR_CONFIG2_TWTR_MSB 25
\r
1223 #define DDR_CONFIG2_TWTR_LSB 21
\r
1224 #define DDR_CONFIG2_TWTR_MASK 0x03e00000
\r
1225 #define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
\r
1226 #define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
\r
1227 //#define DDR_CONFIG2_TWTR_RESET 5'd14
\r
1228 #define DDR_CONFIG2_TRTP_MSB 20
\r
1229 #define DDR_CONFIG2_TRTP_LSB 17
\r
1230 #define DDR_CONFIG2_TRTP_MASK 0x001e0000
\r
1231 #define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
\r
1232 #define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
\r
1233 //#define DDR_CONFIG2_TRTP_RESET 4'd8
\r
1234 #define DDR_CONFIG2_TRTW_MSB 16
\r
1235 #define DDR_CONFIG2_TRTW_LSB 12
\r
1236 #define DDR_CONFIG2_TRTW_MASK 0x0001f000
\r
1237 #define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
\r
1238 #define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
\r
1239 //#define DDR_CONFIG2_TRTW_RESET 5'd16
\r
1240 #define DDR_CONFIG2_TWR_MSB 11
\r
1241 #define DDR_CONFIG2_TWR_LSB 8
\r
1242 #define DDR_CONFIG2_TWR_MASK 0x00000f00
\r
1243 #define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
\r
1244 #define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
\r
1245 //#define DDR_CONFIG2_TWR_RESET 4'd6
\r
1246 #define DDR_CONFIG2_CKE_MSB 7
\r
1247 #define DDR_CONFIG2_CKE_LSB 7
\r
1248 #define DDR_CONFIG2_CKE_MASK 0x00000080
\r
1249 #define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
\r
1250 #define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
\r
1251 //#define DDR_CONFIG2_CKE_RESET 1'd0
\r
1252 #define DDR_CONFIG2_PHASE_SELECT_MSB 6
\r
1253 #define DDR_CONFIG2_PHASE_SELECT_LSB 6
\r
1254 #define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
\r
1255 #define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
\r
1256 #define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
\r
1257 //#define DDR_CONFIG2_PHASE_SELECT_RESET 1'd0
\r
1258 #define DDR_CONFIG2_CNTL_OE_EN_MSB 5
\r
1259 #define DDR_CONFIG2_CNTL_OE_EN_LSB 5
\r
1260 #define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
\r
1261 #define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
\r
1262 #define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
\r
1263 //#define DDR_CONFIG2_CNTL_OE_EN_RESET 1'd1
\r
1264 #define DDR_CONFIG2_BURST_TYPE_MSB 4
\r
1265 #define DDR_CONFIG2_BURST_TYPE_LSB 4
\r
1266 #define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
\r
1267 #define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
\r
1268 #define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
\r
1269 //#define DDR_CONFIG2_BURST_TYPE_RESET 1'd0
\r
1270 #define DDR_CONFIG2_BURST_LENGTH_MSB 3
\r
1271 #define DDR_CONFIG2_BURST_LENGTH_LSB 0
\r
1272 #define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
\r
1273 #define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
\r
1274 #define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
\r
1275 //#define DDR_CONFIG2_BURST_LENGTH_RESET 4'd8
\r
1276 #define DDR_CONFIG2_ADDRESS 0x18000004
\r
1279 #define DDR2_CONFIG_DDR2_TWL_MSB 13
\r
1280 #define DDR2_CONFIG_DDR2_TWL_LSB 10
\r
1281 #define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
\r
1282 #define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
\r
1283 #define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
\r
1284 //#define DDR2_CONFIG_DDR2_TWL_RESET 4'd1
\r
1285 #define DDR2_CONFIG_DDR2_ODT_MSB 9
\r
1286 #define DDR2_CONFIG_DDR2_ODT_LSB 9
\r
1287 #define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
\r
1288 #define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
\r
1289 #define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
\r
1290 //#define DDR2_CONFIG_DDR2_ODT_RESET 1'd1
\r
1291 #define DDR2_CONFIG_TFAW_MSB 7
\r
1292 #define DDR2_CONFIG_TFAW_LSB 2
\r
1293 #define DDR2_CONFIG_TFAW_MASK 0x000000fc
\r
1294 #define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
\r
1295 #define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
\r
1296 //#define DDR2_CONFIG_TFAW_RESET 6'd22
\r
1297 #define DDR2_CONFIG_ENABLE_DDR2_MSB 0
\r
1298 #define DDR2_CONFIG_ENABLE_DDR2_LSB 0
\r
1299 #define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
\r
1300 #define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
\r
1301 #define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
\r
1302 //#define DDR2_CONFIG_ENABLE_DDR2_RESET 1'd0
\r
1303 #define DDR2_CONFIG_ADDRESS 0x180000b8
\r
1305 #define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
\r
1306 #define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
\r
1307 #define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
\r
1308 #define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
\r
1309 #define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
\r
1310 #define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1
\r
1311 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
\r
1312 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
\r
1313 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
\r
1314 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
\r
1315 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
\r
1316 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0
\r
1317 #define DDR_CTL_CONFIG_SPARE_MSB 20
\r
1318 #define DDR_CTL_CONFIG_SPARE_LSB 6
\r
1319 #define DDR_CTL_CONFIG_SPARE_MASK 0x001fffc0
\r
1320 #define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
\r
1321 #define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
\r
1322 #define DDR_CTL_CONFIG_SPARE_RESET 0x4 // 4
\r
1323 #define DDR_CTL_CONFIG_PREFETCH_CNT_MSB 5
\r
1324 #define DDR_CTL_CONFIG_PREFETCH_CNT_LSB 2
\r
1325 #define DDR_CTL_CONFIG_PREFETCH_CNT_MASK 0x0000003c
\r
1326 #define DDR_CTL_CONFIG_PREFETCH_CNT_GET(x) (((x) & DDR_CTL_CONFIG_PREFETCH_CNT_MASK) >> DDR_CTL_CONFIG_PREFETCH_CNT_LSB)
\r
1327 #define DDR_CTL_CONFIG_PREFETCH_CNT_SET(x) (((x) << DDR_CTL_CONFIG_PREFETCH_CNT_LSB) & DDR_CTL_CONFIG_PREFETCH_CNT_MASK)
\r
1328 #define DDR_CTL_CONFIG_PREFETCH_CNT_RESET 0x3 // 3
\r
1329 #define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
\r
1330 #define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
\r
1331 #define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
\r
1332 #define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
\r
1333 #define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
\r
1334 #define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1
\r
1335 #define DDR_CTL_CONFIG_SRAM_MODE_EN_MSB 0
\r
1336 #define DDR_CTL_CONFIG_SRAM_MODE_EN_LSB 0
\r
1337 #define DDR_CTL_CONFIG_SRAM_MODE_EN_MASK 0x00000001
\r
1338 #define DDR_CTL_CONFIG_SRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SRAM_MODE_EN_LSB)
\r
1339 #define DDR_CTL_CONFIG_SRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SRAM_MODE_EN_MASK)
\r
1340 #define DDR_CTL_CONFIG_SRAM_MODE_EN_RESET 0x0 // 0
\r
1341 #define DDR_CTL_CONFIG_ADDRESS 0x18000108
\r
1344 #define CPU_DPLL3_MEAS_AT_TXON_MSB 31
\r
1345 #define CPU_DPLL3_MEAS_AT_TXON_LSB 31
\r
1346 #define CPU_DPLL3_MEAS_AT_TXON_MASK 0x80000000
\r
1347 #define CPU_DPLL3_MEAS_AT_TXON_GET(x) (((x) & CPU_DPLL3_MEAS_AT_TXON_MASK) >> CPU_DPLL3_MEAS_AT_TXON_LSB)
\r
1348 #define CPU_DPLL3_MEAS_AT_TXON_SET(x) (((x) << CPU_DPLL3_MEAS_AT_TXON_LSB) & CPU_DPLL3_MEAS_AT_TXON_MASK)
\r
1349 #define CPU_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0
\r
1350 #define CPU_DPLL3_DO_MEAS_MSB 30
\r
1351 #define CPU_DPLL3_DO_MEAS_LSB 30
\r
1352 #define CPU_DPLL3_DO_MEAS_MASK 0x40000000
\r
1353 #define CPU_DPLL3_DO_MEAS_GET(x) (((x) & CPU_DPLL3_DO_MEAS_MASK) >> CPU_DPLL3_DO_MEAS_LSB)
\r
1354 #define CPU_DPLL3_DO_MEAS_SET(x) (((x) << CPU_DPLL3_DO_MEAS_LSB) & CPU_DPLL3_DO_MEAS_MASK)
\r
1355 #define CPU_DPLL3_DO_MEAS_RESET 0x0 // 0
\r
1356 #define CPU_DPLL3_PHASE_SHIFT_MSB 29
\r
1357 #define CPU_DPLL3_PHASE_SHIFT_LSB 23
\r
1358 #define CPU_DPLL3_PHASE_SHIFT_MASK 0x3f800000
\r
1359 #define CPU_DPLL3_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL3_PHASE_SHIFT_MASK) >> CPU_DPLL3_PHASE_SHIFT_LSB)
\r
1360 #define CPU_DPLL3_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL3_PHASE_SHIFT_LSB) & CPU_DPLL3_PHASE_SHIFT_MASK)
\r
1361 #define CPU_DPLL3_PHASE_SHIFT_RESET 0x0 // 0
\r
1362 #define CPU_DPLL3_SQSUM_DVC_MSB 22
\r
1363 #define CPU_DPLL3_SQSUM_DVC_LSB 3
\r
1364 #define CPU_DPLL3_SQSUM_DVC_MASK 0x007ffff8
\r
1365 #define CPU_DPLL3_SQSUM_DVC_GET(x) (((x) & CPU_DPLL3_SQSUM_DVC_MASK) >> CPU_DPLL3_SQSUM_DVC_LSB)
\r
1366 #define CPU_DPLL3_SQSUM_DVC_SET(x) (((x) << CPU_DPLL3_SQSUM_DVC_LSB) & CPU_DPLL3_SQSUM_DVC_MASK)
\r
1367 #define CPU_DPLL3_SQSUM_DVC_RESET 0x0 // 0
\r
1368 #define CPU_DPLL3_SPARE_MSB 2
\r
1369 #define CPU_DPLL3_SPARE_LSB 0
\r
1370 #define CPU_DPLL3_SPARE_MASK 0x00000007
\r
1371 #define CPU_DPLL3_SPARE_GET(x) (((x) & CPU_DPLL3_SPARE_MASK) >> CPU_DPLL3_SPARE_LSB)
\r
1372 #define CPU_DPLL3_SPARE_SET(x) (((x) << CPU_DPLL3_SPARE_LSB) & CPU_DPLL3_SPARE_MASK)
\r
1373 #define CPU_DPLL3_SPARE_RESET 0x0 // 0
\r
1374 #define CPU_DPLL3_ADDRESS 0x181161c8
\r
1375 #define CPU_DPLL4_MEAN_DVC_MSB 31
\r
1376 #define CPU_DPLL4_MEAN_DVC_LSB 21
\r
1377 #define CPU_DPLL4_MEAN_DVC_MASK 0xffe00000
\r
1378 #define CPU_DPLL4_MEAN_DVC_GET(x) (((x) & CPU_DPLL4_MEAN_DVC_MASK) >> CPU_DPLL4_MEAN_DVC_LSB)
\r
1379 #define CPU_DPLL4_MEAN_DVC_SET(x) (((x) << CPU_DPLL4_MEAN_DVC_LSB) & CPU_DPLL4_MEAN_DVC_MASK)
\r
1380 #define CPU_DPLL4_MEAN_DVC_RESET 0x0 // 0
\r
1381 #define CPU_DPLL4_VC_MEAS0_MSB 20
\r
1382 #define CPU_DPLL4_VC_MEAS0_LSB 4
\r
1383 #define CPU_DPLL4_VC_MEAS0_MASK 0x001ffff0
\r
1384 #define CPU_DPLL4_VC_MEAS0_GET(x) (((x) & CPU_DPLL4_VC_MEAS0_MASK) >> CPU_DPLL4_VC_MEAS0_LSB)
\r
1385 #define CPU_DPLL4_VC_MEAS0_SET(x) (((x) << CPU_DPLL4_VC_MEAS0_LSB) & CPU_DPLL4_VC_MEAS0_MASK)
\r
1386 #define CPU_DPLL4_VC_MEAS0_RESET 0x0 // 0
\r
1387 #define CPU_DPLL4_MEAS_DONE_MSB 3
\r
1388 #define CPU_DPLL4_MEAS_DONE_LSB 3
\r
1389 #define CPU_DPLL4_MEAS_DONE_MASK 0x00000008
\r
1390 #define CPU_DPLL4_MEAS_DONE_GET(x) (((x) & CPU_DPLL4_MEAS_DONE_MASK) >> CPU_DPLL4_MEAS_DONE_LSB)
\r
1391 #define CPU_DPLL4_MEAS_DONE_SET(x) (((x) << CPU_DPLL4_MEAS_DONE_LSB) & CPU_DPLL4_MEAS_DONE_MASK)
\r
1392 #define CPU_DPLL4_MEAS_DONE_RESET 0x0 // 0
\r
1393 #define CPU_DPLL4_SPARE_MSB 2
\r
1394 #define CPU_DPLL4_SPARE_LSB 0
\r
1395 #define CPU_DPLL4_SPARE_MASK 0x00000007
\r
1396 #define CPU_DPLL4_SPARE_GET(x) (((x) & CPU_DPLL4_SPARE_MASK) >> CPU_DPLL4_SPARE_LSB)
\r
1397 #define CPU_DPLL4_SPARE_SET(x) (((x) << CPU_DPLL4_SPARE_LSB) & CPU_DPLL4_SPARE_MASK)
\r
1398 #define CPU_DPLL4_SPARE_RESET 0x0 // 0
\r
1399 #define CPU_DPLL4_ADDRESS 0x181161cc
\r
1401 #define DDR_DPLL3_MEAS_AT_TXON_MSB 31
\r
1402 #define DDR_DPLL3_MEAS_AT_TXON_LSB 31
\r
1403 #define DDR_DPLL3_MEAS_AT_TXON_MASK 0x80000000
\r
1404 #define DDR_DPLL3_MEAS_AT_TXON_GET(x) (((x) & DDR_DPLL3_MEAS_AT_TXON_MASK) >> DDR_DPLL3_MEAS_AT_TXON_LSB)
\r
1405 #define DDR_DPLL3_MEAS_AT_TXON_SET(x) (((x) << DDR_DPLL3_MEAS_AT_TXON_LSB) & DDR_DPLL3_MEAS_AT_TXON_MASK)
\r
1406 #define DDR_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0
\r
1407 #define DDR_DPLL3_DO_MEAS_MSB 30
\r
1408 #define DDR_DPLL3_DO_MEAS_LSB 30
\r
1409 #define DDR_DPLL3_DO_MEAS_MASK 0x40000000
\r
1410 #define DDR_DPLL3_DO_MEAS_GET(x) (((x) & DDR_DPLL3_DO_MEAS_MASK) >> DDR_DPLL3_DO_MEAS_LSB)
\r
1411 #define DDR_DPLL3_DO_MEAS_SET(x) (((x) << DDR_DPLL3_DO_MEAS_LSB) & DDR_DPLL3_DO_MEAS_MASK)
\r
1412 #define DDR_DPLL3_DO_MEAS_RESET 0x0 // 0
\r
1413 #define DDR_DPLL3_PHASE_SHIFT_MSB 29
\r
1414 #define DDR_DPLL3_PHASE_SHIFT_LSB 23
\r
1415 #define DDR_DPLL3_PHASE_SHIFT_MASK 0x3f800000
\r
1416 #define DDR_DPLL3_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL3_PHASE_SHIFT_MASK) >> DDR_DPLL3_PHASE_SHIFT_LSB)
\r
1417 #define DDR_DPLL3_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL3_PHASE_SHIFT_LSB) & DDR_DPLL3_PHASE_SHIFT_MASK)
\r
1418 #define DDR_DPLL3_PHASE_SHIFT_RESET 0x0 // 0
\r
1419 #define DDR_DPLL3_SQSUM_DVC_MSB 22
\r
1420 #define DDR_DPLL3_SQSUM_DVC_LSB 3
\r
1421 #define DDR_DPLL3_SQSUM_DVC_MASK 0x007ffff8
\r
1422 #define DDR_DPLL3_SQSUM_DVC_GET(x) (((x) & DDR_DPLL3_SQSUM_DVC_MASK) >> DDR_DPLL3_SQSUM_DVC_LSB)
\r
1423 #define DDR_DPLL3_SQSUM_DVC_SET(x) (((x) << DDR_DPLL3_SQSUM_DVC_LSB) & DDR_DPLL3_SQSUM_DVC_MASK)
\r
1424 #define DDR_DPLL3_SQSUM_DVC_RESET 0x0 // 0
\r
1425 #define DDR_DPLL3_SPARE_MSB 2
\r
1426 #define DDR_DPLL3_SPARE_LSB 0
\r
1427 #define DDR_DPLL3_SPARE_MASK 0x00000007
\r
1428 #define DDR_DPLL3_SPARE_GET(x) (((x) & DDR_DPLL3_SPARE_MASK) >> DDR_DPLL3_SPARE_LSB)
\r
1429 #define DDR_DPLL3_SPARE_SET(x) (((x) << DDR_DPLL3_SPARE_LSB) & DDR_DPLL3_SPARE_MASK)
\r
1430 #define DDR_DPLL3_SPARE_RESET 0x0 // 0
\r
1431 #define DDR_DPLL3_ADDRESS 0x18116248
\r
1433 // 32'h1811624c (DDR_DPLL4)
\r
1434 #define DDR_DPLL4_MEAN_DVC_MSB 31
\r
1435 #define DDR_DPLL4_MEAN_DVC_LSB 21
\r
1436 #define DDR_DPLL4_MEAN_DVC_MASK 0xffe00000
\r
1437 #define DDR_DPLL4_MEAN_DVC_GET(x) (((x) & DDR_DPLL4_MEAN_DVC_MASK) >> DDR_DPLL4_MEAN_DVC_LSB)
\r
1438 #define DDR_DPLL4_MEAN_DVC_SET(x) (((x) << DDR_DPLL4_MEAN_DVC_LSB) & DDR_DPLL4_MEAN_DVC_MASK)
\r
1439 #define DDR_DPLL4_MEAN_DVC_RESET 0x0 // 0
\r
1440 #define DDR_DPLL4_VC_MEAS0_MSB 20
\r
1441 #define DDR_DPLL4_VC_MEAS0_LSB 4
\r
1442 #define DDR_DPLL4_VC_MEAS0_MASK 0x001ffff0
\r
1443 #define DDR_DPLL4_VC_MEAS0_GET(x) (((x) & DDR_DPLL4_VC_MEAS0_MASK) >> DDR_DPLL4_VC_MEAS0_LSB)
\r
1444 #define DDR_DPLL4_VC_MEAS0_SET(x) (((x) << DDR_DPLL4_VC_MEAS0_LSB) & DDR_DPLL4_VC_MEAS0_MASK)
\r
1445 #define DDR_DPLL4_VC_MEAS0_RESET 0x0 // 0
\r
1446 #define DDR_DPLL4_MEAS_DONE_MSB 3
\r
1447 #define DDR_DPLL4_MEAS_DONE_LSB 3
\r
1448 #define DDR_DPLL4_MEAS_DONE_MASK 0x00000008
\r
1449 #define DDR_DPLL4_MEAS_DONE_GET(x) (((x) & DDR_DPLL4_MEAS_DONE_MASK) >> DDR_DPLL4_MEAS_DONE_LSB)
\r
1450 #define DDR_DPLL4_MEAS_DONE_SET(x) (((x) << DDR_DPLL4_MEAS_DONE_LSB) & DDR_DPLL4_MEAS_DONE_MASK)
\r
1451 #define DDR_DPLL4_MEAS_DONE_RESET 0x0 // 0
\r
1452 #define DDR_DPLL4_SPARE_MSB 2
\r
1453 #define DDR_DPLL4_SPARE_LSB 0
\r
1454 #define DDR_DPLL4_SPARE_MASK 0x00000007
\r
1455 #define DDR_DPLL4_SPARE_GET(x) (((x) & DDR_DPLL4_SPARE_MASK) >> DDR_DPLL4_SPARE_LSB)
\r
1456 #define DDR_DPLL4_SPARE_SET(x) (((x) << DDR_DPLL4_SPARE_LSB) & DDR_DPLL4_SPARE_MASK)
\r
1457 #define DDR_DPLL4_SPARE_RESET 0x0 // 0
\r
1458 #define DDR_DPLL4_ADDRESS 0x1811624c
\r
1460 #define DPLL2_ADDRESS_c4 0x181161c4
\r
1461 #define DPLL3_ADDRESS_c8 CPU_DPLL3_ADDRESS
\r
1462 #define DPLL2_ADDRESS_44 0x18116244
\r
1463 #define DPLL3_ADDRESS_48 DDR_DPLL3_ADDRESS
\r
1464 #define DPLL3_ADDRESS_88 0x18116188
\r
1466 #define PCIe_DPLL_REFDIV_MSB 31
\r
1467 #define PCIe_DPLL_REFDIV_LSB 27
\r
1468 #define PCIe_DPLL_REFDIV_MASK 0xf8000000
\r
1469 #define PCIe_DPLL_REFDIV_GET(x) (((x) & PCIe_DPLL_REFDIV_MASK) >> PCIe_DPLL_REFDIV_LSB)
\r
1470 #define PCIe_DPLL_REFDIV_SET(x) (((x) << PCIe_DPLL_REFDIV_LSB) & PCIe_DPLL_REFDIV_MASK)
\r
1471 #define PCIe_DPLL_REFDIV_RESET 0x1 // 1
\r
1472 #define PCIe_DPLL_NINT_MSB 26
\r
1473 #define PCIe_DPLL_NINT_LSB 18
\r
1474 #define PCIe_DPLL_NINT_MASK 0x07fc0000
\r
1475 #define PCIe_DPLL_NINT_GET(x) (((x) & PCIe_DPLL_NINT_MASK) >> PCIe_DPLL_NINT_LSB)
\r
1476 #define PCIe_DPLL_NINT_SET(x) (((x) << PCIe_DPLL_NINT_LSB) & PCIe_DPLL_NINT_MASK)
\r
1477 #define PCIe_DPLL_NINT_RESET 0x10 // 16
\r
1478 #define PCIe_DPLL_NFRAC_MSB 17
\r
1479 #define PCIe_DPLL_NFRAC_LSB 0
\r
1480 #define PCIe_DPLL_NFRAC_MASK 0x0003ffff
\r
1481 #define PCIe_DPLL_NFRAC_GET(x) (((x) & PCIe_DPLL_NFRAC_MASK) >> PCIe_DPLL_NFRAC_LSB)
\r
1482 #define PCIe_DPLL_NFRAC_SET(x) (((x) << PCIe_DPLL_NFRAC_LSB) & PCIe_DPLL_NFRAC_MASK)
\r
1483 #define PCIe_DPLL_NFRAC_RESET 0x0 // 0
\r
1484 #define PCIe_DPLL_ADDRESS 0x18116c00
\r
1486 // 32'h18116c04 (PCIe_DPLL2)
\r
1487 #define PCIe_DPLL2_RANGE_MSB 31
\r
1488 #define PCIe_DPLL2_RANGE_LSB 31
\r
1489 #define PCIe_DPLL2_RANGE_MASK 0x80000000
\r
1490 #define PCIe_DPLL2_RANGE_GET(x) (((x) & PCIe_DPLL2_RANGE_MASK) >> PCIe_DPLL2_RANGE_LSB)
\r
1491 #define PCIe_DPLL2_RANGE_SET(x) (((x) << PCIe_DPLL2_RANGE_LSB) & PCIe_DPLL2_RANGE_MASK)
\r
1492 #define PCIe_DPLL2_RANGE_RESET 0x0 // 0
\r
1493 #define PCIe_DPLL2_LOCAL_PLL_MSB 30
\r
1494 #define PCIe_DPLL2_LOCAL_PLL_LSB 30
\r
1495 #define PCIe_DPLL2_LOCAL_PLL_MASK 0x40000000
\r
1496 #define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB)
\r
1497 #define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK)
\r
1498 #define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0
\r
1499 #define PCIe_DPLL2_KI_MSB 29
\r
1500 #define PCIe_DPLL2_KI_LSB 26
\r
1501 #define PCIe_DPLL2_KI_MASK 0x3c000000
\r
1502 #define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB)
\r
1503 #define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK)
\r
1504 #define PCIe_DPLL2_KI_RESET 0x6 // 6
\r
1505 #define PCIe_DPLL2_KD_MSB 25
\r
1506 #define PCIe_DPLL2_KD_LSB 19
\r
1507 #define PCIe_DPLL2_KD_MASK 0x03f80000
\r
1508 #define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB)
\r
1509 #define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK)
\r
1510 #define PCIe_DPLL2_KD_RESET 0x7f // 127
\r
1511 #define PCIe_DPLL2_EN_NEGTRIG_MSB 18
\r
1512 #define PCIe_DPLL2_EN_NEGTRIG_LSB 18
\r
1513 #define PCIe_DPLL2_EN_NEGTRIG_MASK 0x00040000
\r
1514 #define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB)
\r
1515 #define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK)
\r
1516 #define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
\r
1517 #define PCIe_DPLL2_SEL_1SDM_MSB 17
\r
1518 #define PCIe_DPLL2_SEL_1SDM_LSB 17
\r
1519 #define PCIe_DPLL2_SEL_1SDM_MASK 0x00020000
\r
1520 #define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB)
\r
1521 #define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK)
\r
1522 #define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0
\r
1523 #define PCIe_DPLL2_PLL_PWD_MSB 16
\r
1524 #define PCIe_DPLL2_PLL_PWD_LSB 16
\r
1525 #define PCIe_DPLL2_PLL_PWD_MASK 0x00010000
\r
1526 #define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB)
\r
1527 #define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK)
\r
1528 #define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1
\r
1529 #define PCIe_DPLL2_OUTDIV_MSB 15
\r
1530 #define PCIe_DPLL2_OUTDIV_LSB 13
\r
1531 #define PCIe_DPLL2_OUTDIV_MASK 0x0000e000
\r
1532 #define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB)
\r
1533 #define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK)
\r
1534 #define PCIe_DPLL2_OUTDIV_RESET 0x0 // 0
\r
1535 #define PCIe_DPLL2_DELTA_MSB 12
\r
1536 #define PCIe_DPLL2_DELTA_LSB 7
\r
1537 #define PCIe_DPLL2_DELTA_MASK 0x00001f80
\r
1538 #define PCIe_DPLL2_DELTA_GET(x) (((x) & PCIe_DPLL2_DELTA_MASK) >> PCIe_DPLL2_DELTA_LSB)
\r
1539 #define PCIe_DPLL2_DELTA_SET(x) (((x) << PCIe_DPLL2_DELTA_LSB) & PCIe_DPLL2_DELTA_MASK)
\r
1540 #define PCIe_DPLL2_DELTA_RESET 0x1e // 30
\r
1541 #define PCIe_DPLL2_SPARE_MSB 6
\r
1542 #define PCIe_DPLL2_SPARE_LSB 0
\r
1543 #define PCIe_DPLL2_SPARE_MASK 0x0000007f
\r
1544 #define PCIe_DPLL2_SPARE_GET(x) (((x) & PCIe_DPLL2_SPARE_MASK) >> PCIe_DPLL2_SPARE_LSB)
\r
1545 #define PCIe_DPLL2_SPARE_SET(x) (((x) << PCIe_DPLL2_SPARE_LSB) & PCIe_DPLL2_SPARE_MASK)
\r
1546 #define PCIe_DPLL2_SPARE_RESET 0x0 // 0
\r
1547 #define PCIe_DPLL2_ADDRESS 0x18116c04
\r
1549 #define PCIe_DPLL3_MEAS_AT_TXON_MSB 31
\r
1550 #define PCIe_DPLL3_MEAS_AT_TXON_LSB 31
\r
1551 #define PCIe_DPLL3_MEAS_AT_TXON_MASK 0x80000000
\r
1552 #define PCIe_DPLL3_MEAS_AT_TXON_GET(x) (((x) & PCIe_DPLL3_MEAS_AT_TXON_MASK) >> PCIe_DPLL3_MEAS_AT_TXON_LSB)
\r
1553 #define PCIe_DPLL3_MEAS_AT_TXON_SET(x) (((x) << PCIe_DPLL3_MEAS_AT_TXON_LSB) & PCIe_DPLL3_MEAS_AT_TXON_MASK)
\r
1554 #define PCIe_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0
\r
1555 #define PCIe_DPLL3_DO_MEAS_MSB 30
\r
1556 #define PCIe_DPLL3_DO_MEAS_LSB 30
\r
1557 #define PCIe_DPLL3_DO_MEAS_MASK 0x40000000
\r
1558 #define PCIe_DPLL3_DO_MEAS_GET(x) (((x) & PCIe_DPLL3_DO_MEAS_MASK) >> PCIe_DPLL3_DO_MEAS_LSB)
\r
1559 #define PCIe_DPLL3_DO_MEAS_SET(x) (((x) << PCIe_DPLL3_DO_MEAS_LSB) & PCIe_DPLL3_DO_MEAS_MASK)
\r
1560 #define PCIe_DPLL3_DO_MEAS_RESET 0x0 // 0
\r
1561 #define PCIe_DPLL3_PHASE_SHIFT_MSB 29
\r
1562 #define PCIe_DPLL3_PHASE_SHIFT_LSB 23
\r
1563 #define PCIe_DPLL3_PHASE_SHIFT_MASK 0x3f800000
\r
1564 #define PCIe_DPLL3_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL3_PHASE_SHIFT_MASK) >> PCIe_DPLL3_PHASE_SHIFT_LSB)
\r
1565 #define PCIe_DPLL3_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL3_PHASE_SHIFT_LSB) & PCIe_DPLL3_PHASE_SHIFT_MASK)
\r
1566 #define PCIe_DPLL3_PHASE_SHIFT_RESET 0x0 // 0
\r
1567 #define PCIe_DPLL3_SQSUM_DVC_MSB 22
\r
1568 #define PCIe_DPLL3_SQSUM_DVC_LSB 3
\r
1569 #define PCIe_DPLL3_SQSUM_DVC_MASK 0x007ffff8
\r
1570 #define PCIe_DPLL3_SQSUM_DVC_GET(x) (((x) & PCIe_DPLL3_SQSUM_DVC_MASK) >> PCIe_DPLL3_SQSUM_DVC_LSB)
\r
1571 #define PCIe_DPLL3_SQSUM_DVC_SET(x) (((x) << PCIe_DPLL3_SQSUM_DVC_LSB) & PCIe_DPLL3_SQSUM_DVC_MASK)
\r
1572 #define PCIe_DPLL3_SQSUM_DVC_RESET 0x0 // 0
\r
1573 #define PCIe_DPLL3_SPARE_MSB 2
\r
1574 #define PCIe_DPLL3_SPARE_LSB 0
\r
1575 #define PCIe_DPLL3_SPARE_MASK 0x00000007
\r
1576 #define PCIe_DPLL3_SPARE_GET(x) (((x) & PCIe_DPLL3_SPARE_MASK) >> PCIe_DPLL3_SPARE_LSB)
\r
1577 #define PCIe_DPLL3_SPARE_SET(x) (((x) << PCIe_DPLL3_SPARE_LSB) & PCIe_DPLL3_SPARE_MASK)
\r
1578 #define PCIe_DPLL3_SPARE_RESET 0x0 // 0
\r
1579 #define PCIe_DPLL3_ADDRESS 0x18116c08
\r
1581 #define PCIe_DPLL4_MEAN_DVC_MSB 31
\r
1582 #define PCIe_DPLL4_MEAN_DVC_LSB 21
\r
1583 #define PCIe_DPLL4_MEAN_DVC_MASK 0xffe00000
\r
1584 #define PCIe_DPLL4_MEAN_DVC_GET(x) (((x) & PCIe_DPLL4_MEAN_DVC_MASK) >> PCIe_DPLL4_MEAN_DVC_LSB)
\r
1585 #define PCIe_DPLL4_MEAN_DVC_SET(x) (((x) << PCIe_DPLL4_MEAN_DVC_LSB) & PCIe_DPLL4_MEAN_DVC_MASK)
\r
1586 #define PCIe_DPLL4_MEAN_DVC_RESET 0x0 // 0
\r
1587 #define PCIe_DPLL4_VC_MEAS0_MSB 20
\r
1588 #define PCIe_DPLL4_VC_MEAS0_LSB 4
\r
1589 #define PCIe_DPLL4_VC_MEAS0_MASK 0x001ffff0
\r
1590 #define PCIe_DPLL4_VC_MEAS0_GET(x) (((x) & PCIe_DPLL4_VC_MEAS0_MASK) >> PCIe_DPLL4_VC_MEAS0_LSB)
\r
1591 #define PCIe_DPLL4_VC_MEAS0_SET(x) (((x) << PCIe_DPLL4_VC_MEAS0_LSB) & PCIe_DPLL4_VC_MEAS0_MASK)
\r
1592 #define PCIe_DPLL4_VC_MEAS0_RESET 0x0 // 0
\r
1593 #define PCIe_DPLL4_MEAS_DONE_MSB 3
\r
1594 #define PCIe_DPLL4_MEAS_DONE_LSB 3
\r
1595 #define PCIe_DPLL4_MEAS_DONE_MASK 0x00000008
\r
1596 #define PCIe_DPLL4_MEAS_DONE_GET(x) (((x) & PCIe_DPLL4_MEAS_DONE_MASK) >> PCIe_DPLL4_MEAS_DONE_LSB)
\r
1597 #define PCIe_DPLL4_MEAS_DONE_SET(x) (((x) << PCIe_DPLL4_MEAS_DONE_LSB) & PCIe_DPLL4_MEAS_DONE_MASK)
\r
1598 #define PCIe_DPLL4_MEAS_DONE_RESET 0x0 // 0
\r
1599 #define PCIe_DPLL4_SPARE_MSB 2
\r
1600 #define PCIe_DPLL4_SPARE_LSB 0
\r
1601 #define PCIe_DPLL4_SPARE_MASK 0x00000007
\r
1602 #define PCIe_DPLL4_SPARE_GET(x) (((x) & PCIe_DPLL4_SPARE_MASK) >> PCIe_DPLL4_SPARE_LSB)
\r
1603 #define PCIe_DPLL4_SPARE_SET(x) (((x) << PCIe_DPLL4_SPARE_LSB) & PCIe_DPLL4_SPARE_MASK)
\r
1604 #define PCIe_DPLL4_SPARE_RESET 0x0 // 0
\r
1605 #define PCIe_DPLL4_ADDRESS 0x18116c0c
\r
1607 #define ATH_DDR_COUNT_LOC 0xbd000000
\r
1608 #define ATH_CPU_COUNT_LOC 0xbd000004
\r
1610 #define XTAL_ADDRESS 0x18116290
\r
1612 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31
\r
1613 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31
\r
1614 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000
\r
1615 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB)
\r
1616 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK)
\r
1617 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0
\r
1618 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30
\r
1619 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29
\r
1620 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000
\r
1621 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB)
\r
1622 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK)
\r
1623 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0
\r
1624 #define PCIE_PHY_REG_1_PERSTDELAY_MSB 28
\r
1625 #define PCIE_PHY_REG_1_PERSTDELAY_LSB 27
\r
1626 #define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000
\r
1627 #define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB)
\r
1628 #define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK)
\r
1629 #define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2
\r
1630 #define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26
\r
1631 #define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25
\r
1632 #define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000
\r
1633 #define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB)
\r
1634 #define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK)
\r
1635 #define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0
\r
1636 #define PCIE_PHY_REG_1_DATAOBSEN_MSB 24
\r
1637 #define PCIE_PHY_REG_1_DATAOBSEN_LSB 24
\r
1638 #define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000
\r
1639 #define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB)
\r
1640 #define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK)
\r
1641 #define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0
\r
1642 #define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23
\r
1643 #define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23
\r
1644 #define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000
\r
1645 #define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB)
\r
1646 #define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK)
\r
1647 #define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0
\r
1648 #define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22
\r
1649 #define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22
\r
1650 #define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000
\r
1651 #define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB)
\r
1652 #define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK)
\r
1653 #define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0
\r
1654 #define PCIE_PHY_REG_1_RXCLKINV_MSB 21
\r
1655 #define PCIE_PHY_REG_1_RXCLKINV_LSB 21
\r
1656 #define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000
\r
1657 #define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB)
\r
1658 #define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK)
\r
1659 #define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1
\r
1660 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20
\r
1661 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20
\r
1662 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000
\r
1663 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB)
\r
1664 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK)
\r
1665 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0
\r
1666 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19
\r
1667 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19
\r
1668 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000
\r
1669 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB)
\r
1670 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK)
\r
1671 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0
\r
1672 #define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18
\r
1673 #define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18
\r
1674 #define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000
\r
1675 #define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB)
\r
1676 #define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK)
\r
1677 #define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0
\r
1678 #define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17
\r
1679 #define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17
\r
1680 #define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000
\r
1681 #define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB)
\r
1682 #define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK)
\r
1683 #define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0
\r
1684 #define PCIE_PHY_REG_1_SEL_CLK_MSB 16
\r
1685 #define PCIE_PHY_REG_1_SEL_CLK_LSB 15
\r
1686 #define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000
\r
1687 #define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB)
\r
1688 #define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK)
\r
1689 #define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2
\r
1690 #define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14
\r
1691 #define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14
\r
1692 #define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000
\r
1693 #define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB)
\r
1694 #define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK)
\r
1695 #define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0
\r
1696 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13
\r
1697 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13
\r
1698 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000
\r
1699 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB)
\r
1700 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK)
\r
1701 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1
\r
1702 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12
\r
1703 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12
\r
1704 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000
\r
1705 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)
\r
1706 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)
\r
1707 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0
\r
1708 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11
\r
1709 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11
\r
1710 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800
\r
1711 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB)
\r
1712 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK)
\r
1713 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0
\r
1714 #define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10
\r
1715 #define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9
\r
1716 #define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600
\r
1717 #define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB)
\r
1718 #define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK)
\r
1719 #define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3
\r
1720 #define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8
\r
1721 #define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7
\r
1722 #define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180
\r
1723 #define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB)
\r
1724 #define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK)
\r
1725 #define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0
\r
1726 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6
\r
1727 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6
\r
1728 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040
\r
1729 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB)
\r
1730 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK)
\r
1731 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1
\r
1732 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5
\r
1733 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5
\r
1734 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020
\r
1735 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB)
\r
1736 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK)
\r
1737 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0
\r
1738 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4
\r
1739 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4
\r
1740 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010
\r
1741 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB)
\r
1742 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK)
\r
1743 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1
\r
1744 #define PCIE_PHY_REG_1_S_MSB 3
\r
1745 #define PCIE_PHY_REG_1_S_LSB 0
\r
1746 #define PCIE_PHY_REG_1_S_MASK 0x0000000f
\r
1747 #define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB)
\r
1748 #define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK)
\r
1749 #define PCIE_PHY_REG_1_S_RESET 0xe // 14
\r
1750 #define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
\r
1752 #define AR934X_GPIO_BASE 0x18040000
\r
1753 #define AR934X_GPIO_OE AR934X_GPIO_BASE + 0x0
\r
1754 #define AR934X_GPIO_IN AR934X_GPIO_BASE + 0x4
\r
1755 #define AR934X_GPIO_OUT AR934X_GPIO_BASE + 0x8
\r
1756 #define AR934X_GPIO_SET AR934X_GPIO_BASE + 0xC
\r
1757 #define AR934X_GPIO_CLEAR AR934X_GPIO_BASE + 0x10
\r
1758 #define AR934X_GPIO_INT AR934X_GPIO_BASE + 0x14
\r
1759 #define AR934X_GPIO_INT_TYPE AR934X_GPIO_BASE + 0x18
\r
1760 #define AR934X_GPIO_INT_POLARITY AR934X_GPIO_BASE + 0x1C
\r
1761 #define AR934X_GPIO_INT_PENDING AR934X_GPIO_BASE + 0x20
\r
1762 #define AR934X_GPIO_INT_MASK AR934X_GPIO_BASE + 0x24
\r
1763 #define AR934X_GPIO_IN_ETH_SWITCH_LED AR934X_GPIO_BASE + 0x28
\r
1764 #define AR934X_GPIO_OUT_FUNCTION0 AR934X_GPIO_BASE + 0x2C
\r
1765 #define AR934X_GPIO_OUT_FUNCTION1 AR934X_GPIO_BASE + 0x30
\r
1766 #define AR934X_GPIO_OUT_FUNCTION2 AR934X_GPIO_BASE + 0x34
\r
1767 #define AR934X_GPIO_OUT_FUNCTION3 AR934X_GPIO_BASE + 0x38
\r
1768 #define AR934X_GPIO_OUT_FUNCTION4 AR934X_GPIO_BASE + 0x3C
\r
1769 #define AR934X_GPIO_IN_ENABLE0 AR934X_GPIO_BASE + 0x44
\r
1770 #define AR934X_GPIO_IN_ENABLE1 AR934X_GPIO_BASE + 0x48
\r
1771 #define AR934X_GPIO_IN_ENABLE2 AR934X_GPIO_BASE + 0x4C
\r
1772 #define AR934X_GPIO_IN_ENABLE3 AR934X_GPIO_BASE + 0x50
\r
1773 #define AR934X_GPIO_IN_ENABLE4 AR934X_GPIO_BASE + 0x54
\r
1774 #define AR934X_GPIO_IN_ENABLE9 AR934X_GPIO_BASE + 0x68
\r
1775 #define AR934X_GPIO_FUNCTION AR934X_GPIO_BASE + 0x6C
\r
1777 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31
\r
1778 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24
\r
1779 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000
\r
1780 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
\r
1781 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
\r
1782 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb // 11
\r
1783 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23
\r
1784 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16
\r
1785 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000
\r
1786 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
\r
1787 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
\r
1788 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa // 10
\r
1789 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15
\r
1790 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8
\r
1791 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00
\r
1792 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
\r
1793 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
\r
1794 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9
\r
1795 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7
\r
1796 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0
\r
1797 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff
\r
1798 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
\r
1799 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
\r
1800 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20
\r
1801 #define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030
\r
1803 #endif /* _AR934X_SOC_H */
\r
projects / oweals / u-boot_mod.git / blob