2 * Atheror AR7240 series processor SOC registers
4 * (C) Copyright 2008 Atheros Communications, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifdef CONFIG_WASP_SUPPORT
28 #include <ar934x_soc.h>
31 #ifdef CONFIG_AR7240_EMU
35 #ifdef CONFIG_WASP_EMU
41 #define AR7240_PCI_MEM_BASE 0x10000000 /* 128M */
42 #define AR7240_APB_BASE 0x18000000 /* 384M */
43 #define AR7240_GE0_BASE 0x19000000 /* 16M */
44 #define AR7240_GE1_BASE 0x1a000000 /* 16M */
45 #define AR7240_USB_EHCI_BASE 0x1b000000
46 #define AR7240_USB_OHCI_BASE 0x1c000000
47 #define AR7240_SPI_BASE 0x1f000000
48 #define ATH_NAND_FLASH_BASE 0x1b000000u
53 #define AR7240_DDR_CTL_BASE AR7240_APB_BASE+0x00000000
54 #define AR7240_CPU_BASE AR7240_APB_BASE+0x00010000
55 #define AR7240_UART_BASE AR7240_APB_BASE+0x00020000
56 #define AR7240_USB_CONFIG_BASE AR7240_APB_BASE+0x00030000
57 #define AR7240_GPIO_BASE AR7240_APB_BASE+0x00040000
58 #define AR7240_PLL_BASE AR7240_APB_BASE+0x00050000
59 #define AR7240_RESET_BASE AR7240_APB_BASE+0x00060000
60 #define AR7240_PCI_LCL_BASE AR7240_APB_BASE+0x000f0000
65 #define AR7240_DDR_CONFIG AR7240_DDR_CTL_BASE+0
66 #define AR7240_DDR_CONFIG2 AR7240_DDR_CTL_BASE+4
67 #define AR7240_DDR_MODE AR7240_DDR_CTL_BASE+0x08
68 #define AR7240_DDR_EXT_MODE AR7240_DDR_CTL_BASE+0x0c
69 #define AR7240_DDR_CONTROL AR7240_DDR_CTL_BASE+0x10
70 #define AR7240_DDR_REFRESH AR7240_DDR_CTL_BASE+0x14
71 #define AR7240_DDR_RD_DATA_THIS_CYCLE AR7240_DDR_CTL_BASE+0x18
72 #define AR7240_DDR_TAP_CONTROL0 AR7240_DDR_CTL_BASE+0x1c
73 #define AR7240_DDR_TAP_CONTROL1 AR7240_DDR_CTL_BASE+0x20
74 #define AR7240_DDR_TAP_CONTROL2 AR7240_DDR_CTL_BASE+0x24
75 #define AR7240_DDR_TAP_CONTROL3 AR7240_DDR_CTL_BASE+0x28
78 #define AR7240_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0xb8
80 #define AR7240_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0x8c
83 #define AR7240_DDR_BURST AR7240_DDR_CTL_BASE+0xc4
84 #define AR7240_DDR_BURST2 AR7240_DDR_CTL_BASE+0xc8
85 #define AR7240_AHB_MASTER_TIMEOUT AR7240_DDR_CTL_BASE+0xcc
86 #define AR7240_DDR_CTL_CONFIG AR7240_DDR_CTL_BASE+0x108
87 #define AR7240_DDR_DEBUG_RD_CNTL AR7240_DDR_CTL_BASE+0x118
89 #define AR7240_DDR_CONFIG_16BIT (1 << 31)
90 #define AR7240_DDR_CONFIG_PAGE_OPEN (1 << 30)
91 #define AR7240_DDR_CONFIG_CAS_LAT_SHIFT 27
92 #define AR7240_DDR_CONFIG_TMRD_SHIFT 23
93 #define AR7240_DDR_CONFIG_TRFC_SHIFT 17
94 #define AR7240_DDR_CONFIG_TRRD_SHIFT 13
95 #define AR7240_DDR_CONFIG_TRP_SHIFT 9
96 #define AR7240_DDR_CONFIG_TRCD_SHIFT 5
97 #define AR7240_DDR_CONFIG_TRAS_SHIFT 0
99 #define AR7240_DDR_CONFIG2_BL2 (2 << 0)
100 #define AR7240_DDR_CONFIG2_BL4 (4 << 0)
101 #define AR7240_DDR_CONFIG2_BL8 (8 << 0)
103 #define AR7240_DDR_CONFIG2_BT_IL (1 << 4)
104 #define AR7240_DDR_CONFIG2_CNTL_OE_EN (1 << 5)
105 #define AR7240_DDR_CONFIG2_PHASE_SEL (1 << 6)
106 #define AR7240_DDR_CONFIG2_DRAM_CKE (1 << 7)
107 #define AR7240_DDR_CONFIG2_TWR_SHIFT 8
108 #define AR7240_DDR_CONFIG2_TRTW_SHIFT 12
109 #define AR7240_DDR_CONFIG2_TRTP_SHIFT 17
110 #define AR7240_DDR_CONFIG2_TWTR_SHIFT 21
111 #define AR7240_DDR_CONFIG2_HALF_WIDTH_L (1 << 31)
113 #define AR7240_DDR_TAP_DEFAULT 0x18
118 #define AR7240_CPU_PLL_CONFIG AR7240_PLL_BASE
119 #define AR7240_USB_PLL_CONFIG AR7240_PLL_BASE+0x4
120 #define AR7240_PCIE_PLL_CONFIG AR7240_PLL_BASE+0x10
121 #define AR7240_CPU_CLOCK_CONTROL AR7240_PLL_BASE+8
123 #ifndef CONFIG_WASP_SUPPORT
124 #define AR7240_USB_PLL_GE0_OFFSET AR7240_PLL_BASE+0x10
125 #define AR7240_USB_PLL_GE1_OFFSET AR7240_PLL_BASE+0x14
126 #define AR7240_S26_CLK_CTRL_OFFSET AR7240_PLL_BASE+0x24
129 #define AR7242_ETH_XMII_CONFIG AR7240_PLL_BASE+0x2c
130 #define AR934X_CPU_PLL_DITHER AR7240_PLL_BASE+0x0048
131 #define AR934X_DDR_PLL_DITHER AR7240_PLL_BASE+0x0044
132 #define AR934X_BB_PLL_CONFIG AR7240_PLL_BASE+0x0040
133 #define AR934X_CURRENT_AUDIO_PLL_MODULATION AR7240_PLL_BASE+0x003c
134 #define AR934X_AUDIO_PLL_MOD_STEP AR7240_PLL_BASE+0x0038
135 #define AR934X_AUDIO_PLL_MODULATION AR7240_PLL_BASE+0x0034
136 #define AR934X_AUDIO_PLL_CONFIG AR7240_PLL_BASE+0x0030
137 #define AR934X_ETH_XMII AR7240_PLL_BASE+0x002c
138 #define AR934X_CURRENT_PCIE_PLL_DITHER AR7240_PLL_BASE+0x0028
139 #define AR934X_SWITCH_CLOCK_SPARE AR7240_PLL_BASE+0x0024
140 #define AR934X_LDO_POWER_CONTROL AR7240_PLL_BASE+0x0020
141 #define AR934X_PCIE_PLL_DITHER_STEP AR7240_PLL_BASE+0x001c
142 #define AR934X_PCIE_PLL_DITHER_DIV_MIN AR7240_PLL_BASE+0x0018
143 #define AR934X_PCIE_PLL_DITHER_DIV_MAX AR7240_PLL_BASE+0x0014
144 #define AR934X_PCIE_PLL_CONFIG AR7240_PLL_BASE+0x0010
145 #define AR934X_CPU_SYNC AR7240_PLL_BASE+0x000c
146 #define AR934X_CPU_DDR_CLOCK_CONTROL AR7240_PLL_BASE+0x0008
147 #define AR934X_DDR_PLL_CONFIG AR7240_PLL_BASE+0x0004
148 #define AR934X_CPU_PLL_CONFIG AR7240_PLL_BASE+0x0000
150 #define PLL_CONFIG_PLL_DIV_SHIFT 0
151 #define PLL_CONFIG_PLL_DIV_MASK (0x3ff<< PLL_CONFIG_PLL_DIV_SHIFT)
152 #define PLL_CONFIG_PLL_REF_DIV_SHIFT 10
153 #define PLL_CONFIG_PLL_REF_DIV_MASK (0xf << PLL_CONFIG_PLL_REF_DIV_SHIFT)
154 #define PLL_CONFIG_PLL_BYPASS_SHIFT 16
155 #define PLL_CONFIG_PLL_BYPASS_MASK (0x1 << PLL_CONFIG_PLL_BYPASS_SHIFT)
156 #define PLL_CONFIG_PLL_UPDATE_SHIFT 17
157 #define PLL_CONFIG_PLL_UPDATE_MASK (0x1 << PLL_CONFIG_PLL_UPDATE_SHIFT)
158 #define PLL_CONFIG_PLL_NOPWD_SHIFT 18
159 #define PLL_CONFIG_PLL_NOPWD_MASK (0x1 << PLL_CONFIG_PLL_NOPWD_SHIFT)
160 #define PLL_CONFIG_AHB_DIV_SHIFT 19
161 #define PLL_CONFIG_AHB_DIV_MASK (0x1 << PLL_CONFIG_AHB_DIV_SHIFT)
162 #define PLL_CONFIG_DDR_DIV_SHIFT 22
163 #define PLL_CONFIG_DDR_DIV_MASK (0x1 << PLL_CONFIG_DDR_DIV_SHIFT)
164 #define PLL_CONFIG_PLL_RESET_SHIFT 25
165 #define PLL_CONFIG_PLL_RESET_MASK (0x1 << PLL_CONFIG_PLL_RESET_SHIFT)
167 /* Hornet's CPU PLL Configuration Register */
168 #define HORNET_PLL_CONFIG_NINT_SHIFT 10
169 #define HORNET_PLL_CONFIG_NINT_MASK (0x3f << HORNET_PLL_CONFIG_NINT_SHIFT)
170 #define HORNET_PLL_CONFIG_REFDIV_SHIFT 16
171 #define HORNET_PLL_CONFIG_REFDIV_MASK (0x1f << HORNET_PLL_CONFIG_REFDIV_SHIFT)
172 #define HORNET_PLL_CONFIG_OUTDIV_SHIFT 23
173 #define HORNET_PLL_CONFIG_OUTDIV_MASK (0x7 << HORNET_PLL_CONFIG_OUTDIV_SHIFT)
174 #define HORNET_PLL_CONFIG_PLLPWD_SHIFT 30
175 #define HORNET_PLL_CONFIG_PLLPWD_MASK (0x1 << HORNET_PLL_CONFIG_PLLPWD_SHIFT)
176 #define HORNET_PLL_CONFIG_UPDATING_SHIFT 31
177 #define HORNET_PLL_CONFIG_UPDATING_MASK (0x1 << HORNET_PLL_CONFIG_UPDATING_SHIFT)
179 /* Hornet's CPU PLL Configuration 2 Register */
180 #define HORNET_PLL_CONFIG2_SETTLE_TIME_SHIFT 0
181 #define HORNET_PLL_CONFIG2_SETTLE_TIME_MASK (0xfff << HORNET_PLL_CONFIG2_SETTLE_TIME_SHIFT)
183 /* Hornet's CPU Clock Control Register */
184 #define HORNET_CLOCK_CONTROL_BYPASS_SHIFT 2
185 #define HORNET_CLOCK_CONTROL_BYPASS_MASK (0x1 << HORNET_CLOCK_CONTROL_BYPASS_SHIFT)
186 #define HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT 5
187 #define HORNET_CLOCK_CONTROL_CPU_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT)
188 #define HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT 10
189 #define HORNET_CLOCK_CONTROL_DDR_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT)
190 #define HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT 15
191 #define HORNET_CLOCK_CONTROL_AHB_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT)
193 #define CLOCK_CONTROL_CLOCK_SWITCH_SHIFT 0
194 #define CLOCK_CONTROL_CLOCK_SWITCH_MASK (1 << CLOCK_CONTROL_CLOCK_SWITCH_SHIFT)
195 #define CLOCK_CONTROL_RST_SWITCH_SHIFT 1
196 #define CLOCK_CONTROL_RST_SWITCH_MASK (1 << CLOCK_CONTROL_RST_SWITCH_SHIFT)
199 ** PLL config for different CPU/DDR/AHB frequencies
201 #define PLL_CONFIG_PLL_NOPWD_VAL (1 << PLL_CONFIG_PLL_NOPWD_SHIFT)
203 #define UBOOT_SIZE (256 * 1024)
204 #define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE)
205 #define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20)
206 #define PLL_MAGIC 0xaabbccdd
207 #define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12)
208 #define SRIF_PLL_MAGIC 0x73726966 /* srif */
213 #define AR7240_PLL_CONFIG AR7240_PLL_BASE+0x0
218 #define AR7240_CPU_CLOCK_CONTROL AR7240_PLL_BASE+8
223 #define AR7240_DDR_GE0_FLUSH AR7240_DDR_CTL_BASE+0x9c
224 #define AR7240_DDR_GE1_FLUSH AR7240_DDR_CTL_BASE+0xa0
225 #define AR7240_DDR_PCI_FLUSH AR7240_DDR_CTL_BASE+0xa8
230 #define AR7240_USB_FLADJ_VAL AR7240_USB_CONFIG_BASE
231 #define AR7240_USB_CONFIG AR7240_USB_CONFIG_BASE+0x4
232 #define AR7240_USB_WINDOW 0x1000000
237 #define AR7240_PCI_WINDOW 0x8000000 /* 128MB */
238 #define AR7240_PCI_WINDOW0_OFFSET AR7240_DDR_CTL_BASE+0x7c
239 #define AR7240_PCI_WINDOW1_OFFSET AR7240_DDR_CTL_BASE+0x80
240 #define AR7240_PCI_WINDOW2_OFFSET AR7240_DDR_CTL_BASE+0x84
241 #define AR7240_PCI_WINDOW3_OFFSET AR7240_DDR_CTL_BASE+0x88
242 #define AR7240_PCI_WINDOW4_OFFSET AR7240_DDR_CTL_BASE+0x8c
243 #define AR7240_PCI_WINDOW5_OFFSET AR7240_DDR_CTL_BASE+0x90
244 #define AR7240_PCI_WINDOW6_OFFSET AR7240_DDR_CTL_BASE+0x94
245 #define AR7240_PCI_WINDOW7_OFFSET AR7240_DDR_CTL_BASE+0x98
247 #define AR7240_PCI_WINDOW0_VAL 0x10000000
248 #define AR7240_PCI_WINDOW1_VAL 0x11000000
249 #define AR7240_PCI_WINDOW2_VAL 0x12000000
250 #define AR7240_PCI_WINDOW3_VAL 0x13000000
251 #define AR7240_PCI_WINDOW4_VAL 0x14000000
252 #define AR7240_PCI_WINDOW5_VAL 0x15000000
253 #define AR7240_PCI_WINDOW6_VAL 0x16000000
254 #define AR7240_PCI_WINDOW7_VAL 0x07000000
257 * CRP. To access the host controller config and status registers
259 #define AR7240_PCI_CRP 0x180c0000
260 #define AR7240_PCI_DEV_CFGBASE 0x14000000
262 #define AR7240_PCI_CRP_AD_CBE AR7240_PCI_CRP
263 #define AR7240_PCI_CRP_WRDATA AR7240_PCI_CRP+0x4
264 #define AR7240_PCI_CRP_RDDATA AR7240_PCI_CRP+0x8
265 #define AR7240_PCI_ERROR AR7240_PCI_CRP+0x1c
266 #define AR7240_PCI_ERROR_ADDRESS AR7240_PCI_CRP+0x20
267 #define AR7240_PCI_AHB_ERROR AR7240_PCI_CRP+0x24
268 #define AR7240_PCI_AHB_ERROR_ADDRESS AR7240_PCI_CRP+0x28
270 #define AR7240_CRP_CMD_WRITE 0x00010000
271 #define AR7240_CRP_CMD_READ 0x00000000
274 * PCI CFG. To generate config cycles
276 #define AR7240_PCI_CFG_AD AR7240_PCI_CRP+0xc
277 #define AR7240_PCI_CFG_CBE AR7240_PCI_CRP+0x10
278 #define AR7240_PCI_CFG_WRDATA AR7240_PCI_CRP+0x14
279 #define AR7240_PCI_CFG_RDDATA AR7240_PCI_CRP+0x18
280 #define AR7240_CFG_CMD_READ 0x0000000a
281 #define AR7240_CFG_CMD_WRITE 0x0000000b
283 #define AR7240_PCI_IDSEL_ADLINE_START 17
284 #define AR7240_PCI_LCL_RESET AR7240_PCI_LCL_BASE+0x18
289 #define AR7240_GPIO_OE AR7240_GPIO_BASE+0x0
290 #define AR7240_GPIO_IN AR7240_GPIO_BASE+0x4
291 #define AR7240_GPIO_OUT AR7240_GPIO_BASE+0x8
292 #define AR7240_GPIO_SET AR7240_GPIO_BASE+0xc
293 #define AR7240_GPIO_CLEAR AR7240_GPIO_BASE+0x10
294 #define AR7240_GPIO_INT_ENABLE AR7240_GPIO_BASE+0x14
295 #define AR7240_GPIO_INT_TYPE AR7240_GPIO_BASE+0x18
296 #define AR7240_GPIO_INT_POLARITY AR7240_GPIO_BASE+0x1c
297 #define AR7240_GPIO_INT_PENDING AR7240_GPIO_BASE+0x20
298 #define AR7240_GPIO_INT_MASK AR7240_GPIO_BASE+0x24
299 #define AR7240_GPIO_FUNC AR7240_GPIO_BASE+0x28
303 * There are 4 conceptual ICs in the system. We generally give a block of 16
311 #define AR7240_CPU_IRQ_BASE 0x00
312 #define AR7240_MISC_IRQ_BASE 0x10
313 #define AR7240_GPIO_IRQ_BASE 0x20
314 #define AR7240_PCI_IRQ_BASE 0x30
317 * The IPs. Connected to CPU (hardware IP's; the first two are software)
319 #define AR7240_CPU_IRQ_PCI AR7240_CPU_IRQ_BASE+2
320 #define AR7240_CPU_IRQ_USB AR7240_CPU_IRQ_BASE+3
321 #define AR7240_CPU_IRQ_GE0 AR7240_CPU_IRQ_BASE+4
322 #define AR7240_CPU_IRQ_GE1 AR7240_CPU_IRQ_BASE+5
323 #define AR7240_CPU_IRQ_MISC AR7240_CPU_IRQ_BASE+6
324 #define AR7240_CPU_IRQ_TIMER AR7240_CPU_IRQ_BASE+7
327 * Interrupts connected to the CPU->Misc line.
329 #define AR7240_MISC_IRQ_TIMER AR7240_MISC_IRQ_BASE+0
330 #define AR7240_MISC_IRQ_ERROR AR7240_MISC_IRQ_BASE+1
331 #define AR7240_MISC_IRQ_GPIO AR7240_MISC_IRQ_BASE+2
332 #define AR7240_MISC_IRQ_UART AR7240_MISC_IRQ_BASE+3
333 #define AR7240_MISC_IRQ_WATCHDOG AR7240_MISC_IRQ_BASE+4
334 #define AR7240_MISC_IRQ_COUNT 5
336 #define MIMR_TIMER 0x01
337 #define MIMR_ERROR 0x02
338 #define MIMR_GPIO 0x04
339 #define MIMR_UART 0x08
340 #define MIMR_WATCHDOG 0x10
342 #define MISR_TIMER MIMR_TIMER
343 #define MISR_ERROR MIMR_ERROR
344 #define MISR_GPIO MIMR_GPIO
345 #define MISR_UART MIMR_UART
346 #define MISR_WATCHDOG MIMR_WATCHDOG
349 * Interrupts connected to the Misc->GPIO line
351 #define AR7240_GPIO_IRQn(_gpio) AR7240_GPIO_IRQ_BASE+(_gpio)
352 #define AR7240_GPIO_IRQ_COUNT 16
355 * Interrupts connected to CPU->PCI
357 #define AR7240_PCI_IRQ_DEV0 AR7240_PCI_IRQ_BASE+0
358 #define AR7240_PCI_IRQ_DEV1 AR7240_PCI_IRQ_BASE+1
359 #define AR7240_PCI_IRQ_DEV2 AR7240_PCI_IRQ_BASE+2
360 #define AR7240_PCI_IRQ_CORE AR7240_PCI_IRQ_BASE+3
361 #define AR7240_PCI_IRQ_COUNT 4
364 * PCI interrupt mask and status
366 #define PIMR_DEV0 0x01
367 #define PIMR_DEV1 0x02
368 #define PIMR_DEV2 0x04
369 #define PIMR_CORE 0x10
371 #define PISR_DEV0 PIMR_DEV0
372 #define PISR_DEV1 PIMR_DEV1
373 #define PISR_DEV2 PIMR_DEV2
374 #define PISR_CORE PIMR_CORE
376 #define AR7240_GPIO_COUNT 16
381 #define AR7240_GENERAL_TMR AR7240_RESET_BASE+0
382 #define AR7240_GENERAL_TMR_RELOAD AR7240_RESET_BASE+4
383 #define AR7240_WATCHDOG_TMR_CONTROL AR7240_RESET_BASE+8
384 #define AR7240_WATCHDOG_TMR AR7240_RESET_BASE+0xc
385 #define AR7240_MISC_INT_STATUS AR7240_RESET_BASE+0x10
386 #define AR7240_MISC_INT_MASK AR7240_RESET_BASE+0x14
387 #define AR7240_GLOBAL_INT_STATUS AR7240_RESET_BASE+0x18
388 #define AR7240_RESET AR7240_RESET_BASE+0x1c
389 #define HORNET_BOOTSTRAP_STATUS AR7240_RESET_BASE+0xac /* Hornet's bootstrap register */
390 #define AR7240_REV_ID (AR7240_RESET_BASE + 0x90)
391 #define AR7240_REV_ID_MASK 0xffff
392 #define HORNET_REV_ID_MASK 0xfff
393 #define AR9344_REV_ID_MASK 0xfff0 /* Ignore minor id */
394 #define HORNET_BOOTSTRAP_SEL_25M_40M_MASK 0x00000001 /* Hornet's bootstrap register */
395 #define HORNET_BOOTSTRAP_MEM_TYPE_SHIFT 12
396 #define HORNET_BOOTSTRAP_MEM_TYPE_MASK (0x3 << HORNET_BOOTSTRAP_MEM_TYPE_SHIFT) /* Hornet's bootstrap register */
397 #define HORNET_BOOTSTRAP_MDIO_SLAVE_MASK 0x00020000 /* Hornet's bootstrap register */
399 // WASP BootStrap Register
400 #define WASP_BOOTSTRAP_REG (AR7240_RESET_BASE + 0xb0)
401 #define WASP_BOOTSTRAP_SDRAM_DISABLE_SHIFT 1
402 #define WASP_BOOTSTRAP_SDRAM_DISABLE_MASK (1 << WASP_BOOTSTRAP_SDRAM_DISABLE_SHIFT)
403 #define WASP_BOOTSTRAP_DDR_SELECT_SHIFT 0
404 #define WASP_BOOTSTRAP_DDR_SELECT_MASK (1 << WASP_BOOTSTRAP_DDR_SELECT_SHIFT)
405 #define WASP_BOOTSTRAP_DDR_WIDTH_SHIFT 21
406 #define WASP_BOOTSTRAP_DDR_WIDTH_MASK (1 << WASP_BOOTSTRAP_DDR_WIDTH_SHIFT)
407 #define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
408 #define WASP_RAM_TYPE(a) ((a) & 0x3)
410 #define CFG_934X_SDRAM_CONFIG_VAL 0x7fbe8cd0
411 #define CFG_934X_SDRAM_MODE_VAL_INIT 0x133
412 #define CFG_934X_SDRAM_MODE_VAL 0x33
413 #define CFG_934X_SDRAM_CONFIG2_VAL 0x959f66a8
414 #define CFG_934X_SDRAM_TAP_VAL 0x1f1f
416 #define CFG_934X_DDR1_CONFIG_VAL 0x7fd48cd0 // 0xc7d48cd0
417 #define CFG_934X_DDR1_MODE_VAL_INIT 0x133
418 #define CFG_934X_DDR1_EXT_MODE_VAL 0x0
419 #define CFG_934X_DDR1_MODE_VAL 0x33
420 #define CFG_934X_DDR1_CONFIG2_VAL 0x99d0e6a8 // 0x9dd0e6a8
422 #if (CFG_PLL_FREQ == CFG_PLL_500_500_250)
423 #define CFG_934X_DDR2_CONFIG_VAL 0xcfbc8cd0
424 #define CFG_934X_DDR2_MODE_VAL_INIT 0x143
425 #define CFG_934X_DDR2_EXT_MODE_VAL 0x402
426 #define CFG_934X_DDR2_MODE_VAL 0x43
427 #define CFG_934X_DDR2_CONFIG2_VAL 0xa5d0e6a8
428 #define CFG_934X_DDR2_EN_TWL_VAL 0x1659
429 #define CFG_934X_DDR2_TAP_VAL 0
430 #elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) || \
431 (CFG_PLL_FREQ == CFG_PLL_600_600_300) || \
432 (CFG_PLL_FREQ == CFG_PLL_600_550_275) || \
433 (CFG_PLL_FREQ == CFG_PLL_600_575_287)
435 #define CFG_934X_DDR2_CONFIG_VAL 0xcfd48cd0
436 #define CFG_934X_DDR2_MODE_VAL_INIT 0x143
437 #define CFG_934X_DDR2_EXT_MODE_VAL 0x402
438 #define CFG_934X_DDR2_MODE_VAL 0x43
439 #define CFG_934X_DDR2_CONFIG2_VAL 0xa1d0e6a8
440 #define CFG_934X_DDR2_EN_TWL_VAL 0x1659
441 #define CFG_934X_DDR2_TAP_VAL 0x5
446 * Reason: patch from LSDK-9.2.0.312
448 #define CFG_934X_DDR2_CONFIG_VAL 0xc7d48cd0
449 #define CFG_934X_DDR2_MODE_VAL_INIT 0x133
450 #define CFG_934X_DDR2_EXT_MODE_VAL_INIT 0x382
451 #define CFG_934X_DDR2_EXT_MODE_VAL 0x402
452 #define CFG_934X_DDR2_MODE_VAL 0x33
453 #define CFG_934X_DDR2_CONFIG2_VAL 0x9dd0e6a8
454 #define CFG_934X_DDR2_EN_TWL_VAL 0xe59
455 #define CFG_934X_DDR2_TAP_VAL 0x10012
458 #define CFG_934X_DDR1_TAP_VAL 0x14
460 #define AR7240_REV_ID_AR7130 0xa0
461 #define AR7240_REV_ID_AR7141 0xa1
462 #define AR7240_REV_ID_AR7161 0xa2
463 #define AR7240_REV_1_0 0xc0
464 #define AR7240_REV_1_1 0xc1
465 #define AR7240_REV_1_2 0xc2
466 #define AR7241_REV_1_0 0x0100
467 #define AR7242_REV_1_0 0x1100
468 #define AR7241_REV_1_1 0x0101
469 #define AR7242_REV_1_1 0x1101
471 #define AR9330_REV_1_0 0x0110 /* 5-port:0x110, 4-port 0x1110 */
472 #define AR9331_REV_1_0 0x1110
473 #define AR9330_REV_1_1 0x0111 /* 5-port:0x111, 4-port 0x1111 */
474 #define AR9331_REV_1_1 0x1111
475 #define AR9330_REV_1_2 0x0112
476 #define AR9331_REV_1_2 0x1112
478 #define AR9344_REV_1_x 0x2120 /* Wasp 1.x, ignore minor id */
479 #define AR9342_REV_1_x 0x1120
480 #define AR9341_REV_1_x 0x0120
482 #define AR9344_REV_1_0 0x2120 /* Wasp 1.0 */
483 #define AR9342_REV_1_0 0x1120
484 #define AR9341_REV_1_0 0x0120
486 #define AR9344_REV_1_1 0x2121 /* Wasp 1.1 */
487 #define AR9342_REV_1_1 0x1121
488 #define AR9341_REV_1_1 0x0121
490 #define is_ar7240() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) || \
491 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_1) || \
492 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_0))
494 #define is_ar7241() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7241_REV_1_0) || \
495 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7241_REV_1_1))
497 #define is_ar7242() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7242_REV_1_0) || \
498 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7242_REV_1_1))
500 #define is_ar9330() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) || \
501 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) || \
502 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_2))
504 #define is_ar9331() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_0) || \
505 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_1) || \
506 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_2))
508 #define is_ar933x_10() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) || \
509 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_0))
511 #define is_ar933x_11() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) || \
512 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_1))
514 #define is_ar933x_12() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_2) || \
515 ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_2))
518 #define is_ar933x() (is_ar9330() || is_ar9331())
520 #define is_ar9344() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9344_REV_1_x)
521 #define is_ar9342() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9342_REV_1_x)
522 #define is_ar9341() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9341_REV_1_x)
524 #ifdef CONFIG_WASP_SUPPORT
526 #define is_ar934x() 1
529 #define is_ar934x() 0
532 #ifdef CONFIG_AR7240_EMU
538 #ifdef CONFIG_F1E_PHY
544 #ifdef CONFIG_F2E_PHY
550 #ifdef CONFIG_ATHRS16_PHY
557 * AR7240_RESET bit defines
559 #define AR7240_RESET_EXTERNAL (1 << 28)
560 #define AR7240_RESET_WMAC (1 << 27)
561 #define AR7240_RESET_FULL_CHIP (1 << 24)
562 #define AR7240_RESET_CPU_NMI (1 << 21)
563 #define AR7240_RESET_CPU_COLD_RESET_MASK (1 << 20)
564 #define AR7240_RESET_DDR (1 << 16)
565 #define AR7240_RESET_GE1_MAC (1 << 13)
566 #define AR7240_RESET_GE1_MDIO (1 << 23)
567 #define AR7240_RESET_GE1_PHY (1 << 12) /* Not valid */
568 #define AR7240_RESET_PCIE_PHY_SERIAL (1 << 10)
569 #define AR7240_RESET_GE0_MAC (1 << 9)
570 #define AR7240_RESET_GE0_MDIO (1 << 22)
571 #define AR7240_RESET_GE0_PHY (1 << 8) /* Switch reset */
572 #define AR7240_RESET_PCIE_PHY (1 << 7)
573 #define AR7240_RESET_PCIE (1 << 6)
574 #define AR7240_RESET_USB_HOST (1 << 5)
575 #define AR7240_RESET_USB_OHCI_DLL (1 << 3)
577 #define AR7240_MII0_CTRL 0x18070000
578 #define AR7240_MII1_CTRL 0x18070004
589 #define ar7240_reg_rd(_phys) (*(volatile unsigned int *)KSEG1ADDR(_phys))
590 #define ar7240_reg_wr_nf(_phys, _val) ((*(volatile unsigned int *)KSEG1ADDR(_phys)) = (_val))
592 #define ar7240_reg_wr(_phys, _val) do { ar7240_reg_wr_nf(_phys, _val); ar7240_reg_rd(_phys); } while(0);
594 #define ar7240_write_pci_window(_no) \
595 ar7240_reg_wr(AR7240_PCI_WINDOW##_no##_OFFSET, AR7240_PCI_WINDOW##_no##_VAL);
597 #define BIT(_x) (1 << (_x))
599 #define ar7240_reg_rmw_set(_reg, _mask) do { \
600 ar7240_reg_wr((_reg), (ar7240_reg_rd((_reg)) | (_mask))); \
601 ar7240_reg_rd((_reg)); \
604 #define ar7240_reg_rmw_clear(_reg, _mask) do { \
605 ar7240_reg_wr((_reg), (ar7240_reg_rd((_reg)) & ~(_mask))); \
606 ar7240_reg_rd((_reg)); \
609 #define ar7240_get_bit(_reg, _bit) (ar7240_reg_rd((_reg)) & (1 << (_bit)))
611 #define ar7240_flush_ge(_unit) do { \
612 u32 reg = (_unit) ? AR7240_DDR_GE1_FLUSH : AR7240_DDR_GE0_FLUSH; \
613 ar7240_reg_wr(reg, 1); \
614 while((ar7240_reg_rd(reg) & 0x1)); \
615 ar7240_reg_wr(reg, 1); \
616 while((ar7240_reg_rd(reg) & 0x1)); \
619 #define ar7240_flush_pci() do { \
620 ar7240_reg_wr(AR7240_DDR_PCI_FLUSH, 1); \
621 while((ar7240_reg_rd(AR7240_DDR_PCI_FLUSH) & 0x1)); \
622 ar7240_reg_wr(AR7240_DDR_PCI_FLUSH, 1); \
623 while((ar7240_reg_rd(AR7240_DDR_PCI_FLUSH) & 0x1)); \
626 #endif /*__ASSEMBLY*/