2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <asm/mipsregs.h>
22 #include <asm/addrspace.h>
23 #include <asm/types.h>
24 #include <linux/types.h>
25 #endif /* __ASSEMBLY__ */
30 #define is_qca953x() (1)
34 #define CPU_PLL_CONFIG_UPDATING_MSB 31
35 #define CPU_PLL_CONFIG_UPDATING_LSB 31
36 #define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
37 #define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
38 #define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
39 #define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1
40 #define CPU_PLL_CONFIG_PLLPWD_MSB 30
41 #define CPU_PLL_CONFIG_PLLPWD_LSB 30
42 #define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
43 #define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
44 #define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
45 #define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
46 #define CPU_PLL_CONFIG_SPARE_MSB 29
47 #define CPU_PLL_CONFIG_SPARE_LSB 22
48 #define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
49 #define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
50 #define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
51 #define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0
52 #define CPU_PLL_CONFIG_OUTDIV_MSB 21
53 #define CPU_PLL_CONFIG_OUTDIV_LSB 19
54 #define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
55 #define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
56 #define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
57 #define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
58 #define CPU_PLL_CONFIG_RANGE_MSB 18
59 #define CPU_PLL_CONFIG_RANGE_LSB 17
60 #define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
61 #define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
62 #define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
63 #define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3
64 #define CPU_PLL_CONFIG_REFDIV_MSB 16
65 #define CPU_PLL_CONFIG_REFDIV_LSB 12
66 #define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
67 #define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
68 #define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
69 #define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2
70 #define CPU_PLL_CONFIG_NINT_MSB 11
71 #define CPU_PLL_CONFIG_NINT_LSB 6
72 #define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
73 #define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
74 #define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
75 #define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20
76 #define CPU_PLL_CONFIG_NFRAC_MSB 5
77 #define CPU_PLL_CONFIG_NFRAC_LSB 0
78 #define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
79 #define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
80 #define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
81 #define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16
82 #define CPU_PLL_CONFIG_ADDRESS 0x18050000
83 #define DDR_PLL_CONFIG_UPDATING_MSB 31
84 #define DDR_PLL_CONFIG_UPDATING_LSB 31
85 #define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
86 #define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
87 #define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
88 #define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1
89 #define DDR_PLL_CONFIG_PLLPWD_MSB 30
90 #define DDR_PLL_CONFIG_PLLPWD_LSB 30
91 #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
92 #define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
93 #define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
94 #define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
95 #define DDR_PLL_CONFIG_SPARE_MSB 29
96 #define DDR_PLL_CONFIG_SPARE_LSB 26
97 #define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
98 #define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
99 #define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
100 #define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0
101 #define DDR_PLL_CONFIG_OUTDIV_MSB 25
102 #define DDR_PLL_CONFIG_OUTDIV_LSB 23
103 #define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
104 #define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
105 #define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
106 #define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
107 #define DDR_PLL_CONFIG_RANGE_MSB 22
108 #define DDR_PLL_CONFIG_RANGE_LSB 21
109 #define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
110 #define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
111 #define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
112 #define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3
113 #define DDR_PLL_CONFIG_REFDIV_MSB 20
114 #define DDR_PLL_CONFIG_REFDIV_LSB 16
115 #define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
116 #define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
117 #define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
118 #define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2
119 #define DDR_PLL_CONFIG_NINT_MSB 15
120 #define DDR_PLL_CONFIG_NINT_LSB 10
121 #define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
122 #define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
123 #define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
124 #define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20
125 #define DDR_PLL_CONFIG_NFRAC_MSB 9
126 #define DDR_PLL_CONFIG_NFRAC_LSB 0
127 #define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
128 #define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
129 #define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
130 #define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512
131 #define DDR_PLL_CONFIG_ADDRESS 0x18050004
133 #define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
134 #define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
135 #define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
136 #define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
137 #define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
138 #define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1
139 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
140 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
141 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
142 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
143 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
144 #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0
145 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20
146 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
147 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
148 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB)
149 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
150 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1
151 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19
152 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
153 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
154 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB)
155 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
156 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1
157 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18
158 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
159 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
160 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB)
161 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
162 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1
163 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17
164 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
165 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
166 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB)
167 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
168 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1
169 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16
170 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
171 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
172 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB)
173 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
174 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1
175 #define DDR_CTL_CONFIG_SPARE_MSB 13
176 #define DDR_CTL_CONFIG_SPARE_LSB 7
177 #define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80
178 #define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
179 #define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
180 #define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0
181 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6
182 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
183 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
184 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB)
185 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
186 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0
187 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4
188 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4
189 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010
190 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB)
191 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK)
192 #define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0
193 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3
194 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3
195 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008
196 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB)
197 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK)
198 #define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0
199 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2
200 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
201 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
202 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB)
203 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
204 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0
205 #define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
206 #define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
207 #define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
208 #define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
209 #define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
210 #define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1
211 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0
212 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0
213 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001
214 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB)
215 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK)
216 #define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0
217 #define DDR_CTL_CONFIG_ADDRESS 0x18000108
219 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31
220 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31
221 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000
222 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB)
223 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK)
224 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0
225 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30
226 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30
227 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000
228 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB)
229 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK)
230 #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0
231 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29
232 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29
233 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000
234 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB)
235 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK)
236 #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0
237 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28
238 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28
239 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000
240 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB)
241 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK)
242 #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1
243 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27
244 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27
245 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000
246 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB)
247 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK)
248 #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0
249 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MSB 16
250 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB 16
251 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK 0x00010000
252 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB)
253 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK)
254 #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_RESET 0x0 // 0
255 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MSB 15
256 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB 15
257 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK 0x00008000
258 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB)
259 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK)
260 #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_RESET 0x0 // 0
261 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14
262 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13
263 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000
264 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB)
265 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK)
266 #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0
267 #define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12
268 #define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8
269 #define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00
270 #define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB)
271 #define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK)
272 #define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1
273 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6
274 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5
275 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060
276 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB)
277 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK)
278 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0
279 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4
280 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0
281 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f
282 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB)
283 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK)
284 #define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1
285 #define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118
287 #define DDR2_CONFIG_DDR2_TWL_MSB 13
288 #define DDR2_CONFIG_DDR2_TWL_LSB 10
289 #define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
290 #define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
291 #define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
292 #define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1
293 #define DDR2_CONFIG_DDR2_ODT_MSB 9
294 #define DDR2_CONFIG_DDR2_ODT_LSB 9
295 #define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
296 #define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
297 #define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
298 #define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1
299 #define DDR2_CONFIG_TFAW_MSB 7
300 #define DDR2_CONFIG_TFAW_LSB 2
301 #define DDR2_CONFIG_TFAW_MASK 0x000000fc
302 #define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
303 #define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
304 #define DDR2_CONFIG_TFAW_RESET 0x16 // 22
305 #define DDR2_CONFIG_ENABLE_DDR2_MSB 0
306 #define DDR2_CONFIG_ENABLE_DDR2_LSB 0
307 #define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
308 #define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
309 #define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
310 #define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0
311 #define DDR2_CONFIG_ADDRESS 0x180000b8
313 #define DDR_CONTROL_EMR3S_MSB 5
314 #define DDR_CONTROL_EMR3S_LSB 5
315 #define DDR_CONTROL_EMR3S_MASK 0x00000020
316 #define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB)
317 #define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK)
318 #define DDR_CONTROL_EMR3S_RESET 0x0 // 0
319 #define DDR_CONTROL_EMR2S_MSB 4
320 #define DDR_CONTROL_EMR2S_LSB 4
321 #define DDR_CONTROL_EMR2S_MASK 0x00000010
322 #define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB)
323 #define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK)
324 #define DDR_CONTROL_EMR2S_RESET 0x0 // 0
325 #define DDR_CONTROL_PREA_MSB 3
326 #define DDR_CONTROL_PREA_LSB 3
327 #define DDR_CONTROL_PREA_MASK 0x00000008
328 #define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB)
329 #define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK)
330 #define DDR_CONTROL_PREA_RESET 0x0 // 0
331 #define DDR_CONTROL_REF_MSB 2
332 #define DDR_CONTROL_REF_LSB 2
333 #define DDR_CONTROL_REF_MASK 0x00000004
334 #define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB)
335 #define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK)
336 #define DDR_CONTROL_REF_RESET 0x0 // 0
337 #define DDR_CONTROL_EMRS_MSB 1
338 #define DDR_CONTROL_EMRS_LSB 1
339 #define DDR_CONTROL_EMRS_MASK 0x00000002
340 #define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB)
341 #define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK)
342 #define DDR_CONTROL_EMRS_RESET 0x0 // 0
343 #define DDR_CONTROL_MRS_MSB 0
344 #define DDR_CONTROL_MRS_LSB 0
345 #define DDR_CONTROL_MRS_MASK 0x00000001
346 #define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB)
347 #define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK)
348 #define DDR_CONTROL_MRS_RESET 0x0 // 0
349 #define DDR_CONTROL_ADDRESS 0x18000010
351 #define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
352 #define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
353 #define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
354 #define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
355 #define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
356 #define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0
357 #define DDR_CONFIG_OPEN_PAGE_MSB 30
358 #define DDR_CONFIG_OPEN_PAGE_LSB 30
359 #define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
360 #define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
361 #define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
362 #define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1
363 #define DDR_CONFIG_CAS_LATENCY_MSB 29
364 #define DDR_CONFIG_CAS_LATENCY_LSB 27
365 #define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
366 #define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
367 #define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
368 #define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6
369 #define DDR_CONFIG_TMRD_MSB 26
370 #define DDR_CONFIG_TMRD_LSB 23
371 #define DDR_CONFIG_TMRD_MASK 0x07800000
372 #define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
373 #define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
374 #define DDR_CONFIG_TMRD_RESET 0xf // 15
375 #define DDR_CONFIG_TRFC_MSB 22
376 #define DDR_CONFIG_TRFC_LSB 17
377 #define DDR_CONFIG_TRFC_MASK 0x007e0000
378 #define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
379 #define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
380 #define DDR_CONFIG_TRFC_RESET 0x24 // 36
381 #define DDR_CONFIG_TRRD_MSB 16
382 #define DDR_CONFIG_TRRD_LSB 13
383 #define DDR_CONFIG_TRRD_MASK 0x0001e000
384 #define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
385 #define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
386 #define DDR_CONFIG_TRRD_RESET 0x4 // 4
387 #define DDR_CONFIG_TRP_MSB 12
388 #define DDR_CONFIG_TRP_LSB 9
389 #define DDR_CONFIG_TRP_MASK 0x00001e00
390 #define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
391 #define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
392 #define DDR_CONFIG_TRP_RESET 0x6 // 6
393 #define DDR_CONFIG_TRCD_MSB 8
394 #define DDR_CONFIG_TRCD_LSB 5
395 #define DDR_CONFIG_TRCD_MASK 0x000001e0
396 #define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
397 #define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
398 #define DDR_CONFIG_TRCD_RESET 0x6 // 6
399 #define DDR_CONFIG_TRAS_MSB 4
400 #define DDR_CONFIG_TRAS_LSB 0
401 #define DDR_CONFIG_TRAS_MASK 0x0000001f
402 #define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
403 #define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
404 #define DDR_CONFIG_TRAS_RESET 0x10 // 16
405 #define DDR_CONFIG_ADDRESS 0x18000000
407 #define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
408 #define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
409 #define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
410 #define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
411 #define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
412 #define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1
413 #define DDR_CONFIG2_SWAP_A26_A27_MSB 30
414 #define DDR_CONFIG2_SWAP_A26_A27_LSB 30
415 #define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
416 #define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB)
417 #define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
418 #define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0
419 #define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
420 #define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
421 #define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
422 #define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
423 #define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
424 #define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6
425 #define DDR_CONFIG2_TWTR_MSB 25
426 #define DDR_CONFIG2_TWTR_LSB 21
427 #define DDR_CONFIG2_TWTR_MASK 0x03e00000
428 #define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
429 #define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
430 #define DDR_CONFIG2_TWTR_RESET 0xe // 14
431 #define DDR_CONFIG2_TRTP_MSB 20
432 #define DDR_CONFIG2_TRTP_LSB 17
433 #define DDR_CONFIG2_TRTP_MASK 0x001e0000
434 #define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
435 #define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
436 #define DDR_CONFIG2_TRTP_RESET 0x8 // 8
437 #define DDR_CONFIG2_TRTW_MSB 16
438 #define DDR_CONFIG2_TRTW_LSB 12
439 #define DDR_CONFIG2_TRTW_MASK 0x0001f000
440 #define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
441 #define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
442 #define DDR_CONFIG2_TRTW_RESET 0x10 // 16
443 #define DDR_CONFIG2_TWR_MSB 11
444 #define DDR_CONFIG2_TWR_LSB 8
445 #define DDR_CONFIG2_TWR_MASK 0x00000f00
446 #define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
447 #define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
448 #define DDR_CONFIG2_TWR_RESET 0x6 // 6
449 #define DDR_CONFIG2_CKE_MSB 7
450 #define DDR_CONFIG2_CKE_LSB 7
451 #define DDR_CONFIG2_CKE_MASK 0x00000080
452 #define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
453 #define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
454 #define DDR_CONFIG2_CKE_RESET 0x0 // 0
455 #define DDR_CONFIG2_PHASE_SELECT_MSB 6
456 #define DDR_CONFIG2_PHASE_SELECT_LSB 6
457 #define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
458 #define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
459 #define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
460 #define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0
461 #define DDR_CONFIG2_CNTL_OE_EN_MSB 5
462 #define DDR_CONFIG2_CNTL_OE_EN_LSB 5
463 #define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
464 #define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
465 #define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
466 #define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1
467 #define DDR_CONFIG2_BURST_TYPE_MSB 4
468 #define DDR_CONFIG2_BURST_TYPE_LSB 4
469 #define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
470 #define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
471 #define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
472 #define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0
473 #define DDR_CONFIG2_BURST_LENGTH_MSB 3
474 #define DDR_CONFIG2_BURST_LENGTH_LSB 0
475 #define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
476 #define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
477 #define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
478 #define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8
479 #define DDR_CONFIG2_ADDRESS 0x18000004
481 #define DDR_CONFIG_3_SPARE_MSB 31
482 #define DDR_CONFIG_3_SPARE_LSB 4
483 #define DDR_CONFIG_3_SPARE_MASK 0xfffffff0
484 #define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB)
485 #define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK)
486 #define DDR_CONFIG_3_SPARE_RESET 0x0 // 0
487 #define DDR_CONFIG_3_TWR_MSB_MSB 3
488 #define DDR_CONFIG_3_TWR_MSB_LSB 3
489 #define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008
490 #define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB)
491 #define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK)
492 #define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0
493 #define DDR_CONFIG_3_TRAS_MSB_MSB 2
494 #define DDR_CONFIG_3_TRAS_MSB_LSB 2
495 #define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004
496 #define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB)
497 #define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK)
498 #define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0
499 #define DDR_CONFIG_3_TRFC_LSB_MSB 1
500 #define DDR_CONFIG_3_TRFC_LSB_LSB 0
501 #define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003
502 #define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB)
503 #define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK)
504 #define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0
505 #define DDR_CONFIG_3_ADDRESS 0x1800015c
507 #define DDR_MODE_REGISTER_VALUE_MSB 13
508 #define DDR_MODE_REGISTER_VALUE_LSB 0
509 #define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff
510 #define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB)
511 #define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK)
512 #define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307
513 #define DDR_MODE_REGISTER_ADDRESS 0x18000008
515 #define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13
516 #define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0
517 #define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff
518 #define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB)
519 #define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK)
520 #define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2
521 #define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c
523 #define DDR_REFRESH_ENABLE_MSB 14
524 #define DDR_REFRESH_ENABLE_LSB 14
525 #define DDR_REFRESH_ENABLE_MASK 0x00004000
526 #define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB)
527 #define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK)
528 #define DDR_REFRESH_ENABLE_RESET 0x0 // 0
529 #define DDR_REFRESH_PERIOD_MSB 13
530 #define DDR_REFRESH_PERIOD_LSB 0
531 #define DDR_REFRESH_PERIOD_MASK 0x00003fff
532 #define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB)
533 #define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK)
534 #define DDR_REFRESH_PERIOD_RESET 0x12c // 300
535 #define DDR_REFRESH_ADDRESS 0x18000014
537 #define BB_DPLL2_LOCAL_PLL_MSB 31
538 #define BB_DPLL2_LOCAL_PLL_LSB 31
539 #define BB_DPLL2_LOCAL_PLL_MASK 0x80000000
540 #define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB)
541 #define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK)
542 #define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0
543 #define BB_DPLL2_KI_MSB 30
544 #define BB_DPLL2_KI_LSB 29
545 #define BB_DPLL2_KI_MASK 0x60000000
546 #define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB)
547 #define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK)
548 #define BB_DPLL2_KI_RESET 0x2 // 2
549 #define BB_DPLL2_KD_MSB 28
550 #define BB_DPLL2_KD_LSB 25
551 #define BB_DPLL2_KD_MASK 0x1e000000
552 #define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB)
553 #define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK)
554 #define BB_DPLL2_KD_RESET 0xa // 10
555 #define BB_DPLL2_EN_NEGTRIG_MSB 24
556 #define BB_DPLL2_EN_NEGTRIG_LSB 24
557 #define BB_DPLL2_EN_NEGTRIG_MASK 0x01000000
558 #define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB)
559 #define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK)
560 #define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
561 #define BB_DPLL2_SEL_1SDM_MSB 23
562 #define BB_DPLL2_SEL_1SDM_LSB 23
563 #define BB_DPLL2_SEL_1SDM_MASK 0x00800000
564 #define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB)
565 #define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK)
566 #define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0
567 #define BB_DPLL2_PLL_PWD_MSB 22
568 #define BB_DPLL2_PLL_PWD_LSB 22
569 #define BB_DPLL2_PLL_PWD_MASK 0x00400000
570 #define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB)
571 #define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK)
572 #define BB_DPLL2_PLL_PWD_RESET 0x1 // 1
573 #define BB_DPLL2_OUTDIV_MSB 21
574 #define BB_DPLL2_OUTDIV_LSB 19
575 #define BB_DPLL2_OUTDIV_MASK 0x00380000
576 #define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB)
577 #define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK)
578 #define BB_DPLL2_OUTDIV_RESET 0x1 // 1
579 #define BB_DPLL2_PHASE_SHIFT_MSB 18
580 #define BB_DPLL2_PHASE_SHIFT_LSB 12
581 #define BB_DPLL2_PHASE_SHIFT_MASK 0x0007f000
582 #define BB_DPLL2_PHASE_SHIFT_GET(x) (((x) & BB_DPLL2_PHASE_SHIFT_MASK) >> BB_DPLL2_PHASE_SHIFT_LSB)
583 #define BB_DPLL2_PHASE_SHIFT_SET(x) (((x) << BB_DPLL2_PHASE_SHIFT_LSB) & BB_DPLL2_PHASE_SHIFT_MASK)
584 #define BB_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
585 #define BB_DPLL2_TESTIN_MSB 11
586 #define BB_DPLL2_TESTIN_LSB 2
587 #define BB_DPLL2_TESTIN_MASK 0x00000ffc
588 #define BB_DPLL2_TESTIN_GET(x) (((x) & BB_DPLL2_TESTIN_MASK) >> BB_DPLL2_TESTIN_LSB)
589 #define BB_DPLL2_TESTIN_SET(x) (((x) << BB_DPLL2_TESTIN_LSB) & BB_DPLL2_TESTIN_MASK)
590 #define BB_DPLL2_TESTIN_RESET 0x0 // 0
591 #define BB_DPLL2_SEL_COUNT_MSB 1
592 #define BB_DPLL2_SEL_COUNT_LSB 1
593 #define BB_DPLL2_SEL_COUNT_MASK 0x00000002
594 #define BB_DPLL2_SEL_COUNT_GET(x) (((x) & BB_DPLL2_SEL_COUNT_MASK) >> BB_DPLL2_SEL_COUNT_LSB)
595 #define BB_DPLL2_SEL_COUNT_SET(x) (((x) << BB_DPLL2_SEL_COUNT_LSB) & BB_DPLL2_SEL_COUNT_MASK)
596 #define BB_DPLL2_SEL_COUNT_RESET 0x0 // 0
597 #define BB_DPLL2_RESET_TEST_MSB 0
598 #define BB_DPLL2_RESET_TEST_LSB 0
599 #define BB_DPLL2_RESET_TEST_MASK 0x00000001
600 #define BB_DPLL2_RESET_TEST_GET(x) (((x) & BB_DPLL2_RESET_TEST_MASK) >> BB_DPLL2_RESET_TEST_LSB)
601 #define BB_DPLL2_RESET_TEST_SET(x) (((x) << BB_DPLL2_RESET_TEST_LSB) & BB_DPLL2_RESET_TEST_MASK)
602 #define BB_DPLL2_RESET_TEST_RESET 0x0 // 0
603 #define BB_DPLL2_ADDRESS 0x18116184
605 #define PCIe_DPLL2_LOCAL_PLL_MSB 31
606 #define PCIe_DPLL2_LOCAL_PLL_LSB 31
607 #define PCIe_DPLL2_LOCAL_PLL_MASK 0x80000000
608 #define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB)
609 #define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK)
610 #define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0
611 #define PCIe_DPLL2_KI_MSB 30
612 #define PCIe_DPLL2_KI_LSB 29
613 #define PCIe_DPLL2_KI_MASK 0x60000000
614 #define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB)
615 #define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK)
616 #define PCIe_DPLL2_KI_RESET 0x2 // 2
617 #define PCIe_DPLL2_KD_MSB 28
618 #define PCIe_DPLL2_KD_LSB 25
619 #define PCIe_DPLL2_KD_MASK 0x1e000000
620 #define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB)
621 #define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK)
622 #define PCIe_DPLL2_KD_RESET 0xa // 10
623 #define PCIe_DPLL2_EN_NEGTRIG_MSB 24
624 #define PCIe_DPLL2_EN_NEGTRIG_LSB 24
625 #define PCIe_DPLL2_EN_NEGTRIG_MASK 0x01000000
626 #define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB)
627 #define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK)
628 #define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
629 #define PCIe_DPLL2_SEL_1SDM_MSB 23
630 #define PCIe_DPLL2_SEL_1SDM_LSB 23
631 #define PCIe_DPLL2_SEL_1SDM_MASK 0x00800000
632 #define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB)
633 #define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK)
634 #define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0
635 #define PCIe_DPLL2_PLL_PWD_MSB 22
636 #define PCIe_DPLL2_PLL_PWD_LSB 22
637 #define PCIe_DPLL2_PLL_PWD_MASK 0x00400000
638 #define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB)
639 #define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK)
640 #define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1
641 #define PCIe_DPLL2_OUTDIV_MSB 21
642 #define PCIe_DPLL2_OUTDIV_LSB 19
643 #define PCIe_DPLL2_OUTDIV_MASK 0x00380000
644 #define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB)
645 #define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK)
646 #define PCIe_DPLL2_OUTDIV_RESET 0x1 // 1
647 #define PCIe_DPLL2_PHASE_SHIFT_MSB 18
648 #define PCIe_DPLL2_PHASE_SHIFT_LSB 12
649 #define PCIe_DPLL2_PHASE_SHIFT_MASK 0x0007f000
650 #define PCIe_DPLL2_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL2_PHASE_SHIFT_MASK) >> PCIe_DPLL2_PHASE_SHIFT_LSB)
651 #define PCIe_DPLL2_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL2_PHASE_SHIFT_LSB) & PCIe_DPLL2_PHASE_SHIFT_MASK)
652 #define PCIe_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
653 #define PCIe_DPLL2_TESTIN_MSB 11
654 #define PCIe_DPLL2_TESTIN_LSB 2
655 #define PCIe_DPLL2_TESTIN_MASK 0x00000ffc
656 #define PCIe_DPLL2_TESTIN_GET(x) (((x) & PCIe_DPLL2_TESTIN_MASK) >> PCIe_DPLL2_TESTIN_LSB)
657 #define PCIe_DPLL2_TESTIN_SET(x) (((x) << PCIe_DPLL2_TESTIN_LSB) & PCIe_DPLL2_TESTIN_MASK)
658 #define PCIe_DPLL2_TESTIN_RESET 0x0 // 0
659 #define PCIe_DPLL2_SEL_COUNT_MSB 1
660 #define PCIe_DPLL2_SEL_COUNT_LSB 1
661 #define PCIe_DPLL2_SEL_COUNT_MASK 0x00000002
662 #define PCIe_DPLL2_SEL_COUNT_GET(x) (((x) & PCIe_DPLL2_SEL_COUNT_MASK) >> PCIe_DPLL2_SEL_COUNT_LSB)
663 #define PCIe_DPLL2_SEL_COUNT_SET(x) (((x) << PCIe_DPLL2_SEL_COUNT_LSB) & PCIe_DPLL2_SEL_COUNT_MASK)
664 #define PCIe_DPLL2_SEL_COUNT_RESET 0x0 // 0
665 #define PCIe_DPLL2_RESET_TEST_MSB 0
666 #define PCIe_DPLL2_RESET_TEST_LSB 0
667 #define PCIe_DPLL2_RESET_TEST_MASK 0x00000001
668 #define PCIe_DPLL2_RESET_TEST_GET(x) (((x) & PCIe_DPLL2_RESET_TEST_MASK) >> PCIe_DPLL2_RESET_TEST_LSB)
669 #define PCIe_DPLL2_RESET_TEST_SET(x) (((x) << PCIe_DPLL2_RESET_TEST_LSB) & PCIe_DPLL2_RESET_TEST_MASK)
670 #define PCIe_DPLL2_RESET_TEST_RESET 0x0 // 0
671 #define PCIe_DPLL2_ADDRESS 0x18116c04
673 #define DDR_DPLL2_LOCAL_PLL_MSB 31
674 #define DDR_DPLL2_LOCAL_PLL_LSB 31
675 #define DDR_DPLL2_LOCAL_PLL_MASK 0x80000000
676 #define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB)
677 #define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK)
678 #define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0
679 #define DDR_DPLL2_KI_MSB 30
680 #define DDR_DPLL2_KI_LSB 29
681 #define DDR_DPLL2_KI_MASK 0x60000000
682 #define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB)
683 #define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK)
684 #define DDR_DPLL2_KI_RESET 0x2 // 2
685 #define DDR_DPLL2_KD_MSB 28
686 #define DDR_DPLL2_KD_LSB 25
687 #define DDR_DPLL2_KD_MASK 0x1e000000
688 #define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB)
689 #define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK)
690 #define DDR_DPLL2_KD_RESET 0xa // 10
691 #define DDR_DPLL2_EN_NEGTRIG_MSB 24
692 #define DDR_DPLL2_EN_NEGTRIG_LSB 24
693 #define DDR_DPLL2_EN_NEGTRIG_MASK 0x01000000
694 #define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB)
695 #define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK)
696 #define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
697 #define DDR_DPLL2_SEL_1SDM_MSB 23
698 #define DDR_DPLL2_SEL_1SDM_LSB 23
699 #define DDR_DPLL2_SEL_1SDM_MASK 0x00800000
700 #define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB)
701 #define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK)
702 #define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0
703 #define DDR_DPLL2_PLL_PWD_MSB 22
704 #define DDR_DPLL2_PLL_PWD_LSB 22
705 #define DDR_DPLL2_PLL_PWD_MASK 0x00400000
706 #define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB)
707 #define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK)
708 #define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1
709 #define DDR_DPLL2_OUTDIV_MSB 21
710 #define DDR_DPLL2_OUTDIV_LSB 19
711 #define DDR_DPLL2_OUTDIV_MASK 0x00380000
712 #define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB)
713 #define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK)
714 #define DDR_DPLL2_OUTDIV_RESET 0x1 // 1
715 #define DDR_DPLL2_PHASE_SHIFT_MSB 18
716 #define DDR_DPLL2_PHASE_SHIFT_LSB 12
717 #define DDR_DPLL2_PHASE_SHIFT_MASK 0x0007f000
718 #define DDR_DPLL2_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL2_PHASE_SHIFT_MASK) >> DDR_DPLL2_PHASE_SHIFT_LSB)
719 #define DDR_DPLL2_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL2_PHASE_SHIFT_LSB) & DDR_DPLL2_PHASE_SHIFT_MASK)
720 #define DDR_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
721 #define DDR_DPLL2_TESTIN_MSB 11
722 #define DDR_DPLL2_TESTIN_LSB 2
723 #define DDR_DPLL2_TESTIN_MASK 0x00000ffc
724 #define DDR_DPLL2_TESTIN_GET(x) (((x) & DDR_DPLL2_TESTIN_MASK) >> DDR_DPLL2_TESTIN_LSB)
725 #define DDR_DPLL2_TESTIN_SET(x) (((x) << DDR_DPLL2_TESTIN_LSB) & DDR_DPLL2_TESTIN_MASK)
726 #define DDR_DPLL2_TESTIN_RESET 0x0 // 0
727 #define DDR_DPLL2_SEL_COUNT_MSB 1
728 #define DDR_DPLL2_SEL_COUNT_LSB 1
729 #define DDR_DPLL2_SEL_COUNT_MASK 0x00000002
730 #define DDR_DPLL2_SEL_COUNT_GET(x) (((x) & DDR_DPLL2_SEL_COUNT_MASK) >> DDR_DPLL2_SEL_COUNT_LSB)
731 #define DDR_DPLL2_SEL_COUNT_SET(x) (((x) << DDR_DPLL2_SEL_COUNT_LSB) & DDR_DPLL2_SEL_COUNT_MASK)
732 #define DDR_DPLL2_SEL_COUNT_RESET 0x0 // 0
733 #define DDR_DPLL2_RESET_TEST_MSB 0
734 #define DDR_DPLL2_RESET_TEST_LSB 0
735 #define DDR_DPLL2_RESET_TEST_MASK 0x00000001
736 #define DDR_DPLL2_RESET_TEST_GET(x) (((x) & DDR_DPLL2_RESET_TEST_MASK) >> DDR_DPLL2_RESET_TEST_LSB)
737 #define DDR_DPLL2_RESET_TEST_SET(x) (((x) << DDR_DPLL2_RESET_TEST_LSB) & DDR_DPLL2_RESET_TEST_MASK)
738 #define DDR_DPLL2_RESET_TEST_RESET 0x0 // 0
739 #define DDR_DPLL2_ADDRESS 0x18116244
741 #define CPU_DPLL2_LOCAL_PLL_MSB 31
742 #define CPU_DPLL2_LOCAL_PLL_LSB 31
743 #define CPU_DPLL2_LOCAL_PLL_MASK 0x80000000
744 #define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB)
745 #define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK)
746 #define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0
747 #define CPU_DPLL2_KI_MSB 30
748 #define CPU_DPLL2_KI_LSB 29
749 #define CPU_DPLL2_KI_MASK 0x60000000
750 #define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB)
751 #define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK)
752 #define CPU_DPLL2_KI_RESET 0x2 // 2
753 #define CPU_DPLL2_KD_MSB 28
754 #define CPU_DPLL2_KD_LSB 25
755 #define CPU_DPLL2_KD_MASK 0x1e000000
756 #define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB)
757 #define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK)
758 #define CPU_DPLL2_KD_RESET 0xa // 10
759 #define CPU_DPLL2_EN_NEGTRIG_MSB 24
760 #define CPU_DPLL2_EN_NEGTRIG_LSB 24
761 #define CPU_DPLL2_EN_NEGTRIG_MASK 0x01000000
762 #define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB)
763 #define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK)
764 #define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
765 #define CPU_DPLL2_SEL_1SDM_MSB 23
766 #define CPU_DPLL2_SEL_1SDM_LSB 23
767 #define CPU_DPLL2_SEL_1SDM_MASK 0x00800000
768 #define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB)
769 #define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK)
770 #define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0
771 #define CPU_DPLL2_PLL_PWD_MSB 22
772 #define CPU_DPLL2_PLL_PWD_LSB 22
773 #define CPU_DPLL2_PLL_PWD_MASK 0x00400000
774 #define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB)
775 #define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK)
776 #define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1
777 #define CPU_DPLL2_OUTDIV_MSB 21
778 #define CPU_DPLL2_OUTDIV_LSB 19
779 #define CPU_DPLL2_OUTDIV_MASK 0x00380000
780 #define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB)
781 #define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK)
782 #define CPU_DPLL2_OUTDIV_RESET 0x1 // 1
783 #define CPU_DPLL2_PHASE_SHIFT_MSB 18
784 #define CPU_DPLL2_PHASE_SHIFT_LSB 12
785 #define CPU_DPLL2_PHASE_SHIFT_MASK 0x0007f000
786 #define CPU_DPLL2_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL2_PHASE_SHIFT_MASK) >> CPU_DPLL2_PHASE_SHIFT_LSB)
787 #define CPU_DPLL2_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL2_PHASE_SHIFT_LSB) & CPU_DPLL2_PHASE_SHIFT_MASK)
788 #define CPU_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
789 #define CPU_DPLL2_TESTIN_MSB 11
790 #define CPU_DPLL2_TESTIN_LSB 2
791 #define CPU_DPLL2_TESTIN_MASK 0x00000ffc
792 #define CPU_DPLL2_TESTIN_GET(x) (((x) & CPU_DPLL2_TESTIN_MASK) >> CPU_DPLL2_TESTIN_LSB)
793 #define CPU_DPLL2_TESTIN_SET(x) (((x) << CPU_DPLL2_TESTIN_LSB) & CPU_DPLL2_TESTIN_MASK)
794 #define CPU_DPLL2_TESTIN_RESET 0x0 // 0
795 #define CPU_DPLL2_SEL_COUNT_MSB 1
796 #define CPU_DPLL2_SEL_COUNT_LSB 1
797 #define CPU_DPLL2_SEL_COUNT_MASK 0x00000002
798 #define CPU_DPLL2_SEL_COUNT_GET(x) (((x) & CPU_DPLL2_SEL_COUNT_MASK) >> CPU_DPLL2_SEL_COUNT_LSB)
799 #define CPU_DPLL2_SEL_COUNT_SET(x) (((x) << CPU_DPLL2_SEL_COUNT_LSB) & CPU_DPLL2_SEL_COUNT_MASK)
800 #define CPU_DPLL2_SEL_COUNT_RESET 0x0 // 0
801 #define CPU_DPLL2_RESET_TEST_MSB 0
802 #define CPU_DPLL2_RESET_TEST_LSB 0
803 #define CPU_DPLL2_RESET_TEST_MASK 0x00000001
804 #define CPU_DPLL2_RESET_TEST_GET(x) (((x) & CPU_DPLL2_RESET_TEST_MASK) >> CPU_DPLL2_RESET_TEST_LSB)
805 #define CPU_DPLL2_RESET_TEST_SET(x) (((x) << CPU_DPLL2_RESET_TEST_LSB) & CPU_DPLL2_RESET_TEST_MASK)
806 #define CPU_DPLL2_RESET_TEST_RESET 0x0 // 0
807 #define CPU_DPLL2_ADDRESS 0x181161c4
809 #define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
811 #define TAP_CONTROL_0_ADDRESS 0x1800001c
812 #define TAP_CONTROL_1_ADDRESS 0x18000020
813 #define TAP_CONTROL_2_ADDRESS 0x18000024
814 #define TAP_CONTROL_3_ADDRESS 0x18000028
816 #define DDR_BURST_CPU_PRIORITY_MSB 31
817 #define DDR_BURST_CPU_PRIORITY_LSB 31
818 #define DDR_BURST_CPU_PRIORITY_MASK 0x80000000
819 #define DDR_BURST_CPU_PRIORITY_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB)
820 #define DDR_BURST_CPU_PRIORITY_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK)
821 #define DDR_BURST_CPU_PRIORITY_RESET 0x0 // 0
822 #define DDR_BURST_CPU_PRIORITY_BE_MSB 30
823 #define DDR_BURST_CPU_PRIORITY_BE_LSB 30
824 #define DDR_BURST_CPU_PRIORITY_BE_MASK 0x40000000
825 #define DDR_BURST_CPU_PRIORITY_BE_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB)
826 #define DDR_BURST_CPU_PRIORITY_BE_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK)
827 #define DDR_BURST_CPU_PRIORITY_BE_RESET 0x1 // 1
828 #define DDR_BURST_ENABLE_RWP_MASK_MSB 29
829 #define DDR_BURST_ENABLE_RWP_MASK_LSB 28
830 #define DDR_BURST_ENABLE_RWP_MASK_MASK 0x30000000
831 #define DDR_BURST_ENABLE_RWP_MASK_GET(x) (((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB)
832 #define DDR_BURST_ENABLE_RWP_MASK_SET(x) (((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK)
833 #define DDR_BURST_ENABLE_RWP_MASK_RESET 0x3 // 3
834 #define DDR_BURST_MAX_WRITE_BURST_MSB 27
835 #define DDR_BURST_MAX_WRITE_BURST_LSB 24
836 #define DDR_BURST_MAX_WRITE_BURST_MASK 0x0f000000
837 #define DDR_BURST_MAX_WRITE_BURST_GET(x) (((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB)
838 #define DDR_BURST_MAX_WRITE_BURST_SET(x) (((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK)
839 #define DDR_BURST_MAX_WRITE_BURST_RESET 0x4 // 4
840 #define DDR_BURST_MAX_READ_BURST_MSB 23
841 #define DDR_BURST_MAX_READ_BURST_LSB 20
842 #define DDR_BURST_MAX_READ_BURST_MASK 0x00f00000
843 #define DDR_BURST_MAX_READ_BURST_GET(x) (((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB)
844 #define DDR_BURST_MAX_READ_BURST_SET(x) (((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK)
845 #define DDR_BURST_MAX_READ_BURST_RESET 0x4 // 4
846 #define DDR_BURST_CPU_MAX_BL_MSB 19
847 #define DDR_BURST_CPU_MAX_BL_LSB 16
848 #define DDR_BURST_CPU_MAX_BL_MASK 0x000f0000
849 #define DDR_BURST_CPU_MAX_BL_GET(x) (((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB)
850 #define DDR_BURST_CPU_MAX_BL_SET(x) (((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK)
851 #define DDR_BURST_CPU_MAX_BL_RESET 0x3 // 3
852 #define DDR_BURST_USB_MAX_BL_MSB 15
853 #define DDR_BURST_USB_MAX_BL_LSB 12
854 #define DDR_BURST_USB_MAX_BL_MASK 0x0000f000
855 #define DDR_BURST_USB_MAX_BL_GET(x) (((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB)
856 #define DDR_BURST_USB_MAX_BL_SET(x) (((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK)
857 #define DDR_BURST_USB_MAX_BL_RESET 0x4 // 4
858 #define DDR_BURST_PCIE_MAX_BL_MSB 11
859 #define DDR_BURST_PCIE_MAX_BL_LSB 8
860 #define DDR_BURST_PCIE_MAX_BL_MASK 0x00000f00
861 #define DDR_BURST_PCIE_MAX_BL_GET(x) (((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB)
862 #define DDR_BURST_PCIE_MAX_BL_SET(x) (((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK)
863 #define DDR_BURST_PCIE_MAX_BL_RESET 0x3 // 3
864 #define DDR_BURST_GE1_MAX_BL_MSB 7
865 #define DDR_BURST_GE1_MAX_BL_LSB 4
866 #define DDR_BURST_GE1_MAX_BL_MASK 0x000000f0
867 #define DDR_BURST_GE1_MAX_BL_GET(x) (((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB)
868 #define DDR_BURST_GE1_MAX_BL_SET(x) (((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK)
869 #define DDR_BURST_GE1_MAX_BL_RESET 0x3 // 3
870 #define DDR_BURST_GE0_MAX_BL_MSB 3
871 #define DDR_BURST_GE0_MAX_BL_LSB 0
872 #define DDR_BURST_GE0_MAX_BL_MASK 0x0000000f
873 #define DDR_BURST_GE0_MAX_BL_GET(x) (((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB)
874 #define DDR_BURST_GE0_MAX_BL_SET(x) (((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK)
875 #define DDR_BURST_GE0_MAX_BL_RESET 0x3 // 3
876 #define DDR_BURST_ADDRESS 0x180000c4
878 #define DDR_BURST2_WMAC_MAX_BL_MSB 3
879 #define DDR_BURST2_WMAC_MAX_BL_LSB 0
880 #define DDR_BURST2_WMAC_MAX_BL_MASK 0x0000000f
881 #define DDR_BURST2_WMAC_MAX_BL_GET(x) (((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB)
882 #define DDR_BURST2_WMAC_MAX_BL_SET(x) (((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK)
883 #define DDR_BURST2_WMAC_MAX_BL_RESET 0x3 // 3
884 #define DDR_BURST2_ADDRESS 0x180000c8
886 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB 19
887 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB 0
888 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK 0x000fffff
889 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x) (((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB)
890 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x) (((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK)
891 #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_RESET 0x8000 // 32768
892 #define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc
894 #define PMU1_ADDRESS 0x18116c40
896 #define PMU2_SWREGMSB_MSB 31
897 #define PMU2_SWREGMSB_LSB 22
898 #define PMU2_SWREGMSB_MASK 0xffc00000
899 #define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB)
900 #define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
901 #define PMU2_SWREGMSB_RESET 0x0 // 0
902 #define PMU2_PGM_MSB 21
903 #define PMU2_PGM_LSB 21
904 #define PMU2_PGM_MASK 0x00200000
905 #define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
906 #define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
907 #define PMU2_PGM_RESET 0x0 // 0
908 #define PMU2_LDO_TUNE_MSB 20
909 #define PMU2_LDO_TUNE_LSB 19
910 #define PMU2_LDO_TUNE_MASK 0x00180000
911 #define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
912 #define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
913 #define PMU2_LDO_TUNE_RESET 0x0 // 0
914 #define PMU2_PWDLDO_DDR_MSB 18
915 #define PMU2_PWDLDO_DDR_LSB 18
916 #define PMU2_PWDLDO_DDR_MASK 0x00040000
917 #define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
918 #define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
919 #define PMU2_PWDLDO_DDR_RESET 0x0 // 0
920 #define PMU2_LPOPWD_MSB 17
921 #define PMU2_LPOPWD_LSB 17
922 #define PMU2_LPOPWD_MASK 0x00020000
923 #define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB)
924 #define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK)
925 #define PMU2_LPOPWD_RESET 0x0 // 0
926 #define PMU2_SPARE_MSB 16
927 #define PMU2_SPARE_LSB 0
928 #define PMU2_SPARE_MASK 0x0001ffff
929 #define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB)
930 #define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK)
931 #define PMU2_SPARE_RESET 0x0 // 0
932 #define PMU2_ADDRESS 0x18116c44
934 #define PHY_CTRL0_LOOPBACK_ERR_CNT_MSB 31
935 #define PHY_CTRL0_LOOPBACK_ERR_CNT_LSB 24
936 #define PHY_CTRL0_LOOPBACK_ERR_CNT_MASK 0xff000000
937 #define PHY_CTRL0_LOOPBACK_ERR_CNT_GET(x) (((x) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) >> PHY_CTRL0_LOOPBACK_ERR_CNT_LSB)
938 #define PHY_CTRL0_LOOPBACK_ERR_CNT_SET(x) (((x) << PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK)
939 #define PHY_CTRL0_LOOPBACK_ERR_CNT_RESET 0x0 // 0
940 #define PHY_CTRL0_DIG_LOOPBACK_EN_MSB 23
941 #define PHY_CTRL0_DIG_LOOPBACK_EN_LSB 23
942 #define PHY_CTRL0_DIG_LOOPBACK_EN_MASK 0x00800000
943 #define PHY_CTRL0_DIG_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) >> PHY_CTRL0_DIG_LOOPBACK_EN_LSB)
944 #define PHY_CTRL0_DIG_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_DIG_LOOPBACK_EN_LSB) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK)
945 #define PHY_CTRL0_DIG_LOOPBACK_EN_RESET 0x0 // 0
946 #define PHY_CTRL0_ANA_LOOPBACK_EN_MSB 22
947 #define PHY_CTRL0_ANA_LOOPBACK_EN_LSB 22
948 #define PHY_CTRL0_ANA_LOOPBACK_EN_MASK 0x00400000
949 #define PHY_CTRL0_ANA_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) >> PHY_CTRL0_ANA_LOOPBACK_EN_LSB)
950 #define PHY_CTRL0_ANA_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_ANA_LOOPBACK_EN_LSB) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK)
951 #define PHY_CTRL0_ANA_LOOPBACK_EN_RESET 0x0 // 0
952 #define PHY_CTRL0_TX_PATTERN_EN_MSB 21
953 #define PHY_CTRL0_TX_PATTERN_EN_LSB 21
954 #define PHY_CTRL0_TX_PATTERN_EN_MASK 0x00200000
955 #define PHY_CTRL0_TX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_TX_PATTERN_EN_MASK) >> PHY_CTRL0_TX_PATTERN_EN_LSB)
956 #define PHY_CTRL0_TX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_TX_PATTERN_EN_LSB) & PHY_CTRL0_TX_PATTERN_EN_MASK)
957 #define PHY_CTRL0_TX_PATTERN_EN_RESET 0x0 // 0
958 #define PHY_CTRL0_RX_PATTERN_EN_MSB 20
959 #define PHY_CTRL0_RX_PATTERN_EN_LSB 20
960 #define PHY_CTRL0_RX_PATTERN_EN_MASK 0x00100000
961 #define PHY_CTRL0_RX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_RX_PATTERN_EN_MASK) >> PHY_CTRL0_RX_PATTERN_EN_LSB)
962 #define PHY_CTRL0_RX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_RX_PATTERN_EN_LSB) & PHY_CTRL0_RX_PATTERN_EN_MASK)
963 #define PHY_CTRL0_RX_PATTERN_EN_RESET 0x0 // 0
964 #define PHY_CTRL0_TEST_SPEED_SELECT_MSB 19
965 #define PHY_CTRL0_TEST_SPEED_SELECT_LSB 19
966 #define PHY_CTRL0_TEST_SPEED_SELECT_MASK 0x00080000
967 #define PHY_CTRL0_TEST_SPEED_SELECT_GET(x) (((x) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) >> PHY_CTRL0_TEST_SPEED_SELECT_LSB)
968 #define PHY_CTRL0_TEST_SPEED_SELECT_SET(x) (((x) << PHY_CTRL0_TEST_SPEED_SELECT_LSB) & PHY_CTRL0_TEST_SPEED_SELECT_MASK)
969 #define PHY_CTRL0_TEST_SPEED_SELECT_RESET 0x0 // 0
970 #define PHY_CTRL0_PLL_OVERIDE_MSB 18
971 #define PHY_CTRL0_PLL_OVERIDE_LSB 18
972 #define PHY_CTRL0_PLL_OVERIDE_MASK 0x00040000
973 #define PHY_CTRL0_PLL_OVERIDE_GET(x) (((x) & PHY_CTRL0_PLL_OVERIDE_MASK) >> PHY_CTRL0_PLL_OVERIDE_LSB)
974 #define PHY_CTRL0_PLL_OVERIDE_SET(x) (((x) << PHY_CTRL0_PLL_OVERIDE_LSB) & PHY_CTRL0_PLL_OVERIDE_MASK)
975 #define PHY_CTRL0_PLL_OVERIDE_RESET 0x0 // 0
976 #define PHY_CTRL0_PLL_MOD_MSB 17
977 #define PHY_CTRL0_PLL_MOD_LSB 15
978 #define PHY_CTRL0_PLL_MOD_MASK 0x00038000
979 #define PHY_CTRL0_PLL_MOD_GET(x) (((x) & PHY_CTRL0_PLL_MOD_MASK) >> PHY_CTRL0_PLL_MOD_LSB)
980 #define PHY_CTRL0_PLL_MOD_SET(x) (((x) << PHY_CTRL0_PLL_MOD_LSB) & PHY_CTRL0_PLL_MOD_MASK)
981 #define PHY_CTRL0_PLL_MOD_RESET 0x0 // 0
982 #define PHY_CTRL0_PLL_DIV_MSB 14
983 #define PHY_CTRL0_PLL_DIV_LSB 6
984 #define PHY_CTRL0_PLL_DIV_MASK 0x00007fc0
985 #define PHY_CTRL0_PLL_DIV_GET(x) (((x) & PHY_CTRL0_PLL_DIV_MASK) >> PHY_CTRL0_PLL_DIV_LSB)
986 #define PHY_CTRL0_PLL_DIV_SET(x) (((x) << PHY_CTRL0_PLL_DIV_LSB) & PHY_CTRL0_PLL_DIV_MASK)
987 #define PHY_CTRL0_PLL_DIV_RESET 0x0 // 0
988 #define PHY_CTRL0_PLL_RS_MSB 5
989 #define PHY_CTRL0_PLL_RS_LSB 3
990 #define PHY_CTRL0_PLL_RS_MASK 0x00000038
991 #define PHY_CTRL0_PLL_RS_GET(x) (((x) & PHY_CTRL0_PLL_RS_MASK) >> PHY_CTRL0_PLL_RS_LSB)
992 #define PHY_CTRL0_PLL_RS_SET(x) (((x) << PHY_CTRL0_PLL_RS_LSB) & PHY_CTRL0_PLL_RS_MASK)
993 #define PHY_CTRL0_PLL_RS_RESET 0x2 // 2
994 #define PHY_CTRL0_PLL_ICP_MSB 2
995 #define PHY_CTRL0_PLL_ICP_LSB 0
996 #define PHY_CTRL0_PLL_ICP_MASK 0x00000007
997 #define PHY_CTRL0_PLL_ICP_GET(x) (((x) & PHY_CTRL0_PLL_ICP_MASK) >> PHY_CTRL0_PLL_ICP_LSB)
998 #define PHY_CTRL0_PLL_ICP_SET(x) (((x) << PHY_CTRL0_PLL_ICP_LSB) & PHY_CTRL0_PLL_ICP_MASK)
999 #define PHY_CTRL0_PLL_ICP_RESET 0x5 // 5
1000 #define PHY_CTRL0_ADDRESS 0x18116c80
1001 #define PHY_CTRL0_OFFSET 0x0000
1002 // SW modifiable bits
1003 #define PHY_CTRL0_SW_MASK 0xffffffff
1004 // bits defined at reset
1005 #define PHY_CTRL0_RSTMASK 0xffffffff
1006 // reset value (ignore bits undefined at reset)
1007 #define PHY_CTRL0_RESET 0x00000015
1009 #define PHY_CTRL1_PLL_OBS_MODE_N_MSB 31
1010 #define PHY_CTRL1_PLL_OBS_MODE_N_LSB 31
1011 #define PHY_CTRL1_PLL_OBS_MODE_N_MASK 0x80000000
1012 #define PHY_CTRL1_PLL_OBS_MODE_N_GET(x) (((x) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) >> PHY_CTRL1_PLL_OBS_MODE_N_LSB)
1013 #define PHY_CTRL1_PLL_OBS_MODE_N_SET(x) (((x) << PHY_CTRL1_PLL_OBS_MODE_N_LSB) & PHY_CTRL1_PLL_OBS_MODE_N_MASK)
1014 #define PHY_CTRL1_PLL_OBS_MODE_N_RESET 0x1 // 1
1015 #define PHY_CTRL1_DISABLE_CLK_GATING_MSB 27
1016 #define PHY_CTRL1_DISABLE_CLK_GATING_LSB 27
1017 #define PHY_CTRL1_DISABLE_CLK_GATING_MASK 0x08000000
1018 #define PHY_CTRL1_DISABLE_CLK_GATING_GET(x) (((x) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) >> PHY_CTRL1_DISABLE_CLK_GATING_LSB)
1019 #define PHY_CTRL1_DISABLE_CLK_GATING_SET(x) (((x) << PHY_CTRL1_DISABLE_CLK_GATING_LSB) & PHY_CTRL1_DISABLE_CLK_GATING_MASK)
1020 #define PHY_CTRL1_DISABLE_CLK_GATING_RESET 0x0 // 0
1021 #define PHY_CTRL1_ENABLE_REFCLK_GATE_MSB 26
1022 #define PHY_CTRL1_ENABLE_REFCLK_GATE_LSB 26
1023 #define PHY_CTRL1_ENABLE_REFCLK_GATE_MASK 0x04000000
1024 #define PHY_CTRL1_ENABLE_REFCLK_GATE_GET(x) (((x) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) >> PHY_CTRL1_ENABLE_REFCLK_GATE_LSB)
1025 #define PHY_CTRL1_ENABLE_REFCLK_GATE_SET(x) (((x) << PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK)
1026 #define PHY_CTRL1_ENABLE_REFCLK_GATE_RESET 0x1 // 1
1027 #define PHY_CTRL1_CLKOBS_SEL_MSB 25
1028 #define PHY_CTRL1_CLKOBS_SEL_LSB 23
1029 #define PHY_CTRL1_CLKOBS_SEL_MASK 0x03800000
1030 #define PHY_CTRL1_CLKOBS_SEL_GET(x) (((x) & PHY_CTRL1_CLKOBS_SEL_MASK) >> PHY_CTRL1_CLKOBS_SEL_LSB)
1031 #define PHY_CTRL1_CLKOBS_SEL_SET(x) (((x) << PHY_CTRL1_CLKOBS_SEL_LSB) & PHY_CTRL1_CLKOBS_SEL_MASK)
1032 #define PHY_CTRL1_CLKOBS_SEL_RESET 0x0 // 0
1033 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MSB 22
1034 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB 21
1035 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK 0x00600000
1036 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) >> PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB)
1037 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK)
1038 #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_RESET 0x3 // 3
1039 #define PHY_CTRL1_USE_PLL_LOCKDETECT_MSB 20
1040 #define PHY_CTRL1_USE_PLL_LOCKDETECT_LSB 20
1041 #define PHY_CTRL1_USE_PLL_LOCKDETECT_MASK 0x00100000
1042 #define PHY_CTRL1_USE_PLL_LOCKDETECT_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) >> PHY_CTRL1_USE_PLL_LOCKDETECT_LSB)
1043 #define PHY_CTRL1_USE_PLL_LOCKDETECT_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK)
1044 #define PHY_CTRL1_USE_PLL_LOCKDETECT_RESET 0x0 // 0
1045 #define PHY_CTRL1_TX_PATTERN_SEL_MSB 19
1046 #define PHY_CTRL1_TX_PATTERN_SEL_LSB 18
1047 #define PHY_CTRL1_TX_PATTERN_SEL_MASK 0x000c0000
1048 #define PHY_CTRL1_TX_PATTERN_SEL_GET(x) (((x) & PHY_CTRL1_TX_PATTERN_SEL_MASK) >> PHY_CTRL1_TX_PATTERN_SEL_LSB)
1049 #define PHY_CTRL1_TX_PATTERN_SEL_SET(x) (((x) << PHY_CTRL1_TX_PATTERN_SEL_LSB) & PHY_CTRL1_TX_PATTERN_SEL_MASK)
1050 #define PHY_CTRL1_TX_PATTERN_SEL_RESET 0x0 // 0
1051 #define PHY_CTRL1_FORCE_SUSPEND_MSB 13
1052 #define PHY_CTRL1_FORCE_SUSPEND_LSB 13
1053 #define PHY_CTRL1_FORCE_SUSPEND_MASK 0x00002000
1054 #define PHY_CTRL1_FORCE_SUSPEND_GET(x) (((x) & PHY_CTRL1_FORCE_SUSPEND_MASK) >> PHY_CTRL1_FORCE_SUSPEND_LSB)
1055 #define PHY_CTRL1_FORCE_SUSPEND_SET(x) (((x) << PHY_CTRL1_FORCE_SUSPEND_LSB) & PHY_CTRL1_FORCE_SUSPEND_MASK)
1056 #define PHY_CTRL1_FORCE_SUSPEND_RESET 0x0 // 0
1057 #define PHY_CTRL1_NO_PLL_PWD_MSB 12
1058 #define PHY_CTRL1_NO_PLL_PWD_LSB 12
1059 #define PHY_CTRL1_NO_PLL_PWD_MASK 0x00001000
1060 #define PHY_CTRL1_NO_PLL_PWD_GET(x) (((x) & PHY_CTRL1_NO_PLL_PWD_MASK) >> PHY_CTRL1_NO_PLL_PWD_LSB)
1061 #define PHY_CTRL1_NO_PLL_PWD_SET(x) (((x) << PHY_CTRL1_NO_PLL_PWD_LSB) & PHY_CTRL1_NO_PLL_PWD_MASK)
1062 #define PHY_CTRL1_NO_PLL_PWD_RESET 0x0 // 0
1063 #define PHY_CTRL1_RX_RSVD_MSB 11
1064 #define PHY_CTRL1_RX_RSVD_LSB 9
1065 #define PHY_CTRL1_RX_RSVD_MASK 0x00000e00
1066 #define PHY_CTRL1_RX_RSVD_GET(x) (((x) & PHY_CTRL1_RX_RSVD_MASK) >> PHY_CTRL1_RX_RSVD_LSB)
1067 #define PHY_CTRL1_RX_RSVD_SET(x) (((x) << PHY_CTRL1_RX_RSVD_LSB) & PHY_CTRL1_RX_RSVD_MASK)
1068 #define PHY_CTRL1_RX_RSVD_RESET 0x0 // 0
1069 #define PHY_CTRL1_RX_SELVREF0P25_MSB 8
1070 #define PHY_CTRL1_RX_SELVREF0P25_LSB 8
1071 #define PHY_CTRL1_RX_SELVREF0P25_MASK 0x00000100
1072 #define PHY_CTRL1_RX_SELVREF0P25_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P25_MASK) >> PHY_CTRL1_RX_SELVREF0P25_LSB)
1073 #define PHY_CTRL1_RX_SELVREF0P25_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P25_LSB) & PHY_CTRL1_RX_SELVREF0P25_MASK)
1074 #define PHY_CTRL1_RX_SELVREF0P25_RESET 0x0 // 0
1075 #define PHY_CTRL1_RX_SELVREF0P6_MSB 7
1076 #define PHY_CTRL1_RX_SELVREF0P6_LSB 7
1077 #define PHY_CTRL1_RX_SELVREF0P6_MASK 0x00000080
1078 #define PHY_CTRL1_RX_SELVREF0P6_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P6_MASK) >> PHY_CTRL1_RX_SELVREF0P6_LSB)
1079 #define PHY_CTRL1_RX_SELVREF0P6_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P6_LSB) & PHY_CTRL1_RX_SELVREF0P6_MASK)
1080 #define PHY_CTRL1_RX_SELVREF0P6_RESET 0x1 // 1
1081 #define PHY_CTRL1_RX_SELIR_100M_MSB 6
1082 #define PHY_CTRL1_RX_SELIR_100M_LSB 5
1083 #define PHY_CTRL1_RX_SELIR_100M_MASK 0x00000060
1084 #define PHY_CTRL1_RX_SELIR_100M_GET(x) (((x) & PHY_CTRL1_RX_SELIR_100M_MASK) >> PHY_CTRL1_RX_SELIR_100M_LSB)
1085 #define PHY_CTRL1_RX_SELIR_100M_SET(x) (((x) << PHY_CTRL1_RX_SELIR_100M_LSB) & PHY_CTRL1_RX_SELIR_100M_MASK)
1086 #define PHY_CTRL1_RX_SELIR_100M_RESET 0x0 // 0
1087 #define PHY_CTRL1_RX_LOWR_PDET_MSB 4
1088 #define PHY_CTRL1_RX_LOWR_PDET_LSB 4
1089 #define PHY_CTRL1_RX_LOWR_PDET_MASK 0x00000010
1090 #define PHY_CTRL1_RX_LOWR_PDET_GET(x) (((x) & PHY_CTRL1_RX_LOWR_PDET_MASK) >> PHY_CTRL1_RX_LOWR_PDET_LSB)
1091 #define PHY_CTRL1_RX_LOWR_PDET_SET(x) (((x) << PHY_CTRL1_RX_LOWR_PDET_LSB) & PHY_CTRL1_RX_LOWR_PDET_MASK)
1092 #define PHY_CTRL1_RX_LOWR_PDET_RESET 0x1 // 1
1093 #define PHY_CTRL1_RX_BYPASSEQ_MSB 3
1094 #define PHY_CTRL1_RX_BYPASSEQ_LSB 3
1095 #define PHY_CTRL1_RX_BYPASSEQ_MASK 0x00000008
1096 #define PHY_CTRL1_RX_BYPASSEQ_GET(x) (((x) & PHY_CTRL1_RX_BYPASSEQ_MASK) >> PHY_CTRL1_RX_BYPASSEQ_LSB)
1097 #define PHY_CTRL1_RX_BYPASSEQ_SET(x) (((x) << PHY_CTRL1_RX_BYPASSEQ_LSB) & PHY_CTRL1_RX_BYPASSEQ_MASK)
1098 #define PHY_CTRL1_RX_BYPASSEQ_RESET 0x0 // 0
1099 #define PHY_CTRL1_RX_FORCERXON_MSB 2
1100 #define PHY_CTRL1_RX_FORCERXON_LSB 2
1101 #define PHY_CTRL1_RX_FORCERXON_MASK 0x00000004
1102 #define PHY_CTRL1_RX_FORCERXON_GET(x) (((x) & PHY_CTRL1_RX_FORCERXON_MASK) >> PHY_CTRL1_RX_FORCERXON_LSB)
1103 #define PHY_CTRL1_RX_FORCERXON_SET(x) (((x) << PHY_CTRL1_RX_FORCERXON_LSB) & PHY_CTRL1_RX_FORCERXON_MASK)
1104 #define PHY_CTRL1_RX_FORCERXON_RESET 0x1 // 1
1105 #define PHY_CTRL1_RX_FILBW_SEL_MSB 1
1106 #define PHY_CTRL1_RX_FILBW_SEL_LSB 0
1107 #define PHY_CTRL1_RX_FILBW_SEL_MASK 0x00000003
1108 #define PHY_CTRL1_RX_FILBW_SEL_GET(x) (((x) & PHY_CTRL1_RX_FILBW_SEL_MASK) >> PHY_CTRL1_RX_FILBW_SEL_LSB)
1109 #define PHY_CTRL1_RX_FILBW_SEL_SET(x) (((x) << PHY_CTRL1_RX_FILBW_SEL_LSB) & PHY_CTRL1_RX_FILBW_SEL_MASK)
1110 #define PHY_CTRL1_RX_FILBW_SEL_RESET 0x1 // 1
1111 #define PHY_CTRL1_ADDRESS 0x18116c84
1112 #define PHY_CTRL1_OFFSET 0x0004
1113 // SW modifiable bits
1114 #define PHY_CTRL1_SW_MASK 0x8ffc3fff
1115 // bits defined at reset
1116 #define PHY_CTRL1_RSTMASK 0xffffffff
1117 // reset value (ignore bits undefined at reset)
1118 #define PHY_CTRL1_RESET 0x84600095
1120 #define PHY_CTRL2_PWD_EXTBIAS_MSB 31
1121 #define PHY_CTRL2_PWD_EXTBIAS_LSB 31
1122 #define PHY_CTRL2_PWD_EXTBIAS_MASK 0x80000000
1123 #define PHY_CTRL2_PWD_EXTBIAS_GET(x) (((x) & PHY_CTRL2_PWD_EXTBIAS_MASK) >> PHY_CTRL2_PWD_EXTBIAS_LSB)
1124 #define PHY_CTRL2_PWD_EXTBIAS_SET(x) (((x) << PHY_CTRL2_PWD_EXTBIAS_LSB) & PHY_CTRL2_PWD_EXTBIAS_MASK)
1125 #define PHY_CTRL2_PWD_EXTBIAS_RESET 0x0 // 0
1126 #define PHY_CTRL2_TX_RSVD_MSB 30
1127 #define PHY_CTRL2_TX_RSVD_LSB 27
1128 #define PHY_CTRL2_TX_RSVD_MASK 0x78000000
1129 #define PHY_CTRL2_TX_RSVD_GET(x) (((x) & PHY_CTRL2_TX_RSVD_MASK) >> PHY_CTRL2_TX_RSVD_LSB)
1130 #define PHY_CTRL2_TX_RSVD_SET(x) (((x) << PHY_CTRL2_TX_RSVD_LSB) & PHY_CTRL2_TX_RSVD_MASK)
1131 #define PHY_CTRL2_TX_RSVD_RESET 0x0 // 0
1132 #define PHY_CTRL2_TX_LCKDET_OVR_MSB 26
1133 #define PHY_CTRL2_TX_LCKDET_OVR_LSB 26
1134 #define PHY_CTRL2_TX_LCKDET_OVR_MASK 0x04000000
1135 #define PHY_CTRL2_TX_LCKDET_OVR_GET(x) (((x) & PHY_CTRL2_TX_LCKDET_OVR_MASK) >> PHY_CTRL2_TX_LCKDET_OVR_LSB)
1136 #define PHY_CTRL2_TX_LCKDET_OVR_SET(x) (((x) << PHY_CTRL2_TX_LCKDET_OVR_LSB) & PHY_CTRL2_TX_LCKDET_OVR_MASK)
1137 #define PHY_CTRL2_TX_LCKDET_OVR_RESET 0x0 // 0
1138 #define PHY_CTRL2_TX_MAN_CAL_MSB 25
1139 #define PHY_CTRL2_TX_MAN_CAL_LSB 22
1140 #define PHY_CTRL2_TX_MAN_CAL_MASK 0x03c00000
1141 #define PHY_CTRL2_TX_MAN_CAL_GET(x) (((x) & PHY_CTRL2_TX_MAN_CAL_MASK) >> PHY_CTRL2_TX_MAN_CAL_LSB)
1142 #define PHY_CTRL2_TX_MAN_CAL_SET(x) (((x) << PHY_CTRL2_TX_MAN_CAL_LSB) & PHY_CTRL2_TX_MAN_CAL_MASK)
1143 #define PHY_CTRL2_TX_MAN_CAL_RESET 0x3 // 3
1144 #define PHY_CTRL2_TX_CAL_SEL_MSB 21
1145 #define PHY_CTRL2_TX_CAL_SEL_LSB 21
1146 #define PHY_CTRL2_TX_CAL_SEL_MASK 0x00200000
1147 #define PHY_CTRL2_TX_CAL_SEL_GET(x) (((x) & PHY_CTRL2_TX_CAL_SEL_MASK) >> PHY_CTRL2_TX_CAL_SEL_LSB)
1148 #define PHY_CTRL2_TX_CAL_SEL_SET(x) (((x) << PHY_CTRL2_TX_CAL_SEL_LSB) & PHY_CTRL2_TX_CAL_SEL_MASK)
1149 #define PHY_CTRL2_TX_CAL_SEL_RESET 0x1 // 1
1150 #define PHY_CTRL2_TX_CAL_EN_MSB 20
1151 #define PHY_CTRL2_TX_CAL_EN_LSB 20
1152 #define PHY_CTRL2_TX_CAL_EN_MASK 0x00100000
1153 #define PHY_CTRL2_TX_CAL_EN_GET(x) (((x) & PHY_CTRL2_TX_CAL_EN_MASK) >> PHY_CTRL2_TX_CAL_EN_LSB)
1154 #define PHY_CTRL2_TX_CAL_EN_SET(x) (((x) << PHY_CTRL2_TX_CAL_EN_LSB) & PHY_CTRL2_TX_CAL_EN_MASK)
1155 #define PHY_CTRL2_TX_CAL_EN_RESET 0x1 // 1
1156 #define PHY_CTRL2_PWD_ISP_MSB 13
1157 #define PHY_CTRL2_PWD_ISP_LSB 8
1158 #define PHY_CTRL2_PWD_ISP_MASK 0x00003f00
1159 #define PHY_CTRL2_PWD_ISP_GET(x) (((x) & PHY_CTRL2_PWD_ISP_MASK) >> PHY_CTRL2_PWD_ISP_LSB)
1160 #define PHY_CTRL2_PWD_ISP_SET(x) (((x) << PHY_CTRL2_PWD_ISP_LSB) & PHY_CTRL2_PWD_ISP_MASK)
1161 #define PHY_CTRL2_PWD_ISP_RESET 0x1b // 27
1162 #define PHY_CTRL2_PWD_IPLL_MSB 7
1163 #define PHY_CTRL2_PWD_IPLL_LSB 2
1164 #define PHY_CTRL2_PWD_IPLL_MASK 0x000000fc
1165 #define PHY_CTRL2_PWD_IPLL_GET(x) (((x) & PHY_CTRL2_PWD_IPLL_MASK) >> PHY_CTRL2_PWD_IPLL_LSB)
1166 #define PHY_CTRL2_PWD_IPLL_SET(x) (((x) << PHY_CTRL2_PWD_IPLL_LSB) & PHY_CTRL2_PWD_IPLL_MASK)
1167 #define PHY_CTRL2_PWD_IPLL_RESET 0x1b // 27
1168 #define PHY_CTRL2_HSRXPHASE_PS_EN_MSB 1
1169 #define PHY_CTRL2_HSRXPHASE_PS_EN_LSB 1
1170 #define PHY_CTRL2_HSRXPHASE_PS_EN_MASK 0x00000002
1171 #define PHY_CTRL2_HSRXPHASE_PS_EN_GET(x) (((x) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> PHY_CTRL2_HSRXPHASE_PS_EN_LSB)
1172 #define PHY_CTRL2_HSRXPHASE_PS_EN_SET(x) (((x) << PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK)
1173 #define PHY_CTRL2_HSRXPHASE_PS_EN_RESET 0x0 // 0
1174 #define PHY_CTRL2_HSTXBIAS_PS_EN_MSB 0
1175 #define PHY_CTRL2_HSTXBIAS_PS_EN_LSB 0
1176 #define PHY_CTRL2_HSTXBIAS_PS_EN_MASK 0x00000001
1177 #define PHY_CTRL2_HSTXBIAS_PS_EN_GET(x) (((x) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> PHY_CTRL2_HSTXBIAS_PS_EN_LSB)
1178 #define PHY_CTRL2_HSTXBIAS_PS_EN_SET(x) (((x) << PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK)
1179 #define PHY_CTRL2_HSTXBIAS_PS_EN_RESET 0x0 // 0
1180 #define PHY_CTRL2_ADDRESS 0x18116c88
1181 #define PHY_CTRL2_OFFSET 0x0008
1182 // SW modifiable bits
1183 #define PHY_CTRL2_SW_MASK 0xfff03fff
1184 // bits defined at reset
1185 #define PHY_CTRL2_RSTMASK 0xffffffff
1186 // reset value (ignore bits undefined at reset)
1187 #define PHY_CTRL2_RESET 0x00f01b6c
1189 #define PHY_CTRL3_SPARE_BITS_MSB 31
1190 #define PHY_CTRL3_SPARE_BITS_LSB 27
1191 #define PHY_CTRL3_SPARE_BITS_MASK 0xf8000000
1192 #define PHY_CTRL3_SPARE_BITS_GET(x) (((x) & PHY_CTRL3_SPARE_BITS_MASK) >> PHY_CTRL3_SPARE_BITS_LSB)
1193 #define PHY_CTRL3_SPARE_BITS_SET(x) (((x) << PHY_CTRL3_SPARE_BITS_LSB) & PHY_CTRL3_SPARE_BITS_MASK)
1194 #define PHY_CTRL3_SPARE_BITS_RESET 0x0 // 0
1195 #define PHY_CTRL3_SUS_RES_FIX_DIS_MSB 26
1196 #define PHY_CTRL3_SUS_RES_FIX_DIS_LSB 26
1197 #define PHY_CTRL3_SUS_RES_FIX_DIS_MASK 0x04000000
1198 #define PHY_CTRL3_SUS_RES_FIX_DIS_GET(x) (((x) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) >> PHY_CTRL3_SUS_RES_FIX_DIS_LSB)
1199 #define PHY_CTRL3_SUS_RES_FIX_DIS_SET(x) (((x) << PHY_CTRL3_SUS_RES_FIX_DIS_LSB) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK)
1200 #define PHY_CTRL3_SUS_RES_FIX_DIS_RESET 0x0 // 0
1201 #define PHY_CTRL3_TX_STARTCAL_MSB 25
1202 #define PHY_CTRL3_TX_STARTCAL_LSB 25
1203 #define PHY_CTRL3_TX_STARTCAL_MASK 0x02000000
1204 #define PHY_CTRL3_TX_STARTCAL_GET(x) (((x) & PHY_CTRL3_TX_STARTCAL_MASK) >> PHY_CTRL3_TX_STARTCAL_LSB)
1205 #define PHY_CTRL3_TX_STARTCAL_SET(x) (((x) << PHY_CTRL3_TX_STARTCAL_LSB) & PHY_CTRL3_TX_STARTCAL_MASK)
1206 #define PHY_CTRL3_TX_STARTCAL_RESET 0x0 // 0
1207 #define PHY_CTRL3_TX_SELTEST_MSB 24
1208 #define PHY_CTRL3_TX_SELTEST_LSB 22
1209 #define PHY_CTRL3_TX_SELTEST_MASK 0x01c00000
1210 #define PHY_CTRL3_TX_SELTEST_GET(x) (((x) & PHY_CTRL3_TX_SELTEST_MASK) >> PHY_CTRL3_TX_SELTEST_LSB)
1211 #define PHY_CTRL3_TX_SELTEST_SET(x) (((x) << PHY_CTRL3_TX_SELTEST_LSB) & PHY_CTRL3_TX_SELTEST_MASK)
1212 #define PHY_CTRL3_TX_SELTEST_RESET 0x0 // 0
1213 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_MSB 21
1214 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB 21
1215 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK 0x00200000
1216 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_GET(x) (((x) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) >> PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB)
1217 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_SET(x) (((x) << PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK)
1218 #define PHY_CTRL3_TX_DISABLE_SHORT_DET_RESET 0x0 // 0
1219 #define PHY_CTRL3_PWD_ITX_MSB 18
1220 #define PHY_CTRL3_PWD_ITX_LSB 0
1221 #define PHY_CTRL3_PWD_ITX_MASK 0x0007ffff
1222 #define PHY_CTRL3_PWD_ITX_GET(x) (((x) & PHY_CTRL3_PWD_ITX_MASK) >> PHY_CTRL3_PWD_ITX_LSB)
1223 #define PHY_CTRL3_PWD_ITX_SET(x) (((x) << PHY_CTRL3_PWD_ITX_LSB) & PHY_CTRL3_PWD_ITX_MASK)
1224 #define PHY_CTRL3_PWD_ITX_RESET 0x14765 // 83813
1225 #define PHY_CTRL3_ADDRESS 0x18116c8c
1226 #define PHY_CTRL3_OFFSET 0x000c
1227 // SW modifiable bits
1228 #define PHY_CTRL3_SW_MASK 0xffe7ffff
1229 // bits defined at reset
1230 #define PHY_CTRL3_RSTMASK 0xffffffff
1231 // reset value (ignore bits undefined at reset)
1232 #define PHY_CTRL3_RESET 0x00014765
1234 #define PHY_CTRL4_PPRBS_ERR_CNT_MSB 31
1235 #define PHY_CTRL4_PPRBS_ERR_CNT_LSB 24
1236 #define PHY_CTRL4_PPRBS_ERR_CNT_MASK 0xff000000
1237 #define PHY_CTRL4_PPRBS_ERR_CNT_GET(x) (((x) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) >> PHY_CTRL4_PPRBS_ERR_CNT_LSB)
1238 #define PHY_CTRL4_PPRBS_ERR_CNT_SET(x) (((x) << PHY_CTRL4_PPRBS_ERR_CNT_LSB) & PHY_CTRL4_PPRBS_ERR_CNT_MASK)
1239 #define PHY_CTRL4_PPRBS_ERR_CNT_RESET 0x0 // 0
1240 #define PHY_CTRL4_LS_PRBS_EN_MSB 21
1241 #define PHY_CTRL4_LS_PRBS_EN_LSB 21
1242 #define PHY_CTRL4_LS_PRBS_EN_MASK 0x00200000
1243 #define PHY_CTRL4_LS_PRBS_EN_GET(x) (((x) & PHY_CTRL4_LS_PRBS_EN_MASK) >> PHY_CTRL4_LS_PRBS_EN_LSB)
1244 #define PHY_CTRL4_LS_PRBS_EN_SET(x) (((x) << PHY_CTRL4_LS_PRBS_EN_LSB) & PHY_CTRL4_LS_PRBS_EN_MASK)
1245 #define PHY_CTRL4_LS_PRBS_EN_RESET 0x0 // 0
1246 #define PHY_CTRL4_PPRBS_TERM_SEL_MSB 20
1247 #define PHY_CTRL4_PPRBS_TERM_SEL_LSB 20
1248 #define PHY_CTRL4_PPRBS_TERM_SEL_MASK 0x00100000
1249 #define PHY_CTRL4_PPRBS_TERM_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) >> PHY_CTRL4_PPRBS_TERM_SEL_LSB)
1250 #define PHY_CTRL4_PPRBS_TERM_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_TERM_SEL_LSB) & PHY_CTRL4_PPRBS_TERM_SEL_MASK)
1251 #define PHY_CTRL4_PPRBS_TERM_SEL_RESET 0x0 // 0
1252 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MSB 19
1253 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB 19
1254 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK 0x00080000
1255 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB)
1256 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK)
1257 #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_RESET 0x0 // 0
1258 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MSB 18
1259 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB 18
1260 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK 0x00040000
1261 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB)
1262 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK)
1263 #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_RESET 0x0 // 0
1264 #define PHY_CTRL4_PPRBS_PAT_SEL_MSB 17
1265 #define PHY_CTRL4_PPRBS_PAT_SEL_LSB 16
1266 #define PHY_CTRL4_PPRBS_PAT_SEL_MASK 0x00030000
1267 #define PHY_CTRL4_PPRBS_PAT_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) >> PHY_CTRL4_PPRBS_PAT_SEL_LSB)
1268 #define PHY_CTRL4_PPRBS_PAT_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_PAT_SEL_LSB) & PHY_CTRL4_PPRBS_PAT_SEL_MASK)
1269 #define PHY_CTRL4_PPRBS_PAT_SEL_RESET 0x0 // 0
1270 #define PHY_CTRL4_PPRBS_TX_EN_MSB 15
1271 #define PHY_CTRL4_PPRBS_TX_EN_LSB 15
1272 #define PHY_CTRL4_PPRBS_TX_EN_MASK 0x00008000
1273 #define PHY_CTRL4_PPRBS_TX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_TX_EN_MASK) >> PHY_CTRL4_PPRBS_TX_EN_LSB)
1274 #define PHY_CTRL4_PPRBS_TX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_TX_EN_LSB) & PHY_CTRL4_PPRBS_TX_EN_MASK)
1275 #define PHY_CTRL4_PPRBS_TX_EN_RESET 0x0 // 0
1276 #define PHY_CTRL4_PPRBS_RX_EN_MSB 14
1277 #define PHY_CTRL4_PPRBS_RX_EN_LSB 14
1278 #define PHY_CTRL4_PPRBS_RX_EN_MASK 0x00004000
1279 #define PHY_CTRL4_PPRBS_RX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_EN_MASK) >> PHY_CTRL4_PPRBS_RX_EN_LSB)
1280 #define PHY_CTRL4_PPRBS_RX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_EN_LSB) & PHY_CTRL4_PPRBS_RX_EN_MASK)
1281 #define PHY_CTRL4_PPRBS_RX_EN_RESET 0x0 // 0
1282 #define PHY_CTRL4_PPRBS_SPEED_SEL_MSB 13
1283 #define PHY_CTRL4_PPRBS_SPEED_SEL_LSB 13
1284 #define PHY_CTRL4_PPRBS_SPEED_SEL_MASK 0x00002000
1285 #define PHY_CTRL4_PPRBS_SPEED_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) >> PHY_CTRL4_PPRBS_SPEED_SEL_LSB)
1286 #define PHY_CTRL4_PPRBS_SPEED_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_SPEED_SEL_LSB) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK)
1287 #define PHY_CTRL4_PPRBS_SPEED_SEL_RESET 0x0 // 0
1288 #define PHY_CTRL4_PPRBS_RX_INV_MSB 12
1289 #define PHY_CTRL4_PPRBS_RX_INV_LSB 12
1290 #define PHY_CTRL4_PPRBS_RX_INV_MASK 0x00001000
1291 #define PHY_CTRL4_PPRBS_RX_INV_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_INV_MASK) >> PHY_CTRL4_PPRBS_RX_INV_LSB)
1292 #define PHY_CTRL4_PPRBS_RX_INV_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_INV_LSB) & PHY_CTRL4_PPRBS_RX_INV_MASK)
1293 #define PHY_CTRL4_PPRBS_RX_INV_RESET 0x0 // 0
1294 #define PHY_CTRL4_PWD_IRX_MSB 11
1295 #define PHY_CTRL4_PWD_IRX_LSB 0
1296 #define PHY_CTRL4_PWD_IRX_MASK 0x00000fff
1297 #define PHY_CTRL4_PWD_IRX_GET(x) (((x) & PHY_CTRL4_PWD_IRX_MASK) >> PHY_CTRL4_PWD_IRX_LSB)
1298 #define PHY_CTRL4_PWD_IRX_SET(x) (((x) << PHY_CTRL4_PWD_IRX_LSB) & PHY_CTRL4_PWD_IRX_MASK)
1299 #define PHY_CTRL4_PWD_IRX_RESET 0x6dd // 1757
1300 #define PHY_CTRL4_ADDRESS 0x18116c90
1301 #define PHY_CTRL4_OFFSET 0x0010
1302 // SW modifiable bits
1303 #define PHY_CTRL4_SW_MASK 0xff3fffff
1304 // bits defined at reset
1305 #define PHY_CTRL4_RSTMASK 0xffffffff
1306 // reset value (ignore bits undefined at reset)
1307 #define PHY_CTRL4_RESET 0x000006dd
1309 #define PHY_CTRL5_SPARE_BITS_MSB 31
1310 #define PHY_CTRL5_SPARE_BITS_LSB 30
1311 #define PHY_CTRL5_SPARE_BITS_MASK 0xc0000000
1312 #define PHY_CTRL5_SPARE_BITS_GET(x) (((x) & PHY_CTRL5_SPARE_BITS_MASK) >> PHY_CTRL5_SPARE_BITS_LSB)
1313 #define PHY_CTRL5_SPARE_BITS_SET(x) (((x) << PHY_CTRL5_SPARE_BITS_LSB) & PHY_CTRL5_SPARE_BITS_MASK)
1314 #define PHY_CTRL5_SPARE_BITS_RESET 0x0 // 0
1315 #define PHY_CTRL5_HOST_RES_FIX_EN_MSB 29
1316 #define PHY_CTRL5_HOST_RES_FIX_EN_LSB 29
1317 #define PHY_CTRL5_HOST_RES_FIX_EN_MASK 0x20000000
1318 #define PHY_CTRL5_HOST_RES_FIX_EN_GET(x) (((x) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) >> PHY_CTRL5_HOST_RES_FIX_EN_LSB)
1319 #define PHY_CTRL5_HOST_RES_FIX_EN_SET(x) (((x) << PHY_CTRL5_HOST_RES_FIX_EN_LSB) & PHY_CTRL5_HOST_RES_FIX_EN_MASK)
1320 #define PHY_CTRL5_HOST_RES_FIX_EN_RESET 0x1 // 1
1321 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MSB 28
1322 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB 26
1323 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK 0x1c000000
1324 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) >> PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB)
1325 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK)
1326 #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_RESET 0x6 // 6
1327 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_MSB 25
1328 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB 25
1329 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK 0x02000000
1330 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) >> PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB)
1331 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK)
1332 #define PHY_CTRL5_HOST_DISCON_DETECT_ON_RESET 0x1 // 1
1333 #define PHY_CTRL5_HOST_DISCON_FIX_ON_MSB 24
1334 #define PHY_CTRL5_HOST_DISCON_FIX_ON_LSB 24
1335 #define PHY_CTRL5_HOST_DISCON_FIX_ON_MASK 0x01000000
1336 #define PHY_CTRL5_HOST_DISCON_FIX_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) >> PHY_CTRL5_HOST_DISCON_FIX_ON_LSB)
1337 #define PHY_CTRL5_HOST_DISCON_FIX_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK)
1338 #define PHY_CTRL5_HOST_DISCON_FIX_ON_RESET 0x1 // 1
1339 #define PHY_CTRL5_DM_PULLDOWN_MSB 23
1340 #define PHY_CTRL5_DM_PULLDOWN_LSB 23
1341 #define PHY_CTRL5_DM_PULLDOWN_MASK 0x00800000
1342 #define PHY_CTRL5_DM_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DM_PULLDOWN_MASK) >> PHY_CTRL5_DM_PULLDOWN_LSB)
1343 #define PHY_CTRL5_DM_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DM_PULLDOWN_LSB) & PHY_CTRL5_DM_PULLDOWN_MASK)
1344 #define PHY_CTRL5_DM_PULLDOWN_RESET 0x0 // 0
1345 #define PHY_CTRL5_DP_PULLDOWN_MSB 22
1346 #define PHY_CTRL5_DP_PULLDOWN_LSB 22
1347 #define PHY_CTRL5_DP_PULLDOWN_MASK 0x00400000
1348 #define PHY_CTRL5_DP_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DP_PULLDOWN_MASK) >> PHY_CTRL5_DP_PULLDOWN_LSB)
1349 #define PHY_CTRL5_DP_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DP_PULLDOWN_LSB) & PHY_CTRL5_DP_PULLDOWN_MASK)
1350 #define PHY_CTRL5_DP_PULLDOWN_RESET 0x0 // 0
1351 #define PHY_CTRL5_SUSPEND_N_MSB 21
1352 #define PHY_CTRL5_SUSPEND_N_LSB 21
1353 #define PHY_CTRL5_SUSPEND_N_MASK 0x00200000
1354 #define PHY_CTRL5_SUSPEND_N_GET(x) (((x) & PHY_CTRL5_SUSPEND_N_MASK) >> PHY_CTRL5_SUSPEND_N_LSB)
1355 #define PHY_CTRL5_SUSPEND_N_SET(x) (((x) << PHY_CTRL5_SUSPEND_N_LSB) & PHY_CTRL5_SUSPEND_N_MASK)
1356 #define PHY_CTRL5_SUSPEND_N_RESET 0x1 // 1
1357 #define PHY_CTRL5_TERM_SEL_MSB 20
1358 #define PHY_CTRL5_TERM_SEL_LSB 20
1359 #define PHY_CTRL5_TERM_SEL_MASK 0x00100000
1360 #define PHY_CTRL5_TERM_SEL_GET(x) (((x) & PHY_CTRL5_TERM_SEL_MASK) >> PHY_CTRL5_TERM_SEL_LSB)
1361 #define PHY_CTRL5_TERM_SEL_SET(x) (((x) << PHY_CTRL5_TERM_SEL_LSB) & PHY_CTRL5_TERM_SEL_MASK)
1362 #define PHY_CTRL5_TERM_SEL_RESET 0x0 // 0
1363 #define PHY_CTRL5_XCVR_SEL_MSB 19
1364 #define PHY_CTRL5_XCVR_SEL_LSB 18
1365 #define PHY_CTRL5_XCVR_SEL_MASK 0x000c0000
1366 #define PHY_CTRL5_XCVR_SEL_GET(x) (((x) & PHY_CTRL5_XCVR_SEL_MASK) >> PHY_CTRL5_XCVR_SEL_LSB)
1367 #define PHY_CTRL5_XCVR_SEL_SET(x) (((x) << PHY_CTRL5_XCVR_SEL_LSB) & PHY_CTRL5_XCVR_SEL_MASK)
1368 #define PHY_CTRL5_XCVR_SEL_RESET 0x0 // 0
1369 #define PHY_CTRL5_TEST_JK_OVERRIDE_MSB 17
1370 #define PHY_CTRL5_TEST_JK_OVERRIDE_LSB 17
1371 #define PHY_CTRL5_TEST_JK_OVERRIDE_MASK 0x00020000
1372 #define PHY_CTRL5_TEST_JK_OVERRIDE_GET(x) (((x) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) >> PHY_CTRL5_TEST_JK_OVERRIDE_LSB)
1373 #define PHY_CTRL5_TEST_JK_OVERRIDE_SET(x) (((x) << PHY_CTRL5_TEST_JK_OVERRIDE_LSB) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK)
1374 #define PHY_CTRL5_TEST_JK_OVERRIDE_RESET 0x0 // 0
1375 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_MSB 16
1376 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB 16
1377 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK 0x00010000
1378 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) >> PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB)
1379 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK)
1380 #define PHY_CTRL5_FORCE_TEST_SE0_NAK_RESET 0x0 // 0
1381 #define PHY_CTRL5_FORCE_TEST_K_MSB 15
1382 #define PHY_CTRL5_FORCE_TEST_K_LSB 15
1383 #define PHY_CTRL5_FORCE_TEST_K_MASK 0x00008000
1384 #define PHY_CTRL5_FORCE_TEST_K_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_K_MASK) >> PHY_CTRL5_FORCE_TEST_K_LSB)
1385 #define PHY_CTRL5_FORCE_TEST_K_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_K_LSB) & PHY_CTRL5_FORCE_TEST_K_MASK)
1386 #define PHY_CTRL5_FORCE_TEST_K_RESET 0x0 // 0
1387 #define PHY_CTRL5_FORCE_TEST_J_MSB 14
1388 #define PHY_CTRL5_FORCE_TEST_J_LSB 14
1389 #define PHY_CTRL5_FORCE_TEST_J_MASK 0x00004000
1390 #define PHY_CTRL5_FORCE_TEST_J_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_J_MASK) >> PHY_CTRL5_FORCE_TEST_J_LSB)
1391 #define PHY_CTRL5_FORCE_TEST_J_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_J_LSB) & PHY_CTRL5_FORCE_TEST_J_MASK)
1392 #define PHY_CTRL5_FORCE_TEST_J_RESET 0x0 // 0
1393 #define PHY_CTRL5_FORCE_IDDQ_MSB 13
1394 #define PHY_CTRL5_FORCE_IDDQ_LSB 13
1395 #define PHY_CTRL5_FORCE_IDDQ_MASK 0x00002000
1396 #define PHY_CTRL5_FORCE_IDDQ_GET(x) (((x) & PHY_CTRL5_FORCE_IDDQ_MASK) >> PHY_CTRL5_FORCE_IDDQ_LSB)
1397 #define PHY_CTRL5_FORCE_IDDQ_SET(x) (((x) << PHY_CTRL5_FORCE_IDDQ_LSB) & PHY_CTRL5_FORCE_IDDQ_MASK)
1398 #define PHY_CTRL5_FORCE_IDDQ_RESET 0x0 // 0
1399 #define PHY_CTRL5_EB_WATERMARK_MSB 12
1400 #define PHY_CTRL5_EB_WATERMARK_LSB 7
1401 #define PHY_CTRL5_EB_WATERMARK_MASK 0x00001f80
1402 #define PHY_CTRL5_EB_WATERMARK_GET(x) (((x) & PHY_CTRL5_EB_WATERMARK_MASK) >> PHY_CTRL5_EB_WATERMARK_LSB)
1403 #define PHY_CTRL5_EB_WATERMARK_SET(x) (((x) << PHY_CTRL5_EB_WATERMARK_LSB) & PHY_CTRL5_EB_WATERMARK_MASK)
1404 #define PHY_CTRL5_EB_WATERMARK_RESET 0x14 // 20
1405 #define PHY_CTRL5_TX_BIAS_DELAY_MSB 6
1406 #define PHY_CTRL5_TX_BIAS_DELAY_LSB 0
1407 #define PHY_CTRL5_TX_BIAS_DELAY_MASK 0x0000007f
1408 #define PHY_CTRL5_TX_BIAS_DELAY_GET(x) (((x) & PHY_CTRL5_TX_BIAS_DELAY_MASK) >> PHY_CTRL5_TX_BIAS_DELAY_LSB)
1409 #define PHY_CTRL5_TX_BIAS_DELAY_SET(x) (((x) << PHY_CTRL5_TX_BIAS_DELAY_LSB) & PHY_CTRL5_TX_BIAS_DELAY_MASK)
1410 #define PHY_CTRL5_TX_BIAS_DELAY_RESET 0x32 // 50
1411 #define PHY_CTRL5_ADDRESS 0x18116c94
1412 #define PHY_CTRL5_OFFSET 0x0014
1413 // SW modifiable bits
1414 #define PHY_CTRL5_SW_MASK 0xffffffff
1415 // bits defined at reset
1416 #define PHY_CTRL5_RSTMASK 0xffffffff
1417 // reset value (ignore bits undefined at reset)
1418 #define PHY_CTRL5_RESET 0x3b200a32
1419 #define PHY_CTRL5_RESET_1 0x3b202a58
1421 #define PHY_CTRL6_SPARE_BITS_MSB 31
1422 #define PHY_CTRL6_SPARE_BITS_LSB 9
1423 #define PHY_CTRL6_SPARE_BITS_MASK 0xfffffe00
1424 #define PHY_CTRL6_SPARE_BITS_GET(x) (((x) & PHY_CTRL6_SPARE_BITS_MASK) >> PHY_CTRL6_SPARE_BITS_LSB)
1425 #define PHY_CTRL6_SPARE_BITS_SET(x) (((x) << PHY_CTRL6_SPARE_BITS_LSB) & PHY_CTRL6_SPARE_BITS_MASK)
1426 #define PHY_CTRL6_SPARE_BITS_RESET 0x0 // 0
1427 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MSB 8
1428 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB 8
1429 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK 0x00000100
1430 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_GET(x) (((x) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) >> PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB)
1431 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_SET(x) (((x) << PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK)
1432 #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_RESET 0x0 // 0
1433 #define PHY_CTRL6_XCVR_SEL_MSB 7
1434 #define PHY_CTRL6_XCVR_SEL_LSB 6
1435 #define PHY_CTRL6_XCVR_SEL_MASK 0x000000c0
1436 #define PHY_CTRL6_XCVR_SEL_GET(x) (((x) & PHY_CTRL6_XCVR_SEL_MASK) >> PHY_CTRL6_XCVR_SEL_LSB)
1437 #define PHY_CTRL6_XCVR_SEL_SET(x) (((x) << PHY_CTRL6_XCVR_SEL_LSB) & PHY_CTRL6_XCVR_SEL_MASK)
1438 #define PHY_CTRL6_XCVR_SEL_RESET 0x0 // 0
1439 #define PHY_CTRL6_XCVRSEL_OVERRIDE_MSB 5
1440 #define PHY_CTRL6_XCVRSEL_OVERRIDE_LSB 5
1441 #define PHY_CTRL6_XCVRSEL_OVERRIDE_MASK 0x00000020
1442 #define PHY_CTRL6_XCVRSEL_OVERRIDE_GET(x) (((x) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) >> PHY_CTRL6_XCVRSEL_OVERRIDE_LSB)
1443 #define PHY_CTRL6_XCVRSEL_OVERRIDE_SET(x) (((x) << PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK)
1444 #define PHY_CTRL6_XCVRSEL_OVERRIDE_RESET 0x0 // 0
1445 #define PHY_CTRL6_IDDIG_MSB 4
1446 #define PHY_CTRL6_IDDIG_LSB 4
1447 #define PHY_CTRL6_IDDIG_MASK 0x00000010
1448 #define PHY_CTRL6_IDDIG_GET(x) (((x) & PHY_CTRL6_IDDIG_MASK) >> PHY_CTRL6_IDDIG_LSB)
1449 #define PHY_CTRL6_IDDIG_SET(x) (((x) << PHY_CTRL6_IDDIG_LSB) & PHY_CTRL6_IDDIG_MASK)
1450 #define PHY_CTRL6_IDDIG_RESET 0x0 // 0
1451 #define PHY_CTRL6_SESSEND_MSB 3
1452 #define PHY_CTRL6_SESSEND_LSB 3
1453 #define PHY_CTRL6_SESSEND_MASK 0x00000008
1454 #define PHY_CTRL6_SESSEND_GET(x) (((x) & PHY_CTRL6_SESSEND_MASK) >> PHY_CTRL6_SESSEND_LSB)
1455 #define PHY_CTRL6_SESSEND_SET(x) (((x) << PHY_CTRL6_SESSEND_LSB) & PHY_CTRL6_SESSEND_MASK)
1456 #define PHY_CTRL6_SESSEND_RESET 0x0 // 0
1457 #define PHY_CTRL6_VBUSVALID_MSB 2
1458 #define PHY_CTRL6_VBUSVALID_LSB 2
1459 #define PHY_CTRL6_VBUSVALID_MASK 0x00000004
1460 #define PHY_CTRL6_VBUSVALID_GET(x) (((x) & PHY_CTRL6_VBUSVALID_MASK) >> PHY_CTRL6_VBUSVALID_LSB)
1461 #define PHY_CTRL6_VBUSVALID_SET(x) (((x) << PHY_CTRL6_VBUSVALID_LSB) & PHY_CTRL6_VBUSVALID_MASK)
1462 #define PHY_CTRL6_VBUSVALID_RESET 0x1 // 1
1463 #define PHY_CTRL6_BVALID_MSB 1
1464 #define PHY_CTRL6_BVALID_LSB 1
1465 #define PHY_CTRL6_BVALID_MASK 0x00000002
1466 #define PHY_CTRL6_BVALID_GET(x) (((x) & PHY_CTRL6_BVALID_MASK) >> PHY_CTRL6_BVALID_LSB)
1467 #define PHY_CTRL6_BVALID_SET(x) (((x) << PHY_CTRL6_BVALID_LSB) & PHY_CTRL6_BVALID_MASK)
1468 #define PHY_CTRL6_BVALID_RESET 0x1 // 1
1469 #define PHY_CTRL6_AVALID_MSB 0
1470 #define PHY_CTRL6_AVALID_LSB 0
1471 #define PHY_CTRL6_AVALID_MASK 0x00000001
1472 #define PHY_CTRL6_AVALID_GET(x) (((x) & PHY_CTRL6_AVALID_MASK) >> PHY_CTRL6_AVALID_LSB)
1473 #define PHY_CTRL6_AVALID_SET(x) (((x) << PHY_CTRL6_AVALID_LSB) & PHY_CTRL6_AVALID_MASK)
1474 #define PHY_CTRL6_AVALID_RESET 0x1 // 1
1475 #define PHY_CTRL6_ADDRESS 0x18116c98
1476 #define PHY_CTRL6_OFFSET 0x0018
1477 // SW modifiable bits
1478 #define PHY_CTRL6_SW_MASK 0xffffffff
1479 // bits defined at reset
1480 #define PHY_CTRL6_RSTMASK 0xffffffff
1481 // reset value (ignore bits undefined at reset)
1482 #define PHY_CTRL6_RESET 0x00000007
1484 #define PHY_STATUS_TX_CAL_MSB 3
1485 #define PHY_STATUS_TX_CAL_LSB 0
1486 #define PHY_STATUS_TX_CAL_MASK 0x0000000f
1487 #define PHY_STATUS_TX_CAL_GET(x) (((x) & PHY_STATUS_TX_CAL_MASK) >> PHY_STATUS_TX_CAL_LSB)
1488 #define PHY_STATUS_TX_CAL_SET(x) (((x) << PHY_STATUS_TX_CAL_LSB) & PHY_STATUS_TX_CAL_MASK)
1489 #define PHY_STATUS_TX_CAL_RESET 0x0 // 0
1490 #define PHY_STATUS_ADDRESS 0x18116c9c
1491 #define PHY_STATUS_OFFSET 0x001c
1492 // SW modifiable bits
1493 #define PHY_STATUS_SW_MASK 0x0000000f
1494 // bits defined at reset
1495 #define PHY_STATUS_RSTMASK 0xffffffff
1496 // reset value (ignore bits undefined at reset)
1497 #define PHY_STATUS_RESET 0x00000000
1499 #define PHY_CTRL7_PPRBS_ERROR_RATE_MSB 31
1500 #define PHY_CTRL7_PPRBS_ERROR_RATE_LSB 11
1501 #define PHY_CTRL7_PPRBS_ERROR_RATE_MASK 0xfffff800
1502 #define PHY_CTRL7_PPRBS_ERROR_RATE_GET(x) (((x) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) >> PHY_CTRL7_PPRBS_ERROR_RATE_LSB)
1503 #define PHY_CTRL7_PPRBS_ERROR_RATE_SET(x) (((x) << PHY_CTRL7_PPRBS_ERROR_RATE_LSB) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK)
1504 #define PHY_CTRL7_PPRBS_ERROR_RATE_RESET 0xa000 // 40960
1505 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MSB 10
1506 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB 1
1507 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe
1508 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) >> PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB)
1509 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK)
1510 #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0
1511 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MSB 0
1512 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB 0
1513 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK 0x00000001
1514 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_GET(x) (((x) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) >> PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB)
1515 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_SET(x) (((x) << PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK)
1516 #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_RESET 0x0 // 0
1517 #define PHY_CTRL7_ADDRESS 0x18116ca0
1518 #define PHY_CTRL7_OFFSET 0x0020
1519 // SW modifiable bits
1520 #define PHY_CTRL7_SW_MASK 0xffffffff
1521 // bits defined at reset
1522 #define PHY_CTRL7_RSTMASK 0xffffffff
1523 // reset value (ignore bits undefined at reset)
1524 #define PHY_CTRL7_RESET 0x05000000
1526 #define PHY_CTRL8_USBPLL_PWD_MSB 7
1527 #define PHY_CTRL8_USBPLL_PWD_LSB 7
1528 #define PHY_CTRL8_USBPLL_PWD_MASK 0x00000080
1529 #define PHY_CTRL8_USBPLL_PWD_GET(x) (((x) & PHY_CTRL8_USBPLL_PWD_MASK) >> PHY_CTRL8_USBPLL_PWD_LSB)
1530 #define PHY_CTRL8_USBPLL_PWD_SET(x) (((x) << PHY_CTRL8_USBPLL_PWD_LSB) & PHY_CTRL8_USBPLL_PWD_MASK)
1531 #define PHY_CTRL8_USBPLL_PWD_RESET 0x0 // 0
1532 #define PHY_CTRL8_TX_FASTRISE_MSB 6
1533 #define PHY_CTRL8_TX_FASTRISE_LSB 4
1534 #define PHY_CTRL8_TX_FASTRISE_MASK 0x00000070
1535 #define PHY_CTRL8_TX_FASTRISE_GET(x) (((x) & PHY_CTRL8_TX_FASTRISE_MASK) >> PHY_CTRL8_TX_FASTRISE_LSB)
1536 #define PHY_CTRL8_TX_FASTRISE_SET(x) (((x) << PHY_CTRL8_TX_FASTRISE_LSB) & PHY_CTRL8_TX_FASTRISE_MASK)
1537 #define PHY_CTRL8_TX_FASTRISE_RESET 0x5 // 5
1538 #define PHY_CTRL8_TX_ENPRE_MSB 3
1539 #define PHY_CTRL8_TX_ENPRE_LSB 2
1540 #define PHY_CTRL8_TX_ENPRE_MASK 0x0000000c
1541 #define PHY_CTRL8_TX_ENPRE_GET(x) (((x) & PHY_CTRL8_TX_ENPRE_MASK) >> PHY_CTRL8_TX_ENPRE_LSB)
1542 #define PHY_CTRL8_TX_ENPRE_SET(x) (((x) << PHY_CTRL8_TX_ENPRE_LSB) & PHY_CTRL8_TX_ENPRE_MASK)
1543 #define PHY_CTRL8_TX_ENPRE_RESET 0x0 // 0
1544 #define PHY_CTRL8_RX_SQ_HYST_EN_MSB 1
1545 #define PHY_CTRL8_RX_SQ_HYST_EN_LSB 1
1546 #define PHY_CTRL8_RX_SQ_HYST_EN_MASK 0x00000002
1547 #define PHY_CTRL8_RX_SQ_HYST_EN_GET(x) (((x) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) >> PHY_CTRL8_RX_SQ_HYST_EN_LSB)
1548 #define PHY_CTRL8_RX_SQ_HYST_EN_SET(x) (((x) << PHY_CTRL8_RX_SQ_HYST_EN_LSB) & PHY_CTRL8_RX_SQ_HYST_EN_MASK)
1549 #define PHY_CTRL8_RX_SQ_HYST_EN_RESET 0x0 // 0
1550 #define PHY_CTRL8_RX_SKIP2_MSB 0
1551 #define PHY_CTRL8_RX_SKIP2_LSB 0
1552 #define PHY_CTRL8_RX_SKIP2_MASK 0x00000001
1553 #define PHY_CTRL8_RX_SKIP2_GET(x) (((x) & PHY_CTRL8_RX_SKIP2_MASK) >> PHY_CTRL8_RX_SKIP2_LSB)
1554 #define PHY_CTRL8_RX_SKIP2_SET(x) (((x) << PHY_CTRL8_RX_SKIP2_LSB) & PHY_CTRL8_RX_SKIP2_MASK)
1555 #define PHY_CTRL8_RX_SKIP2_RESET 0x0 // 0
1556 #define PHY_CTRL8_ADDRESS 0x18116ca4
1557 #define PHY_CTRL8_OFFSET 0x0024
1558 // SW modifiable bits
1559 #define PHY_CTRL8_SW_MASK 0x000000ff
1560 // bits defined at reset
1561 #define PHY_CTRL8_RSTMASK 0xffffffff
1562 // reset value (ignore bits undefined at reset)
1563 #define PHY_CTRL8_RESET 0x00000050
1564 #define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
1565 #define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
1566 #define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
1567 #define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
1568 #define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
1569 #define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0x0 // 0
1570 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
1571 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
1572 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
1573 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
1574 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
1575 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 0x1 // 1
1576 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
1577 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
1578 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
1579 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
1580 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
1581 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0x0 // 0
1582 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
1583 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
1584 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
1585 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
1586 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
1587 #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0 // 0
1588 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21
1589 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21
1590 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000
1591 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB)
1592 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK)
1593 #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 0x1 // 1
1594 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20
1595 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20
1596 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000
1597 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB)
1598 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK)
1599 #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 0x1 // 1
1600 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
1601 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
1602 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
1603 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
1604 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
1605 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0x0 // 0
1606 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
1607 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
1608 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
1609 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
1610 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
1611 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0x0 // 0
1612 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
1613 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
1614 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
1615 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
1616 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
1617 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0x0 // 0
1618 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
1619 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
1620 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
1621 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
1622 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
1623 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 0x1 // 1
1624 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
1625 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
1626 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
1627 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
1628 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
1629 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 0x1 // 1
1630 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
1631 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
1632 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
1633 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
1634 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
1635 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 0x1 // 1
1636 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
1637 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
1638 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
1639 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
1640 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
1641 #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0x0 // 0
1642 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
1643 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
1644 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
1645 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
1646 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
1647 #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0x0 // 0
1648 #define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008
1650 #define PCIE_PLL_CONFIG_UPDATING_MSB 31
1651 #define PCIE_PLL_CONFIG_UPDATING_LSB 31
1652 #define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000
1653 #define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
1654 #define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
1655 #define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0
1656 #define PCIE_PLL_CONFIG_PLLPWD_MSB 30
1657 #define PCIE_PLL_CONFIG_PLLPWD_LSB 30
1658 #define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000
1659 #define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
1660 #define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
1661 #define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
1662 #define PCIE_PLL_CONFIG_BYPASS_MSB 16
1663 #define PCIE_PLL_CONFIG_BYPASS_LSB 16
1664 #define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000
1665 #define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
1666 #define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
1667 #define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1
1668 #define PCIE_PLL_CONFIG_REFDIV_MSB 14
1669 #define PCIE_PLL_CONFIG_REFDIV_LSB 10
1670 #define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00
1671 #define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
1672 #define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
1673 #define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1
1674 #define PCIE_PLL_CONFIG_ADDRESS 0x18050010
1676 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31
1677 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31
1678 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000
1679 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
1680 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
1681 #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1
1682 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30
1683 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30
1684 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000
1685 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
1686 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
1687 #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1
1688 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20
1689 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15
1690 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000
1691 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
1692 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
1693 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19
1694 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14
1695 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1
1696 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe
1697 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
1698 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
1699 #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383
1700 #define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050014
1702 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20
1703 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15
1704 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000
1705 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
1706 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
1707 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19
1708 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14
1709 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1
1710 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe
1711 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
1712 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
1713 #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749
1714 #define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050018
1716 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31
1717 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28
1718 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000
1719 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
1720 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
1721 #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0
1722 #define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24
1723 #define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15
1724 #define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000
1725 #define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
1726 #define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
1727 #define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0
1728 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14
1729 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1
1730 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe
1731 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
1732 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
1733 #define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10
1734 #define PCIE_PLL_DITHER_STEP_ADDRESS 0x1805001c
1738 // 32'h180f0008 (PCIE_PWR_MGMT)
1739 #define PCIE_PWR_MGMT_PME_INT_MSB 8
1740 #define PCIE_PWR_MGMT_PME_INT_LSB 8
1741 #define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100
1742 #define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
1743 #define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
1744 #define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0
1745 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7
1746 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7
1747 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080
1748 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
1749 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
1750 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0
1751 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6
1752 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6
1753 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040
1754 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
1755 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
1756 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0
1757 #define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5
1758 #define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5
1759 #define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020
1760 #define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
1761 #define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
1762 #define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0
1763 #define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4
1764 #define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4
1765 #define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010
1766 #define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
1767 #define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
1768 #define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0
1769 #define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3
1770 #define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3
1771 #define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008
1772 #define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
1773 #define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
1774 #define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0
1775 #define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2
1776 #define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2
1777 #define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004
1778 #define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
1779 #define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
1780 #define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0
1781 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1
1782 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1
1783 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002
1784 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
1785 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
1786 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0
1787 #define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0
1788 #define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0
1789 #define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001
1790 #define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
1791 #define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
1792 #define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0
1793 #define PCIE_PWR_MGMT_ADDRESS 0x180f0008
1794 #define PCIE_PWR_MGMT_OFFSET 0x0008
1795 // SW modifiable bits
1796 #define PCIE_PWR_MGMT_SW_MASK 0x000001ff
1797 // bits defined at reset
1798 #define PCIE_PWR_MGMT_RSTMASK 0xffffffff
1799 // reset value (ignore bits undefined at reset)
1800 #define PCIE_PWR_MGMT_RESET 0x00000000
1803 // 32'h180600c0 (RST_CLKGAT_EN)
1804 #define RST_CLKGAT_EN_SPARE_MSB 31
1805 #define RST_CLKGAT_EN_SPARE_LSB 12
1806 #define RST_CLKGAT_EN_SPARE_MASK 0xfffff000
1807 #define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB)
1808 #define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK)
1809 #define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0
1810 #define RST_CLKGAT_EN_WMAC_MSB 9
1811 #define RST_CLKGAT_EN_WMAC_LSB 9
1812 #define RST_CLKGAT_EN_WMAC_MASK 0x00000200
1813 #define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)
1814 #define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)
1815 #define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1
1816 #define RST_CLKGAT_EN_USB1_MSB 7
1817 #define RST_CLKGAT_EN_USB1_LSB 7
1818 #define RST_CLKGAT_EN_USB1_MASK 0x00000080
1819 #define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)
1820 #define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)
1821 #define RST_CLKGAT_EN_USB1_RESET 0x1 // 1
1822 #define RST_CLKGAT_EN_GE1_MSB 6
1823 #define RST_CLKGAT_EN_GE1_LSB 6
1824 #define RST_CLKGAT_EN_GE1_MASK 0x00000040
1825 #define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)
1826 #define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)
1827 #define RST_CLKGAT_EN_GE1_RESET 0x1 // 1
1828 #define RST_CLKGAT_EN_GE0_MSB 5
1829 #define RST_CLKGAT_EN_GE0_LSB 5
1830 #define RST_CLKGAT_EN_GE0_MASK 0x00000020
1831 #define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)
1832 #define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)
1833 #define RST_CLKGAT_EN_GE0_RESET 0x1 // 1
1834 #define RST_CLKGAT_EN_PCIE_RC_MSB 1
1835 #define RST_CLKGAT_EN_PCIE_RC_LSB 1
1836 #define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002
1837 #define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)
1838 #define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)
1839 #define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1
1840 #define RST_CLKGAT_EN_ADDRESS 0x180600c0
1841 #define RST_CLKGAT_EN_OFFSET 0x00c0
1842 // SW modifiable bits
1843 #define RST_CLKGAT_EN_SW_MASK 0xfffff2e2
1844 // bits defined at reset
1845 #define RST_CLKGAT_EN_RSTMASK 0xffffffff
1846 // reset value (ignore bits undefined at reset)
1847 #define RST_CLKGAT_EN_RESET 0x000002e2
1851 #define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
1852 #define PCIE_PHY_REG_3_ADDRESS 0x18116cc8
1858 #define LDO_POWER_CONTROL_PKG_SEL_MSB 5
1859 #define LDO_POWER_CONTROL_PKG_SEL_LSB 5
1860 #define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020
1861 #define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
1862 #define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
1863 #define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0
1864 #define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4
1865 #define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4
1866 #define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010
1867 #define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
1868 #define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
1869 #define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0
1870 #define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3
1871 #define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3
1872 #define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008
1873 #define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
1874 #define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
1875 #define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0
1876 #define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2
1877 #define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1
1878 #define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006
1879 #define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
1880 #define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
1881 #define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3
1882 #define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0
1883 #define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0
1884 #define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001
1885 #define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
1886 #define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
1887 #define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0
1888 #define LDO_POWER_CONTROL_ADDRESS 0x18050020
1890 #define SWITCH_CLOCK_SPARE_SPARE_MSB 31
1891 #define SWITCH_CLOCK_SPARE_SPARE_LSB 12
1892 #define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000
1893 #define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
1894 #define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
1895 #define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0
1896 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
1897 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
1898 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
1899 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
1900 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
1901 #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5
1902 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
1903 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
1904 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
1905 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
1906 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
1907 #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0
1908 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6
1909 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6
1910 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040
1911 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB)
1912 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK)
1913 #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0x0 // 0
1914 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5
1915 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5
1916 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020
1917 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)
1918 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)
1919 #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1
1920 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4
1921 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4
1922 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010
1923 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)
1924 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)
1925 #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1
1926 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3
1927 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3
1928 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008
1929 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)
1930 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)
1931 #define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0
1932 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2
1933 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2
1934 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004
1935 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB)
1936 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK)
1937 #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0x0 // 0
1938 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1
1939 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1
1940 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002
1941 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)
1942 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)
1943 #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0
1944 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0
1945 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0
1946 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001
1947 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)
1948 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)
1949 #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1
1950 #define SWITCH_CLOCK_SPARE_ADDRESS 0x18050024
1952 #define CURRENT_PCIE_PLL_DITHER_INT_MSB 20
1953 #define CURRENT_PCIE_PLL_DITHER_INT_LSB 15
1954 #define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000
1955 #define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)
1956 #define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)
1957 #define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1
1958 #define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13
1959 #define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0
1960 #define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff
1961 #define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)
1962 #define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)
1963 #define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0
1964 #define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050028
1966 #define ETH_XMII_TX_INVERT_MSB 31
1967 #define ETH_XMII_TX_INVERT_LSB 31
1968 #define ETH_XMII_TX_INVERT_MASK 0x80000000
1969 #define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
1970 #define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
1971 #define ETH_XMII_TX_INVERT_RESET 0x0 // 0
1972 #define ETH_XMII_GIGE_QUAD_MSB 30
1973 #define ETH_XMII_GIGE_QUAD_LSB 30
1974 #define ETH_XMII_GIGE_QUAD_MASK 0x40000000
1975 #define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
1976 #define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
1977 #define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0
1978 #define ETH_XMII_RX_DELAY_MSB 29
1979 #define ETH_XMII_RX_DELAY_LSB 28
1980 #define ETH_XMII_RX_DELAY_MASK 0x30000000
1981 #define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
1982 #define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
1983 #define ETH_XMII_RX_DELAY_RESET 0x0 // 0
1984 #define ETH_XMII_TX_DELAY_MSB 27
1985 #define ETH_XMII_TX_DELAY_LSB 26
1986 #define ETH_XMII_TX_DELAY_MASK 0x0c000000
1987 #define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
1988 #define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
1989 #define ETH_XMII_TX_DELAY_RESET 0x0 // 0
1990 #define ETH_XMII_GIGE_MSB 25
1991 #define ETH_XMII_GIGE_LSB 25
1992 #define ETH_XMII_GIGE_MASK 0x02000000
1993 #define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
1994 #define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
1995 #define ETH_XMII_GIGE_RESET 0x0 // 0
1996 #define ETH_XMII_OFFSET_PHASE_MSB 24
1997 #define ETH_XMII_OFFSET_PHASE_LSB 24
1998 #define ETH_XMII_OFFSET_PHASE_MASK 0x01000000
1999 #define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
2000 #define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
2001 #define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0
2002 #define ETH_XMII_OFFSET_COUNT_MSB 23
2003 #define ETH_XMII_OFFSET_COUNT_LSB 16
2004 #define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000
2005 #define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
2006 #define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
2007 #define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0
2008 #define ETH_XMII_PHASE1_COUNT_MSB 15
2009 #define ETH_XMII_PHASE1_COUNT_LSB 8
2010 #define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00
2011 #define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
2012 #define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
2013 #define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1
2014 #define ETH_XMII_PHASE0_COUNT_MSB 7
2015 #define ETH_XMII_PHASE0_COUNT_LSB 0
2016 #define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff
2017 #define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
2018 #define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
2019 #define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1
2020 #define ETH_XMII_ADDRESS 0x1805002c
2022 #define BB_PLL_CONFIG_UPDATING_MSB 31
2023 #define BB_PLL_CONFIG_UPDATING_LSB 31
2024 #define BB_PLL_CONFIG_UPDATING_MASK 0x80000000
2025 #define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)
2026 #define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)
2027 #define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1
2028 #define BB_PLL_CONFIG_PLLPWD_MSB 30
2029 #define BB_PLL_CONFIG_PLLPWD_LSB 30
2030 #define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000
2031 #define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)
2032 #define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)
2033 #define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
2034 #define BB_PLL_CONFIG_SPARE_MSB 29
2035 #define BB_PLL_CONFIG_SPARE_LSB 29
2036 #define BB_PLL_CONFIG_SPARE_MASK 0x20000000
2037 #define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)
2038 #define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)
2039 #define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0
2040 #define BB_PLL_CONFIG_REFDIV_MSB 28
2041 #define BB_PLL_CONFIG_REFDIV_LSB 24
2042 #define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000
2043 #define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)
2044 #define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)
2045 #define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1
2046 #define BB_PLL_CONFIG_NINT_MSB 21
2047 #define BB_PLL_CONFIG_NINT_LSB 16
2048 #define BB_PLL_CONFIG_NINT_MASK 0x003f0000
2049 #define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)
2050 #define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)
2051 #define BB_PLL_CONFIG_NINT_RESET 0x2 // 2
2052 #define BB_PLL_CONFIG_NFRAC_MSB 13
2053 #define BB_PLL_CONFIG_NFRAC_LSB 0
2054 #define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff
2055 #define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)
2056 #define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)
2057 #define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276
2058 #define BB_PLL_CONFIG_ADDRESS 0x18050040
2060 #define DDR_PLL_DITHER_DITHER_EN_MSB 31
2061 #define DDR_PLL_DITHER_DITHER_EN_LSB 31
2062 #define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
2063 #define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
2064 #define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
2065 #define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
2066 #define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
2067 #define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
2068 #define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
2069 #define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
2070 #define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
2071 #define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15
2072 #define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
2073 #define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
2074 #define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
2075 #define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
2076 #define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
2077 #define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
2078 #define DDR_PLL_DITHER_NFRAC_MIN_MSB 19
2079 #define DDR_PLL_DITHER_NFRAC_MIN_LSB 10
2080 #define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00
2081 #define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
2082 #define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
2083 #define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25
2084 #define DDR_PLL_DITHER_NFRAC_MAX_MSB 9
2085 #define DDR_PLL_DITHER_NFRAC_MAX_LSB 0
2086 #define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff
2087 #define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
2088 #define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
2089 #define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000
2090 #define DDR_PLL_DITHER_ADDRESS 0x18050044
2092 #define CPU_PLL_DITHER_DITHER_EN_MSB 31
2093 #define CPU_PLL_DITHER_DITHER_EN_LSB 31
2094 #define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
2095 #define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
2096 #define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
2097 #define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
2098 #define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23
2099 #define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
2100 #define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
2101 #define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
2102 #define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
2103 #define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20
2104 #define CPU_PLL_DITHER_NFRAC_STEP_MSB 17
2105 #define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
2106 #define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
2107 #define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
2108 #define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
2109 #define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
2110 #define CPU_PLL_DITHER_NFRAC_MIN_MSB 11
2111 #define CPU_PLL_DITHER_NFRAC_MIN_LSB 6
2112 #define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0
2113 #define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
2114 #define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
2115 #define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3
2116 #define CPU_PLL_DITHER_NFRAC_MAX_MSB 5
2117 #define CPU_PLL_DITHER_NFRAC_MAX_LSB 0
2118 #define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f
2119 #define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
2120 #define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
2121 #define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60
2122 #define CPU_PLL_DITHER_ADDRESS 0x18050048
2124 #define RST_RESET_USB_EXT_PWR_SEQ_MSB 29
2125 #define RST_RESET_USB_EXT_PWR_SEQ_LSB 29
2126 #define RST_RESET_USB_EXT_PWR_SEQ_MASK 0x20000000
2127 #define RST_RESET_USB_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET_USB_EXT_PWR_SEQ_MASK) >> RST_RESET_USB_EXT_PWR_SEQ_LSB)
2128 #define RST_RESET_USB_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET_USB_EXT_PWR_SEQ_LSB) & RST_RESET_USB_EXT_PWR_SEQ_MASK)
2129 #define RST_RESET_USB_EXT_PWR_SEQ_RESET 0x1 // 1
2130 #define RST_RESET_EXTERNAL_RESET_MSB 28
2131 #define RST_RESET_EXTERNAL_RESET_LSB 28
2132 #define RST_RESET_EXTERNAL_RESET_MASK 0x10000000
2133 #define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
2134 #define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
2135 #define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0
2136 #define RST_RESET_RTC_RESET_MSB 27
2137 #define RST_RESET_RTC_RESET_LSB 27
2138 #define RST_RESET_RTC_RESET_MASK 0x08000000
2139 #define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
2140 #define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
2141 #define RST_RESET_RTC_RESET_RESET 0x1 // 1
2142 #define RST_RESET_FULL_CHIP_RESET_MSB 24
2143 #define RST_RESET_FULL_CHIP_RESET_LSB 24
2144 #define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000
2145 #define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)
2146 #define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)
2147 #define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0
2148 #define RST_RESET_GE1_MDIO_RESET_MSB 23
2149 #define RST_RESET_GE1_MDIO_RESET_LSB 23
2150 #define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000
2151 #define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
2152 #define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
2153 #define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1
2154 #define RST_RESET_GE0_MDIO_RESET_MSB 22
2155 #define RST_RESET_GE0_MDIO_RESET_LSB 22
2156 #define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000
2157 #define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
2158 #define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
2159 #define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1
2160 #define RST_RESET_CPU_NMI_MSB 21
2161 #define RST_RESET_CPU_NMI_LSB 21
2162 #define RST_RESET_CPU_NMI_MASK 0x00200000
2163 #define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
2164 #define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
2165 #define RST_RESET_CPU_NMI_RESET 0x0 // 0
2166 #define RST_RESET_CPU_COLD_RESET_MSB 20
2167 #define RST_RESET_CPU_COLD_RESET_LSB 20
2168 #define RST_RESET_CPU_COLD_RESET_MASK 0x00100000
2169 #define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
2170 #define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
2171 #define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0
2172 #define RST_RESET_DDR_RESET_MSB 16
2173 #define RST_RESET_DDR_RESET_LSB 16
2174 #define RST_RESET_DDR_RESET_MASK 0x00010000
2175 #define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
2176 #define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
2177 #define RST_RESET_DDR_RESET_RESET 0x0 // 0
2178 #define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15
2179 #define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15
2180 #define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000
2181 #define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
2182 #define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
2183 #define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0
2184 #define RST_RESET_GE1_MAC_RESET_MSB 13
2185 #define RST_RESET_GE1_MAC_RESET_LSB 13
2186 #define RST_RESET_GE1_MAC_RESET_MASK 0x00002000
2187 #define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
2188 #define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
2189 #define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1
2190 #define RST_RESET_ETH_SWITCH_ARESET_MSB 12
2191 #define RST_RESET_ETH_SWITCH_ARESET_LSB 12
2192 #define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000
2193 #define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB)
2194 #define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK)
2195 #define RST_RESET_ETH_SWITCH_ARESET_RESET 0x1 // 1
2196 #define RST_RESET_USB_PHY_ARESET_MSB 11
2197 #define RST_RESET_USB_PHY_ARESET_LSB 11
2198 #define RST_RESET_USB_PHY_ARESET_MASK 0x00000800
2199 #define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
2200 #define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
2201 #define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1
2202 #define RST_RESET_GE0_MAC_RESET_MSB 9
2203 #define RST_RESET_GE0_MAC_RESET_LSB 9
2204 #define RST_RESET_GE0_MAC_RESET_MASK 0x00000200
2205 #define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
2206 #define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
2207 #define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1
2208 #define RST_RESET_ETH_SWITCH_RESET_MSB 8
2209 #define RST_RESET_ETH_SWITCH_RESET_LSB 8
2210 #define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100
2211 #define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB)
2212 #define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK)
2213 #define RST_RESET_ETH_SWITCH_RESET_RESET 0x1 // 1
2214 #define RST_RESET_PCIE_PHY_RESET_MSB 7
2215 #define RST_RESET_PCIE_PHY_RESET_LSB 7
2216 #define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080
2217 #define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
2218 #define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
2219 #define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1
2220 #define RST_RESET_PCIE_RESET_MSB 6
2221 #define RST_RESET_PCIE_RESET_LSB 6
2222 #define RST_RESET_PCIE_RESET_MASK 0x00000040
2223 #define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
2224 #define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
2225 #define RST_RESET_PCIE_RESET_RESET 0x1 // 1
2226 #define RST_RESET_USB_HOST_RESET_MSB 5
2227 #define RST_RESET_USB_HOST_RESET_LSB 5
2228 #define RST_RESET_USB_HOST_RESET_MASK 0x00000020
2229 #define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
2230 #define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
2231 #define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1
2232 #define RST_RESET_USB_PHY_RESET_MSB 4
2233 #define RST_RESET_USB_PHY_RESET_LSB 4
2234 #define RST_RESET_USB_PHY_RESET_MASK 0x00000010
2235 #define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
2236 #define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
2237 #define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1
2238 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3
2239 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3
2240 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008
2241 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
2242 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
2243 #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0
2244 #define RST_RESET_ADDRESS 0x1806001c
2247 #define RST_MISC2_SPARE_MSB 31
2248 #define RST_MISC2_SPARE_LSB 26
2249 #define RST_MISC2_SPARE_MASK 0xfc000000
2250 #define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB)
2251 #define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK)
2252 #define RST_MISC2_SPARE_RESET 0x0 // 0
2253 #define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 19
2254 #define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 19
2255 #define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x00080000
2256 #define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)
2257 #define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)
2258 #define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0
2259 #define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18
2260 #define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18
2261 #define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000
2262 #define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)
2263 #define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)
2264 #define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0
2265 #define RST_MISC2_PERSTN_RCPHY_MSB 13
2266 #define RST_MISC2_PERSTN_RCPHY_LSB 13
2267 #define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000
2268 #define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)
2269 #define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)
2270 #define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1
2271 #define RST_MISC2_RESERVED_MSB 3
2272 #define RST_MISC2_RESERVED_LSB 1
2273 #define RST_MISC2_RESERVED_MASK 0x0000000e
2274 #define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB)
2275 #define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK)
2276 #define RST_MISC2_RESERVED_RESET 0x0 // 0
2277 #define RST_MISC2_ADDRESS 0x180600bc
2279 #define PCIE_APP_CFG_TYPE_MSB 21
2280 #define PCIE_APP_CFG_TYPE_LSB 20
2281 #define PCIE_APP_CFG_TYPE_MASK 0x00300000
2282 #define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)
2283 #define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)
2284 #define PCIE_APP_CFG_TYPE_RESET 0x0 // 0
2285 #define PCIE_APP_PCIE_BAR_MSN_MSB 19
2286 #define PCIE_APP_PCIE_BAR_MSN_LSB 16
2287 #define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000
2288 #define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)
2289 #define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)
2290 #define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1
2291 #define PCIE_APP_CFG_BE_MSB 15
2292 #define PCIE_APP_CFG_BE_LSB 12
2293 #define PCIE_APP_CFG_BE_MASK 0x0000f000
2294 #define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)
2295 #define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)
2296 #define PCIE_APP_CFG_BE_RESET 0xf // 15
2297 #define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11
2298 #define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6
2299 #define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0
2300 #define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)
2301 #define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)
2302 #define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63
2303 #define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5
2304 #define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4
2305 #define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030
2306 #define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)
2307 #define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)
2308 #define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0
2309 #define PCIE_APP_INIT_RST_MSB 3
2310 #define PCIE_APP_INIT_RST_LSB 3
2311 #define PCIE_APP_INIT_RST_MASK 0x00000008
2312 #define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)
2313 #define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)
2314 #define PCIE_APP_INIT_RST_RESET 0x0 // 0
2315 #define PCIE_APP_PM_XMT_TURNOFF_MSB 2
2316 #define PCIE_APP_PM_XMT_TURNOFF_LSB 2
2317 #define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004
2318 #define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)
2319 #define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)
2320 #define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0
2321 #define PCIE_APP_UNLOCK_MSG_MSB 1
2322 #define PCIE_APP_UNLOCK_MSG_LSB 1
2323 #define PCIE_APP_UNLOCK_MSG_MASK 0x00000002
2324 #define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)
2325 #define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)
2326 #define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0
2327 #define PCIE_APP_LTSSM_ENABLE_MSB 0
2328 #define PCIE_APP_LTSSM_ENABLE_LSB 0
2329 #define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001
2330 #define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)
2331 #define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)
2332 #define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0
2333 #define PCIE_APP_ADDRESS 0x180f0000
2335 #define PCIE_PWR_MGMT_PME_INT_MSB 8
2336 #define PCIE_PWR_MGMT_PME_INT_LSB 8
2337 #define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100
2338 #define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
2339 #define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
2340 #define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0
2341 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7
2342 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7
2343 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080
2344 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
2345 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
2346 #define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0
2347 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6
2348 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6
2349 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040
2350 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
2351 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
2352 #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0
2353 #define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5
2354 #define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5
2355 #define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020
2356 #define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
2357 #define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
2358 #define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0
2359 #define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4
2360 #define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4
2361 #define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010
2362 #define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
2363 #define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
2364 #define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0
2365 #define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3
2366 #define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3
2367 #define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008
2368 #define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
2369 #define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
2370 #define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0
2371 #define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2
2372 #define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2
2373 #define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004
2374 #define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
2375 #define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
2376 #define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0
2377 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1
2378 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1
2379 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002
2380 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
2381 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
2382 #define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0
2383 #define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0
2384 #define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0
2385 #define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001
2386 #define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
2387 #define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
2388 #define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0
2389 #define PCIE_PWR_MGMT_ADDRESS 0x180f0008
2390 #define PCIE_PWR_MGMT_OFFSET 0x0008
2391 // SW modifiable bits
2392 #define PCIE_PWR_MGMT_SW_MASK 0x000001ff
2393 // bits defined at reset
2394 #define PCIE_PWR_MGMT_RSTMASK 0xffffffff
2395 // reset value (ignore bits undefined at reset)
2396 #define PCIE_PWR_MGMT_RESET 0x00000000
2398 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31
2399 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31
2400 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000
2401 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB)
2402 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK)
2403 #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0
2404 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30
2405 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29
2406 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000
2407 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB)
2408 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK)
2409 #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0
2410 #define PCIE_PHY_REG_1_PERSTDELAY_MSB 28
2411 #define PCIE_PHY_REG_1_PERSTDELAY_LSB 27
2412 #define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000
2413 #define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB)
2414 #define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK)
2415 #define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2
2416 #define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26
2417 #define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25
2418 #define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000
2419 #define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB)
2420 #define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK)
2421 #define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0
2422 #define PCIE_PHY_REG_1_DATAOBSEN_MSB 24
2423 #define PCIE_PHY_REG_1_DATAOBSEN_LSB 24
2424 #define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000
2425 #define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB)
2426 #define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK)
2427 #define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0
2428 #define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23
2429 #define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23
2430 #define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000
2431 #define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB)
2432 #define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK)
2433 #define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0
2434 #define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22
2435 #define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22
2436 #define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000
2437 #define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB)
2438 #define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK)
2439 #define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0
2440 #define PCIE_PHY_REG_1_RXCLKINV_MSB 21
2441 #define PCIE_PHY_REG_1_RXCLKINV_LSB 21
2442 #define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000
2443 #define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB)
2444 #define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK)
2445 #define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1
2446 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20
2447 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20
2448 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000
2449 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB)
2450 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK)
2451 #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0
2452 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19
2453 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19
2454 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000
2455 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB)
2456 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK)
2457 #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0
2458 #define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18
2459 #define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18
2460 #define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000
2461 #define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB)
2462 #define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK)
2463 #define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0
2464 #define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17
2465 #define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17
2466 #define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000
2467 #define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB)
2468 #define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK)
2469 #define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0
2470 #define PCIE_PHY_REG_1_SEL_CLK_MSB 16
2471 #define PCIE_PHY_REG_1_SEL_CLK_LSB 15
2472 #define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000
2473 #define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB)
2474 #define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK)
2475 #define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2
2476 #define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14
2477 #define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14
2478 #define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000
2479 #define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB)
2480 #define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK)
2481 #define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0
2482 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13
2483 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13
2484 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000
2485 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB)
2486 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK)
2487 #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1
2488 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12
2489 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12
2490 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000
2491 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)
2492 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)
2493 #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0
2494 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11
2495 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11
2496 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800
2497 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB)
2498 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK)
2499 #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0
2500 #define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10
2501 #define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9
2502 #define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600
2503 #define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB)
2504 #define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK)
2505 #define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3
2506 #define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8
2507 #define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7
2508 #define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180
2509 #define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB)
2510 #define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK)
2511 #define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0
2512 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6
2513 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6
2514 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040
2515 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB)
2516 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK)
2517 #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1
2518 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5
2519 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5
2520 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020
2521 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB)
2522 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK)
2523 #define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0
2524 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4
2525 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4
2526 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010
2527 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB)
2528 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK)
2529 #define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1
2530 #define PCIE_PHY_REG_1_S_MSB 3
2531 #define PCIE_PHY_REG_1_S_LSB 0
2532 #define PCIE_PHY_REG_1_S_MASK 0x0000000f
2533 #define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB)
2534 #define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK)
2535 #define PCIE_PHY_REG_1_S_RESET 0xe // 14
2536 #define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
2537 #define PCIE_PHY_REG_1_OFFSET 0x0000
2538 // SW modifiable bits
2539 #define PCIE_PHY_REG_1_SW_MASK 0xffffffff
2540 // bits defined at reset
2541 #define PCIE_PHY_REG_1_RSTMASK 0xffffffff
2542 // reset value (ignore bits undefined at reset)
2543 #define PCIE_PHY_REG_1_RESET 0x1021265e
2544 #define PCIE_PHY_REG_1_RESET_1 0x0061060e
2546 // 32'h18116cc4 (PCIE_PHY_REG_2)
2547 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MSB 31
2548 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB 24
2549 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK 0xff000000
2550 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB)
2551 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK)
2552 #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_RESET 0x0 // 0
2553 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB 23
2554 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB 23
2555 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK 0x00800000
2556 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB)
2557 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK)
2558 #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET 0x0 // 0
2559 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MSB 22
2560 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB 22
2561 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK 0x00400000
2562 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB)
2563 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK)
2564 #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_RESET 0x0 // 0
2565 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MSB 21
2566 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB 21
2567 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK 0x00200000
2568 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB)
2569 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK)
2570 #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_RESET 0x0 // 0
2571 #define PCIE_PHY_REG_2_PRBS_START_MSB 20
2572 #define PCIE_PHY_REG_2_PRBS_START_LSB 20
2573 #define PCIE_PHY_REG_2_PRBS_START_MASK 0x00100000
2574 #define PCIE_PHY_REG_2_PRBS_START_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_START_MASK) >> PCIE_PHY_REG_2_PRBS_START_LSB)
2575 #define PCIE_PHY_REG_2_PRBS_START_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_START_LSB) & PCIE_PHY_REG_2_PRBS_START_MASK)
2576 #define PCIE_PHY_REG_2_PRBS_START_RESET 0x0 // 0
2577 #define PCIE_PHY_REG_2_PRBS_TS_NUM_MSB 19
2578 #define PCIE_PHY_REG_2_PRBS_TS_NUM_LSB 13
2579 #define PCIE_PHY_REG_2_PRBS_TS_NUM_MASK 0x000fe000
2580 #define PCIE_PHY_REG_2_PRBS_TS_NUM_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_PHY_REG_2_PRBS_TS_NUM_LSB)
2581 #define PCIE_PHY_REG_2_PRBS_TS_NUM_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK)
2582 #define PCIE_PHY_REG_2_PRBS_TS_NUM_RESET 0x40 // 64
2583 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MSB 12
2584 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB 12
2585 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK 0x00001000
2586 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB)
2587 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK)
2588 #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_RESET 0x0 // 0
2589 #define PCIE_PHY_REG_2_TXDETRXOVREN_MSB 11
2590 #define PCIE_PHY_REG_2_TXDETRXOVREN_LSB 11
2591 #define PCIE_PHY_REG_2_TXDETRXOVREN_MASK 0x00000800
2592 #define PCIE_PHY_REG_2_TXDETRXOVREN_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_PHY_REG_2_TXDETRXOVREN_LSB)
2593 #define PCIE_PHY_REG_2_TXDETRXOVREN_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK)
2594 #define PCIE_PHY_REG_2_TXDETRXOVREN_RESET 0x0 // 0
2595 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_MSB 10
2596 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB 10
2597 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK 0x00000400
2598 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_GET(x) (((x) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB)
2599 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_SET(x) (((x) << PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK)
2600 #define PCIE_PHY_REG_2_DATAOBSPRBSERR_RESET 0x0 // 0
2601 #define PCIE_PHY_REG_2_CDRREADYTIMER_MSB 9
2602 #define PCIE_PHY_REG_2_CDRREADYTIMER_LSB 6
2603 #define PCIE_PHY_REG_2_CDRREADYTIMER_MASK 0x000003c0
2604 #define PCIE_PHY_REG_2_CDRREADYTIMER_GET(x) (((x) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_PHY_REG_2_CDRREADYTIMER_LSB)
2605 #define PCIE_PHY_REG_2_CDRREADYTIMER_SET(x) (((x) << PCIE_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK)
2606 #define PCIE_PHY_REG_2_CDRREADYTIMER_RESET 0x7 // 7
2607 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MSB 5
2608 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB 1
2609 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK 0x0000003e
2610 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB)
2611 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK)
2612 #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_RESET 0xc // 12
2613 #define PCIE_PHY_REG_2_FORCEDETECT_MSB 0
2614 #define PCIE_PHY_REG_2_FORCEDETECT_LSB 0
2615 #define PCIE_PHY_REG_2_FORCEDETECT_MASK 0x00000001
2616 #define PCIE_PHY_REG_2_FORCEDETECT_GET(x) (((x) & PCIE_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_PHY_REG_2_FORCEDETECT_LSB)
2617 #define PCIE_PHY_REG_2_FORCEDETECT_SET(x) (((x) << PCIE_PHY_REG_2_FORCEDETECT_LSB) & PCIE_PHY_REG_2_FORCEDETECT_MASK)
2618 #define PCIE_PHY_REG_2_FORCEDETECT_RESET 0x0 // 0
2619 #define PCIE_PHY_REG_2_ADDRESS 0x18116cc4
2620 #define PCIE_PHY_REG_2_OFFSET 0x0004
2621 // SW modifiable bits
2622 #define PCIE_PHY_REG_2_SW_MASK 0xffffffff
2623 // bits defined at reset
2624 #define PCIE_PHY_REG_2_RSTMASK 0xffffffff
2625 // reset value (ignore bits undefined at reset)
2626 #define PCIE_PHY_REG_2_RESET 0x000801d8
2628 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MSB 31
2629 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB 28
2630 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK 0xf0000000
2631 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_GET(x) (((x) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB)
2632 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_SET(x) (((x) << PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK)
2633 #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_RESET 0x0 // 0
2634 #define PCIE_PHY_REG_3_SPARE_MSB 27
2635 #define PCIE_PHY_REG_3_SPARE_LSB 11
2636 #define PCIE_PHY_REG_3_SPARE_MASK 0x0ffff800
2637 #define PCIE_PHY_REG_3_SPARE_GET(x) (((x) & PCIE_PHY_REG_3_SPARE_MASK) >> PCIE_PHY_REG_3_SPARE_LSB)
2638 #define PCIE_PHY_REG_3_SPARE_SET(x) (((x) << PCIE_PHY_REG_3_SPARE_LSB) & PCIE_PHY_REG_3_SPARE_MASK)
2639 #define PCIE_PHY_REG_3_SPARE_RESET 0xa0b // 2571
2640 #define PCIE_PHY_REG_3_SEL_CLK100_MSB 10
2641 #define PCIE_PHY_REG_3_SEL_CLK100_LSB 10
2642 #define PCIE_PHY_REG_3_SEL_CLK100_MASK 0x00000400
2643 #define PCIE_PHY_REG_3_SEL_CLK100_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_PHY_REG_3_SEL_CLK100_LSB)
2644 #define PCIE_PHY_REG_3_SEL_CLK100_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK100_LSB) & PCIE_PHY_REG_3_SEL_CLK100_MASK)
2645 #define PCIE_PHY_REG_3_SEL_CLK100_RESET 0x0 // 0
2646 #define PCIE_PHY_REG_3_EN_BEACONGEN_MSB 9
2647 #define PCIE_PHY_REG_3_EN_BEACONGEN_LSB 9
2648 #define PCIE_PHY_REG_3_EN_BEACONGEN_MASK 0x00000200
2649 #define PCIE_PHY_REG_3_EN_BEACONGEN_GET(x) (((x) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_PHY_REG_3_EN_BEACONGEN_LSB)
2650 #define PCIE_PHY_REG_3_EN_BEACONGEN_SET(x) (((x) << PCIE_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK)
2651 #define PCIE_PHY_REG_3_EN_BEACONGEN_RESET 0x0 // 0
2652 #define PCIE_PHY_REG_3_TXELECIDLE_MSB 8
2653 #define PCIE_PHY_REG_3_TXELECIDLE_LSB 8
2654 #define PCIE_PHY_REG_3_TXELECIDLE_MASK 0x00000100
2655 #define PCIE_PHY_REG_3_TXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_PHY_REG_3_TXELECIDLE_LSB)
2656 #define PCIE_PHY_REG_3_TXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_3_TXELECIDLE_LSB) & PCIE_PHY_REG_3_TXELECIDLE_MASK)
2657 #define PCIE_PHY_REG_3_TXELECIDLE_RESET 0x0 // 0
2658 #define PCIE_PHY_REG_3_SEL_CLK_MSB 7
2659 #define PCIE_PHY_REG_3_SEL_CLK_LSB 6
2660 #define PCIE_PHY_REG_3_SEL_CLK_MASK 0x000000c0
2661 #define PCIE_PHY_REG_3_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK_MASK) >> PCIE_PHY_REG_3_SEL_CLK_LSB)
2662 #define PCIE_PHY_REG_3_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK_LSB) & PCIE_PHY_REG_3_SEL_CLK_MASK)
2663 #define PCIE_PHY_REG_3_SEL_CLK_RESET 0x0 // 0
2664 #define PCIE_PHY_REG_3_RX_DET_REQ_MSB 5
2665 #define PCIE_PHY_REG_3_RX_DET_REQ_LSB 5
2666 #define PCIE_PHY_REG_3_RX_DET_REQ_MASK 0x00000020
2667 #define PCIE_PHY_REG_3_RX_DET_REQ_GET(x) (((x) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_PHY_REG_3_RX_DET_REQ_LSB)
2668 #define PCIE_PHY_REG_3_RX_DET_REQ_SET(x) (((x) << PCIE_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_PHY_REG_3_RX_DET_REQ_MASK)
2669 #define PCIE_PHY_REG_3_RX_DET_REQ_RESET 0x0 // 0
2670 #define PCIE_PHY_REG_3_MODE_OCLK_IN_MSB 4
2671 #define PCIE_PHY_REG_3_MODE_OCLK_IN_LSB 4
2672 #define PCIE_PHY_REG_3_MODE_OCLK_IN_MASK 0x00000010
2673 #define PCIE_PHY_REG_3_MODE_OCLK_IN_GET(x) (((x) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_PHY_REG_3_MODE_OCLK_IN_LSB)
2674 #define PCIE_PHY_REG_3_MODE_OCLK_IN_SET(x) (((x) << PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK)
2675 #define PCIE_PHY_REG_3_MODE_OCLK_IN_RESET 0x0 // 0
2676 #define PCIE_PHY_REG_3_EN_PLL_MSB 3
2677 #define PCIE_PHY_REG_3_EN_PLL_LSB 3
2678 #define PCIE_PHY_REG_3_EN_PLL_MASK 0x00000008
2679 #define PCIE_PHY_REG_3_EN_PLL_GET(x) (((x) & PCIE_PHY_REG_3_EN_PLL_MASK) >> PCIE_PHY_REG_3_EN_PLL_LSB)
2680 #define PCIE_PHY_REG_3_EN_PLL_SET(x) (((x) << PCIE_PHY_REG_3_EN_PLL_LSB) & PCIE_PHY_REG_3_EN_PLL_MASK)
2681 #define PCIE_PHY_REG_3_EN_PLL_RESET 0x1 // 1
2682 #define PCIE_PHY_REG_3_EN_LCKDT_MSB 2
2683 #define PCIE_PHY_REG_3_EN_LCKDT_LSB 2
2684 #define PCIE_PHY_REG_3_EN_LCKDT_MASK 0x00000004
2685 #define PCIE_PHY_REG_3_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_PHY_REG_3_EN_LCKDT_LSB)
2686 #define PCIE_PHY_REG_3_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_3_EN_LCKDT_LSB) & PCIE_PHY_REG_3_EN_LCKDT_MASK)
2687 #define PCIE_PHY_REG_3_EN_LCKDT_RESET 0x1 // 1
2688 #define PCIE_PHY_REG_3_EN_BUFS_RX_MSB 1
2689 #define PCIE_PHY_REG_3_EN_BUFS_RX_LSB 1
2690 #define PCIE_PHY_REG_3_EN_BUFS_RX_MASK 0x00000002
2691 #define PCIE_PHY_REG_3_EN_BUFS_RX_GET(x) (((x) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_PHY_REG_3_EN_BUFS_RX_LSB)
2692 #define PCIE_PHY_REG_3_EN_BUFS_RX_SET(x) (((x) << PCIE_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK)
2693 #define PCIE_PHY_REG_3_EN_BUFS_RX_RESET 0x0 // 0
2694 #define PCIE_PHY_REG_3_EN_MSB 0
2695 #define PCIE_PHY_REG_3_EN_LSB 0
2696 #define PCIE_PHY_REG_3_EN_MASK 0x00000001
2697 #define PCIE_PHY_REG_3_EN_GET(x) (((x) & PCIE_PHY_REG_3_EN_MASK) >> PCIE_PHY_REG_3_EN_LSB)
2698 #define PCIE_PHY_REG_3_EN_SET(x) (((x) << PCIE_PHY_REG_3_EN_LSB) & PCIE_PHY_REG_3_EN_MASK)
2699 #define PCIE_PHY_REG_3_EN_RESET 0x0 // 0
2700 #define PCIE_PHY_REG_3_ADDRESS 0x18116cc8
2701 #define PCIE_PHY_REG_3_OFFSET 0x0008
2702 // SW modifiable bits
2703 #define PCIE_PHY_REG_3_SW_MASK 0xffffffff
2704 // bits defined at reset
2705 #define PCIE_PHY_REG_3_RSTMASK 0xffffffff
2706 // reset value (ignore bits undefined at reset)
2707 #define PCIE_PHY_REG_3_RESET 0x0050580c
2708 #define PCIE_PHY_REG_3_RESET_1 0x00505900
2710 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MSB 31
2711 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB 11
2712 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK 0xfffff800
2713 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) >> PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB)
2714 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK)
2715 #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_RESET 0xa000 // 40960
2716 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MSB 10
2717 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB 1
2718 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe
2719 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) >> PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB)
2720 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK)
2721 #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0
2722 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MSB 0
2723 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB 0
2724 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK 0x00000001
2725 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) >> PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB)
2726 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK)
2727 #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_RESET 0x0 // 0
2728 #define PCIE_PHY_REG_4_ADDRESS 0x18116ccc
2729 #define PCIE_PHY_REG_4_OFFSET 0x000c
2730 // SW modifiable bits
2731 #define PCIE_PHY_REG_4_SW_MASK 0xffffffff
2732 // bits defined at reset
2733 #define PCIE_PHY_REG_4_RSTMASK 0xffffffff
2734 // reset value (ignore bits undefined at reset)
2735 #define PCIE_PHY_REG_4_RESET 0x05000000
2737 #define XTAL_TCXODET_MSB 31
2738 #define XTAL_TCXODET_LSB 31
2739 #define XTAL_TCXODET_MASK 0x80000000
2740 #define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB)
2741 #define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK)
2742 #define XTAL_TCXODET_RESET 0x0 // 0
2743 #define XTAL_XTAL_CAPINDAC_MSB 30
2744 #define XTAL_XTAL_CAPINDAC_LSB 24
2745 #define XTAL_XTAL_CAPINDAC_MASK 0x7f000000
2746 #define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB)
2747 #define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK)
2748 #define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75
2749 #define XTAL_XTAL_CAPOUTDAC_MSB 23
2750 #define XTAL_XTAL_CAPOUTDAC_LSB 17
2751 #define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000
2752 #define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB)
2753 #define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK)
2754 #define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75
2755 #define XTAL_XTAL_DRVSTR_MSB 16
2756 #define XTAL_XTAL_DRVSTR_LSB 15
2757 #define XTAL_XTAL_DRVSTR_MASK 0x00018000
2758 #define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB)
2759 #define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK)
2760 #define XTAL_XTAL_DRVSTR_RESET 0x0 // 0
2761 #define XTAL_XTAL_SHORTXIN_MSB 14
2762 #define XTAL_XTAL_SHORTXIN_LSB 14
2763 #define XTAL_XTAL_SHORTXIN_MASK 0x00004000
2764 #define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB)
2765 #define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK)
2766 #define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0
2767 #define XTAL_XTAL_LOCALBIAS_MSB 13
2768 #define XTAL_XTAL_LOCALBIAS_LSB 13
2769 #define XTAL_XTAL_LOCALBIAS_MASK 0x00002000
2770 #define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB)
2771 #define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK)
2772 #define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1
2773 #define XTAL_XTAL_PWDCLKD_MSB 12
2774 #define XTAL_XTAL_PWDCLKD_LSB 12
2775 #define XTAL_XTAL_PWDCLKD_MASK 0x00001000
2776 #define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB)
2777 #define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK)
2778 #define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0
2779 #define XTAL_XTAL_BIAS2X_MSB 11
2780 #define XTAL_XTAL_BIAS2X_LSB 11
2781 #define XTAL_XTAL_BIAS2X_MASK 0x00000800
2782 #define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB)
2783 #define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK)
2784 #define XTAL_XTAL_BIAS2X_RESET 0x0 // 0
2785 #define XTAL_XTAL_LBIAS2X_MSB 10
2786 #define XTAL_XTAL_LBIAS2X_LSB 10
2787 #define XTAL_XTAL_LBIAS2X_MASK 0x00000400
2788 #define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB)
2789 #define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK)
2790 #define XTAL_XTAL_LBIAS2X_RESET 0x0 // 0
2791 #define XTAL_XTAL_SELVREG_MSB 9
2792 #define XTAL_XTAL_SELVREG_LSB 9
2793 #define XTAL_XTAL_SELVREG_MASK 0x00000200
2794 #define XTAL_XTAL_SELVREG_GET(x) (((x) & XTAL_XTAL_SELVREG_MASK) >> XTAL_XTAL_SELVREG_LSB)
2795 #define XTAL_XTAL_SELVREG_SET(x) (((x) << XTAL_XTAL_SELVREG_LSB) & XTAL_XTAL_SELVREG_MASK)
2796 #define XTAL_XTAL_SELVREG_RESET 0x0 // 0
2797 #define XTAL_XTAL_OSCON_MSB 8
2798 #define XTAL_XTAL_OSCON_LSB 8
2799 #define XTAL_XTAL_OSCON_MASK 0x00000100
2800 #define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB)
2801 #define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK)
2802 #define XTAL_XTAL_OSCON_RESET 0x1 // 1
2803 #define XTAL_XTAL_PWDCLKIN_MSB 7
2804 #define XTAL_XTAL_PWDCLKIN_LSB 7
2805 #define XTAL_XTAL_PWDCLKIN_MASK 0x00000080
2806 #define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB)
2807 #define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK)
2808 #define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0
2809 #define XTAL_LOCAL_XTAL_MSB 6
2810 #define XTAL_LOCAL_XTAL_LSB 6
2811 #define XTAL_LOCAL_XTAL_MASK 0x00000040
2812 #define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB)
2813 #define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK)
2814 #define XTAL_LOCAL_XTAL_RESET 0x0 // 0
2815 #define XTAL_PWD_SWREGCLK_MSB 5
2816 #define XTAL_PWD_SWREGCLK_LSB 5
2817 #define XTAL_PWD_SWREGCLK_MASK 0x00000020
2818 #define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB)
2819 #define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK)
2820 #define XTAL_PWD_SWREGCLK_RESET 0x0 // 0
2821 #define XTAL_LOCAL_EXT_CLK_OUT_EN_MSB 4
2822 #define XTAL_LOCAL_EXT_CLK_OUT_EN_LSB 4
2823 #define XTAL_LOCAL_EXT_CLK_OUT_EN_MASK 0x00000010
2824 #define XTAL_LOCAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) >> XTAL_LOCAL_EXT_CLK_OUT_EN_LSB)
2825 #define XTAL_LOCAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK)
2826 #define XTAL_LOCAL_EXT_CLK_OUT_EN_RESET 0x0 // 0
2827 #define XTAL_EXT_CLK_OUT_EN_MSB 3
2828 #define XTAL_EXT_CLK_OUT_EN_LSB 3
2829 #define XTAL_EXT_CLK_OUT_EN_MASK 0x00000008
2830 #define XTAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_EXT_CLK_OUT_EN_MASK) >> XTAL_EXT_CLK_OUT_EN_LSB)
2831 #define XTAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_EXT_CLK_OUT_EN_LSB) & XTAL_EXT_CLK_OUT_EN_MASK)
2832 #define XTAL_EXT_CLK_OUT_EN_RESET 0x0 // 0
2833 #define XTAL_XTAL_SVREG_MSB 2
2834 #define XTAL_XTAL_SVREG_LSB 2
2835 #define XTAL_XTAL_SVREG_MASK 0x00000004
2836 #define XTAL_XTAL_SVREG_GET(x) (((x) & XTAL_XTAL_SVREG_MASK) >> XTAL_XTAL_SVREG_LSB)
2837 #define XTAL_XTAL_SVREG_SET(x) (((x) << XTAL_XTAL_SVREG_LSB) & XTAL_XTAL_SVREG_MASK)
2838 #define XTAL_XTAL_SVREG_RESET 0x0 // 0
2839 #define XTAL_RBK_UDSEL_MSB 1
2840 #define XTAL_RBK_UDSEL_LSB 1
2841 #define XTAL_RBK_UDSEL_MASK 0x00000002
2842 #define XTAL_RBK_UDSEL_GET(x) (((x) & XTAL_RBK_UDSEL_MASK) >> XTAL_RBK_UDSEL_LSB)
2843 #define XTAL_RBK_UDSEL_SET(x) (((x) << XTAL_RBK_UDSEL_LSB) & XTAL_RBK_UDSEL_MASK)
2844 #define XTAL_RBK_UDSEL_RESET 0x0 // 0
2845 #define XTAL_SPARE_MSB 0
2846 #define XTAL_SPARE_LSB 0
2847 #define XTAL_SPARE_MASK 0x00000001
2848 #define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB)
2849 #define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK)
2850 #define XTAL_SPARE_RESET 0x0 // 0
2851 #define XTAL_ADDRESS 0x181162c0
2853 #define XTAL2_TDC_COUNT_MSB 31
2854 #define XTAL2_TDC_COUNT_LSB 26
2855 #define XTAL2_TDC_COUNT_MASK 0xfc000000
2856 #define XTAL2_TDC_COUNT_GET(x) (((x) & XTAL2_TDC_COUNT_MASK) >> XTAL2_TDC_COUNT_LSB)
2857 #define XTAL2_TDC_COUNT_SET(x) (((x) << XTAL2_TDC_COUNT_LSB) & XTAL2_TDC_COUNT_MASK)
2858 #define XTAL2_TDC_COUNT_RESET 0x0 // 0
2859 #define XTAL2_TDC_PH_COUNT_MSB 25
2860 #define XTAL2_TDC_PH_COUNT_LSB 21
2861 #define XTAL2_TDC_PH_COUNT_MASK 0x03e00000
2862 #define XTAL2_TDC_PH_COUNT_GET(x) (((x) & XTAL2_TDC_PH_COUNT_MASK) >> XTAL2_TDC_PH_COUNT_LSB)
2863 #define XTAL2_TDC_PH_COUNT_SET(x) (((x) << XTAL2_TDC_PH_COUNT_LSB) & XTAL2_TDC_PH_COUNT_MASK)
2864 #define XTAL2_TDC_PH_COUNT_RESET 0x0 // 0
2865 #define XTAL2_DUTY_UP_MSB 20
2866 #define XTAL2_DUTY_UP_LSB 16
2867 #define XTAL2_DUTY_UP_MASK 0x001f0000
2868 #define XTAL2_DUTY_UP_GET(x) (((x) & XTAL2_DUTY_UP_MASK) >> XTAL2_DUTY_UP_LSB)
2869 #define XTAL2_DUTY_UP_SET(x) (((x) << XTAL2_DUTY_UP_LSB) & XTAL2_DUTY_UP_MASK)
2870 #define XTAL2_DUTY_UP_RESET 0x0 // 0
2871 #define XTAL2_DUTY_DN_MSB 15
2872 #define XTAL2_DUTY_DN_LSB 11
2873 #define XTAL2_DUTY_DN_MASK 0x0000f800
2874 #define XTAL2_DUTY_DN_GET(x) (((x) & XTAL2_DUTY_DN_MASK) >> XTAL2_DUTY_DN_LSB)
2875 #define XTAL2_DUTY_DN_SET(x) (((x) << XTAL2_DUTY_DN_LSB) & XTAL2_DUTY_DN_MASK)
2876 #define XTAL2_DUTY_DN_RESET 0x0 // 0
2877 #define XTAL2_DCA_BYPASS_MSB 10
2878 #define XTAL2_DCA_BYPASS_LSB 10
2879 #define XTAL2_DCA_BYPASS_MASK 0x00000400
2880 #define XTAL2_DCA_BYPASS_GET(x) (((x) & XTAL2_DCA_BYPASS_MASK) >> XTAL2_DCA_BYPASS_LSB)
2881 #define XTAL2_DCA_BYPASS_SET(x) (((x) << XTAL2_DCA_BYPASS_LSB) & XTAL2_DCA_BYPASS_MASK)
2882 #define XTAL2_DCA_BYPASS_RESET 0x1 // 1
2883 #define XTAL2_DCA_SWCAL_MSB 9
2884 #define XTAL2_DCA_SWCAL_LSB 9
2885 #define XTAL2_DCA_SWCAL_MASK 0x00000200
2886 #define XTAL2_DCA_SWCAL_GET(x) (((x) & XTAL2_DCA_SWCAL_MASK) >> XTAL2_DCA_SWCAL_LSB)
2887 #define XTAL2_DCA_SWCAL_SET(x) (((x) << XTAL2_DCA_SWCAL_LSB) & XTAL2_DCA_SWCAL_MASK)
2888 #define XTAL2_DCA_SWCAL_RESET 0x0 // 0
2889 #define XTAL2_FSM_UD_HOLD_MSB 8
2890 #define XTAL2_FSM_UD_HOLD_LSB 8
2891 #define XTAL2_FSM_UD_HOLD_MASK 0x00000100
2892 #define XTAL2_FSM_UD_HOLD_GET(x) (((x) & XTAL2_FSM_UD_HOLD_MASK) >> XTAL2_FSM_UD_HOLD_LSB)
2893 #define XTAL2_FSM_UD_HOLD_SET(x) (((x) << XTAL2_FSM_UD_HOLD_LSB) & XTAL2_FSM_UD_HOLD_MASK)
2894 #define XTAL2_FSM_UD_HOLD_RESET 0x0 // 0
2895 #define XTAL2_FSM_START_L_MSB 7
2896 #define XTAL2_FSM_START_L_LSB 7
2897 #define XTAL2_FSM_START_L_MASK 0x00000080
2898 #define XTAL2_FSM_START_L_GET(x) (((x) & XTAL2_FSM_START_L_MASK) >> XTAL2_FSM_START_L_LSB)
2899 #define XTAL2_FSM_START_L_SET(x) (((x) << XTAL2_FSM_START_L_LSB) & XTAL2_FSM_START_L_MASK)
2900 #define XTAL2_FSM_START_L_RESET 0x1 // 1
2901 #define XTAL2_FSM_DN_READBACK_MSB 6
2902 #define XTAL2_FSM_DN_READBACK_LSB 2
2903 #define XTAL2_FSM_DN_READBACK_MASK 0x0000007c
2904 #define XTAL2_FSM_DN_READBACK_GET(x) (((x) & XTAL2_FSM_DN_READBACK_MASK) >> XTAL2_FSM_DN_READBACK_LSB)
2905 #define XTAL2_FSM_DN_READBACK_SET(x) (((x) << XTAL2_FSM_DN_READBACK_LSB) & XTAL2_FSM_DN_READBACK_MASK)
2906 #define XTAL2_FSM_DN_READBACK_RESET 0x0 // 0
2907 #define XTAL2_TDC_SAT_FLAG_MSB 1
2908 #define XTAL2_TDC_SAT_FLAG_LSB 1
2909 #define XTAL2_TDC_SAT_FLAG_MASK 0x00000002
2910 #define XTAL2_TDC_SAT_FLAG_GET(x) (((x) & XTAL2_TDC_SAT_FLAG_MASK) >> XTAL2_TDC_SAT_FLAG_LSB)
2911 #define XTAL2_TDC_SAT_FLAG_SET(x) (((x) << XTAL2_TDC_SAT_FLAG_LSB) & XTAL2_TDC_SAT_FLAG_MASK)
2912 #define XTAL2_TDC_SAT_FLAG_RESET 0x0 // 0
2913 #define XTAL2_FSM_READY_MSB 0
2914 #define XTAL2_FSM_READY_LSB 0
2915 #define XTAL2_FSM_READY_MASK 0x00000001
2916 #define XTAL2_FSM_READY_GET(x) (((x) & XTAL2_FSM_READY_MASK) >> XTAL2_FSM_READY_LSB)
2917 #define XTAL2_FSM_READY_SET(x) (((x) << XTAL2_FSM_READY_LSB) & XTAL2_FSM_READY_MASK)
2918 #define XTAL2_FSM_READY_RESET 0x0 // 0
2919 #define XTAL2_ADDRESS 0x181162c4
2921 #define XTAL3_FSM_UP_READBACK_MSB 31
2922 #define XTAL3_FSM_UP_READBACK_LSB 27
2923 #define XTAL3_FSM_UP_READBACK_MASK 0xf8000000
2924 #define XTAL3_FSM_UP_READBACK_GET(x) (((x) & XTAL3_FSM_UP_READBACK_MASK) >> XTAL3_FSM_UP_READBACK_LSB)
2925 #define XTAL3_FSM_UP_READBACK_SET(x) (((x) << XTAL3_FSM_UP_READBACK_LSB) & XTAL3_FSM_UP_READBACK_MASK)
2926 #define XTAL3_FSM_UP_READBACK_RESET 0x0 // 0
2927 #define XTAL3_EVAL_LENGTH_MSB 26
2928 #define XTAL3_EVAL_LENGTH_LSB 16
2929 #define XTAL3_EVAL_LENGTH_MASK 0x07ff0000
2930 #define XTAL3_EVAL_LENGTH_GET(x) (((x) & XTAL3_EVAL_LENGTH_MASK) >> XTAL3_EVAL_LENGTH_LSB)
2931 #define XTAL3_EVAL_LENGTH_SET(x) (((x) << XTAL3_EVAL_LENGTH_LSB) & XTAL3_EVAL_LENGTH_MASK)
2932 #define XTAL3_EVAL_LENGTH_RESET 0x400 // 1024
2933 #define XTAL3_TDC_ERROR_FLAG_MSB 15
2934 #define XTAL3_TDC_ERROR_FLAG_LSB 15
2935 #define XTAL3_TDC_ERROR_FLAG_MASK 0x00008000
2936 #define XTAL3_TDC_ERROR_FLAG_GET(x) (((x) & XTAL3_TDC_ERROR_FLAG_MASK) >> XTAL3_TDC_ERROR_FLAG_LSB)
2937 #define XTAL3_TDC_ERROR_FLAG_SET(x) (((x) << XTAL3_TDC_ERROR_FLAG_LSB) & XTAL3_TDC_ERROR_FLAG_MASK)
2938 #define XTAL3_TDC_ERROR_FLAG_RESET 0x0 // 0
2939 #define XTAL3_HARMONIC_NUMBER_MSB 14
2940 #define XTAL3_HARMONIC_NUMBER_LSB 2
2941 #define XTAL3_HARMONIC_NUMBER_MASK 0x00007ffc
2942 #define XTAL3_HARMONIC_NUMBER_GET(x) (((x) & XTAL3_HARMONIC_NUMBER_MASK) >> XTAL3_HARMONIC_NUMBER_LSB)
2943 #define XTAL3_HARMONIC_NUMBER_SET(x) (((x) << XTAL3_HARMONIC_NUMBER_LSB) & XTAL3_HARMONIC_NUMBER_MASK)
2944 #define XTAL3_HARMONIC_NUMBER_RESET 0x51 // 81
2945 #define XTAL3_SPARE_MSB 1
2946 #define XTAL3_SPARE_LSB 0
2947 #define XTAL3_SPARE_MASK 0x00000003
2948 #define XTAL3_SPARE_GET(x) (((x) & XTAL3_SPARE_MASK) >> XTAL3_SPARE_LSB)
2949 #define XTAL3_SPARE_SET(x) (((x) << XTAL3_SPARE_LSB) & XTAL3_SPARE_MASK)
2950 #define XTAL3_SPARE_RESET 0x0 // 0
2951 #define XTAL3_ADDRESS 0x181162c8
2953 #define RST_REVISION_ID_ADDRESS 0x18060090
2954 #define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000))
2956 #define RST_BOOTSTRAP_RES4_MSB 15
2957 #define RST_BOOTSTRAP_RES4_LSB 13
2958 #define RST_BOOTSTRAP_RES4_MASK 0x0000e000
2959 #define RST_BOOTSTRAP_RES4_GET(x) (((x) & RST_BOOTSTRAP_RES4_MASK) >> RST_BOOTSTRAP_RES4_LSB)
2960 #define RST_BOOTSTRAP_RES4_SET(x) (((x) << RST_BOOTSTRAP_RES4_LSB) & RST_BOOTSTRAP_RES4_MASK)
2961 #define RST_BOOTSTRAP_RES4_RESET 0x0 // 0
2962 #define RST_BOOTSTRAP_SW_OPTION2_MSB 12
2963 #define RST_BOOTSTRAP_SW_OPTION2_LSB 12
2964 #define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000
2965 #define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)
2966 #define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)
2967 #define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0
2968 #define RST_BOOTSTRAP_SW_OPTION1_MSB 11
2969 #define RST_BOOTSTRAP_SW_OPTION1_LSB 11
2970 #define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800
2971 #define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)
2972 #define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)
2973 #define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0
2974 #define RST_BOOTSTRAP_TESTROM_ENABLE_MSB 10
2975 #define RST_BOOTSTRAP_TESTROM_ENABLE_LSB 10
2976 #define RST_BOOTSTRAP_TESTROM_ENABLE_MASK 0x00000400
2977 #define RST_BOOTSTRAP_TESTROM_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) >> RST_BOOTSTRAP_TESTROM_ENABLE_LSB)
2978 #define RST_BOOTSTRAP_TESTROM_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_ENABLE_LSB) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK)
2979 #define RST_BOOTSTRAP_TESTROM_ENABLE_RESET 0x0 // 0
2980 #define RST_BOOTSTRAP_RES3_MSB 9
2981 #define RST_BOOTSTRAP_RES3_LSB 9
2982 #define RST_BOOTSTRAP_RES3_MASK 0x00000200
2983 #define RST_BOOTSTRAP_RES3_GET(x) (((x) & RST_BOOTSTRAP_RES3_MASK) >> RST_BOOTSTRAP_RES3_LSB)
2984 #define RST_BOOTSTRAP_RES3_SET(x) (((x) << RST_BOOTSTRAP_RES3_LSB) & RST_BOOTSTRAP_RES3_MASK)
2985 #define RST_BOOTSTRAP_RES3_RESET 0x0 // 0
2986 #define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8
2987 #define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8
2988 #define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100
2989 #define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)
2990 #define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)
2991 #define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0
2992 #define RST_BOOTSTRAP_USB_MODE_MSB 7
2993 #define RST_BOOTSTRAP_USB_MODE_LSB 7
2994 #define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080
2995 #define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)
2996 #define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)
2997 #define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0
2998 #define RST_BOOTSTRAP_RES2_MSB 6
2999 #define RST_BOOTSTRAP_RES2_LSB 6
3000 #define RST_BOOTSTRAP_RES2_MASK 0x00000040
3001 #define RST_BOOTSTRAP_RES2_GET(x) (((x) & RST_BOOTSTRAP_RES2_MASK) >> RST_BOOTSTRAP_RES2_LSB)
3002 #define RST_BOOTSTRAP_RES2_SET(x) (((x) << RST_BOOTSTRAP_RES2_LSB) & RST_BOOTSTRAP_RES2_MASK)
3003 #define RST_BOOTSTRAP_RES2_RESET 0x0 // 0
3004 #define RST_BOOTSTRAP_EJTAG_MODE_MSB 5
3005 #define RST_BOOTSTRAP_EJTAG_MODE_LSB 5
3006 #define RST_BOOTSTRAP_EJTAG_MODE_MASK 0x00000020
3007 #define RST_BOOTSTRAP_EJTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_EJTAG_MODE_MASK) >> RST_BOOTSTRAP_EJTAG_MODE_LSB)
3008 #define RST_BOOTSTRAP_EJTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_EJTAG_MODE_LSB) & RST_BOOTSTRAP_EJTAG_MODE_MASK)
3009 #define RST_BOOTSTRAP_EJTAG_MODE_RESET 0x0 // 0
3010 #define RST_BOOTSTRAP_REF_CLK_MSB 4
3011 #define RST_BOOTSTRAP_REF_CLK_LSB 4
3012 #define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010
3013 #define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)
3014 #define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)
3015 #define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0
3016 #define RST_BOOTSTRAP_RES1_MSB 3
3017 #define RST_BOOTSTRAP_RES1_LSB 3
3018 #define RST_BOOTSTRAP_RES1_MASK 0x00000008
3019 #define RST_BOOTSTRAP_RES1_GET(x) (((x) & RST_BOOTSTRAP_RES1_MASK) >> RST_BOOTSTRAP_RES1_LSB)
3020 #define RST_BOOTSTRAP_RES1_SET(x) (((x) << RST_BOOTSTRAP_RES1_LSB) & RST_BOOTSTRAP_RES1_MASK)
3021 #define RST_BOOTSTRAP_RES1_RESET 0x0 // 0
3022 #define RST_BOOTSTRAP_RES0_MSB 2
3023 #define RST_BOOTSTRAP_RES0_LSB 2
3024 #define RST_BOOTSTRAP_RES0_MASK 0x00000004
3025 #define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)
3026 #define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)
3027 #define RST_BOOTSTRAP_RES0_RESET 0x0 // 0
3028 #define RST_BOOTSTRAP_SDRAM_SELECT_MSB 1
3029 #define RST_BOOTSTRAP_SDRAM_SELECT_LSB 1
3030 #define RST_BOOTSTRAP_SDRAM_SELECT_MASK 0x00000002
3031 #define RST_BOOTSTRAP_SDRAM_SELECT_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) >> RST_BOOTSTRAP_SDRAM_SELECT_LSB)
3032 #define RST_BOOTSTRAP_SDRAM_SELECT_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_SELECT_LSB) & RST_BOOTSTRAP_SDRAM_SELECT_MASK)
3033 #define RST_BOOTSTRAP_SDRAM_SELECT_RESET 0x0 // 0
3034 #define RST_BOOTSTRAP_DDR_SELECT_MSB 0
3035 #define RST_BOOTSTRAP_DDR_SELECT_LSB 0
3036 #define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001
3037 #define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)
3038 #define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)
3039 #define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0
3040 #define RST_BOOTSTRAP_ADDRESS 0x180600b0
3042 #define RST_CLKGAT_EN_SPARE_MSB 31
3043 #define RST_CLKGAT_EN_SPARE_LSB 12
3044 #define RST_CLKGAT_EN_SPARE_MASK 0xfffff000
3045 #define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB)
3046 #define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK)
3047 #define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0
3048 #define RST_CLKGAT_EN_WMAC_MSB 9
3049 #define RST_CLKGAT_EN_WMAC_LSB 9
3050 #define RST_CLKGAT_EN_WMAC_MASK 0x00000200
3051 #define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)
3052 #define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)
3053 #define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1
3054 #define RST_CLKGAT_EN_USB1_MSB 7
3055 #define RST_CLKGAT_EN_USB1_LSB 7
3056 #define RST_CLKGAT_EN_USB1_MASK 0x00000080
3057 #define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)
3058 #define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)
3059 #define RST_CLKGAT_EN_USB1_RESET 0x1 // 1
3060 #define RST_CLKGAT_EN_GE1_MSB 6
3061 #define RST_CLKGAT_EN_GE1_LSB 6
3062 #define RST_CLKGAT_EN_GE1_MASK 0x00000040
3063 #define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)
3064 #define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)
3065 #define RST_CLKGAT_EN_GE1_RESET 0x1 // 1
3066 #define RST_CLKGAT_EN_GE0_MSB 5
3067 #define RST_CLKGAT_EN_GE0_LSB 5
3068 #define RST_CLKGAT_EN_GE0_MASK 0x00000020
3069 #define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)
3070 #define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)
3071 #define RST_CLKGAT_EN_GE0_RESET 0x1 // 1
3072 #define RST_CLKGAT_EN_PCIE_RC_MSB 1
3073 #define RST_CLKGAT_EN_PCIE_RC_LSB 1
3074 #define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002
3075 #define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)
3076 #define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)
3077 #define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1
3078 #define RST_CLKGAT_EN_ADDRESS 0x180600c0
3079 #define RST_CLKGAT_EN_OFFSET 0x00c0
3080 // SW modifiable bits
3081 #define RST_CLKGAT_EN_SW_MASK 0xfffff2e2
3082 // bits defined at reset
3083 #define RST_CLKGAT_EN_RSTMASK 0xffffffff
3084 // reset value (ignore bits undefined at reset)
3085 #define RST_CLKGAT_EN_RESET 0x000002e2
3087 #define GPIO_OE_ADDRESS 0x18040000
3088 #define GPIO_IN_ADDRESS 0x18040004/* by huangwenzhong, 03Sep13 */
3089 #define GPIO_OUT_ADDRESS 0x18040008
3090 #define GPIO_SPARE_ADDRESS 0x18040070
3093 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB 31
3094 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB 24
3095 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK 0xff000000
3096 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB)
3097 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK)
3098 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET 0x0 // 0
3099 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB 23
3100 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB 16
3101 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK 0x00ff0000
3102 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB)
3103 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK)
3104 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET 0x0 // 0
3105 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB 15
3106 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB 8
3107 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK 0x0000ff00
3108 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB)
3109 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK)
3110 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET 0x0 // 0
3111 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB 7
3112 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB 0
3113 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK 0x000000ff
3114 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB)
3115 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK)
3116 #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET 0x0 // 0
3117 #define GPIO_OUT_FUNCTION0_ADDRESS 0x1804002c
3119 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31
3120 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24
3121 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000
3122 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
3123 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
3124 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xc // 12
3125 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23
3126 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16
3127 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000
3128 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
3129 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
3130 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0x8 // 8
3131 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15
3132 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8
3133 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00
3134 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
3135 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
3136 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9
3137 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7
3138 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0
3139 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff
3140 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
3141 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
3142 #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x5d // 93
3143 #define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030
3145 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31
3146 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24
3147 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000
3148 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)
3149 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)
3150 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0
3151 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23
3152 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16
3153 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000
3154 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)
3155 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)
3156 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0
3157 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15
3158 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8
3159 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00
3160 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)
3161 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)
3162 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0
3163 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7
3164 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0
3165 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff
3166 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)
3167 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)
3168 #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0
3169 #define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034
3171 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31
3172 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24
3173 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000
3174 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB)
3175 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK)
3176 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0
3177 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23
3178 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16
3179 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000
3180 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB)
3181 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK)
3182 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0
3183 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15
3184 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8
3185 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00
3186 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB)
3187 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK)
3188 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0
3189 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7
3190 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0
3191 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff
3192 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB)
3193 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK)
3194 #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0
3195 #define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038
3197 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15
3198 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
3199 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
3200 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)
3201 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
3202 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x1 // 1
3203 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7
3204 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0
3205 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff
3206 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)
3207 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)
3208 #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0
3209 #define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c
3211 #define GPIO_IN_ENABLE0_UART_SIN_MSB 15
3212 #define GPIO_IN_ENABLE0_UART_SIN_LSB 8
3213 #define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00
3214 #define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)
3215 #define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)
3216 #define GPIO_IN_ENABLE0_UART_SIN_RESET 0x80 // 128
3217 #define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7
3218 #define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0
3219 #define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff
3220 #define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB)
3221 #define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK)
3222 #define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8
3223 #define GPIO_IN_ENABLE0_ADDRESS 0x18040044
3225 #define GPIO_IN_ENABLE1_RES_MSB 31
3226 #define GPIO_IN_ENABLE1_RES_LSB 0
3227 #define GPIO_IN_ENABLE1_RES_MASK 0xffffffff
3228 #define GPIO_IN_ENABLE1_RES_GET(x) (((x) & GPIO_IN_ENABLE1_RES_MASK) >> GPIO_IN_ENABLE1_RES_LSB)
3229 #define GPIO_IN_ENABLE1_RES_SET(x) (((x) << GPIO_IN_ENABLE1_RES_LSB) & GPIO_IN_ENABLE1_RES_MASK)
3230 #define GPIO_IN_ENABLE1_RES_RESET 0x0 // 0
3231 #define GPIO_IN_ENABLE1_ADDRESS 0x18040048
3233 #define GPIO_IN_ENABLE2_RES_MSB 31
3234 #define GPIO_IN_ENABLE2_RES_LSB 0
3235 #define GPIO_IN_ENABLE2_RES_MASK 0xffffffff
3236 #define GPIO_IN_ENABLE2_RES_GET(x) (((x) & GPIO_IN_ENABLE2_RES_MASK) >> GPIO_IN_ENABLE2_RES_LSB)
3237 #define GPIO_IN_ENABLE2_RES_SET(x) (((x) << GPIO_IN_ENABLE2_RES_LSB) & GPIO_IN_ENABLE2_RES_MASK)
3238 #define GPIO_IN_ENABLE2_RES_RESET 0x0 // 0
3239 #define GPIO_IN_ENABLE2_ADDRESS 0x1804004c
3241 #define GPIO_IN_ENABLE3_RES_MSB 31
3242 #define GPIO_IN_ENABLE3_RES_LSB 0
3243 #define GPIO_IN_ENABLE3_RES_MASK 0xffffffff
3244 #define GPIO_IN_ENABLE3_RES_GET(x) (((x) & GPIO_IN_ENABLE3_RES_MASK) >> GPIO_IN_ENABLE3_RES_LSB)
3245 #define GPIO_IN_ENABLE3_RES_SET(x) (((x) << GPIO_IN_ENABLE3_RES_LSB) & GPIO_IN_ENABLE3_RES_MASK)
3246 #define GPIO_IN_ENABLE3_RES_RESET 0x0 // 0
3247 #define GPIO_IN_ENABLE3_ADDRESS 0x18040050
3249 #define GPIO_IN_ENABLE4_RES_MSB 31
3250 #define GPIO_IN_ENABLE4_RES_LSB 0
3251 #define GPIO_IN_ENABLE4_RES_MASK 0xffffffff
3252 #define GPIO_IN_ENABLE4_RES_GET(x) (((x) & GPIO_IN_ENABLE4_RES_MASK) >> GPIO_IN_ENABLE4_RES_LSB)
3253 #define GPIO_IN_ENABLE4_RES_SET(x) (((x) << GPIO_IN_ENABLE4_RES_LSB) & GPIO_IN_ENABLE4_RES_MASK)
3254 #define GPIO_IN_ENABLE4_RES_RESET 0x0 // 0
3255 #define GPIO_IN_ENABLE4_ADDRESS 0x18040054
3257 #define GPIO_IN_ENABLE5_WMAC_IN3_MSB 31
3258 #define GPIO_IN_ENABLE5_WMAC_IN3_LSB 24
3259 #define GPIO_IN_ENABLE5_WMAC_IN3_MASK 0xff000000
3260 #define GPIO_IN_ENABLE5_WMAC_IN3_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) >> GPIO_IN_ENABLE5_WMAC_IN3_LSB)
3261 #define GPIO_IN_ENABLE5_WMAC_IN3_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN3_LSB) & GPIO_IN_ENABLE5_WMAC_IN3_MASK)
3262 #define GPIO_IN_ENABLE5_WMAC_IN3_RESET 0x80 // 128
3263 #define GPIO_IN_ENABLE5_WMAC_IN2_MSB 23
3264 #define GPIO_IN_ENABLE5_WMAC_IN2_LSB 16
3265 #define GPIO_IN_ENABLE5_WMAC_IN2_MASK 0x00ff0000
3266 #define GPIO_IN_ENABLE5_WMAC_IN2_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) >> GPIO_IN_ENABLE5_WMAC_IN2_LSB)
3267 #define GPIO_IN_ENABLE5_WMAC_IN2_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN2_LSB) & GPIO_IN_ENABLE5_WMAC_IN2_MASK)
3268 #define GPIO_IN_ENABLE5_WMAC_IN2_RESET 0x80 // 128
3269 #define GPIO_IN_ENABLE5_WMAC_IN1_MSB 15
3270 #define GPIO_IN_ENABLE5_WMAC_IN1_LSB 8
3271 #define GPIO_IN_ENABLE5_WMAC_IN1_MASK 0x0000ff00
3272 #define GPIO_IN_ENABLE5_WMAC_IN1_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) >> GPIO_IN_ENABLE5_WMAC_IN1_LSB)
3273 #define GPIO_IN_ENABLE5_WMAC_IN1_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN1_LSB) & GPIO_IN_ENABLE5_WMAC_IN1_MASK)
3274 #define GPIO_IN_ENABLE5_WMAC_IN1_RESET 0x80 // 128
3275 #define GPIO_IN_ENABLE5_WMAC_IN0_MSB 7
3276 #define GPIO_IN_ENABLE5_WMAC_IN0_LSB 0
3277 #define GPIO_IN_ENABLE5_WMAC_IN0_MASK 0x000000ff
3278 #define GPIO_IN_ENABLE5_WMAC_IN0_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) >> GPIO_IN_ENABLE5_WMAC_IN0_LSB)
3279 #define GPIO_IN_ENABLE5_WMAC_IN0_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN0_LSB) & GPIO_IN_ENABLE5_WMAC_IN0_MASK)
3280 #define GPIO_IN_ENABLE5_WMAC_IN0_RESET 0x80 // 128
3281 #define GPIO_IN_ENABLE5_ADDRESS 0x18040058
3283 #define GPIO_IN_ENABLE6_WMAC_IN7_MSB 31
3284 #define GPIO_IN_ENABLE6_WMAC_IN7_LSB 24
3285 #define GPIO_IN_ENABLE6_WMAC_IN7_MASK 0xff000000
3286 #define GPIO_IN_ENABLE6_WMAC_IN7_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) >> GPIO_IN_ENABLE6_WMAC_IN7_LSB)
3287 #define GPIO_IN_ENABLE6_WMAC_IN7_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN7_LSB) & GPIO_IN_ENABLE6_WMAC_IN7_MASK)
3288 #define GPIO_IN_ENABLE6_WMAC_IN7_RESET 0x80 // 128
3289 #define GPIO_IN_ENABLE6_WMAC_IN6_MSB 23
3290 #define GPIO_IN_ENABLE6_WMAC_IN6_LSB 16
3291 #define GPIO_IN_ENABLE6_WMAC_IN6_MASK 0x00ff0000
3292 #define GPIO_IN_ENABLE6_WMAC_IN6_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) >> GPIO_IN_ENABLE6_WMAC_IN6_LSB)
3293 #define GPIO_IN_ENABLE6_WMAC_IN6_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN6_LSB) & GPIO_IN_ENABLE6_WMAC_IN6_MASK)
3294 #define GPIO_IN_ENABLE6_WMAC_IN6_RESET 0x80 // 128
3295 #define GPIO_IN_ENABLE6_WMAC_IN5_MSB 15
3296 #define GPIO_IN_ENABLE6_WMAC_IN5_LSB 8
3297 #define GPIO_IN_ENABLE6_WMAC_IN5_MASK 0x0000ff00
3298 #define GPIO_IN_ENABLE6_WMAC_IN5_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) >> GPIO_IN_ENABLE6_WMAC_IN5_LSB)
3299 #define GPIO_IN_ENABLE6_WMAC_IN5_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN5_LSB) & GPIO_IN_ENABLE6_WMAC_IN5_MASK)
3300 #define GPIO_IN_ENABLE6_WMAC_IN5_RESET 0x80 // 128
3301 #define GPIO_IN_ENABLE6_WMAC_IN4_MSB 7
3302 #define GPIO_IN_ENABLE6_WMAC_IN4_LSB 0
3303 #define GPIO_IN_ENABLE6_WMAC_IN4_MASK 0x000000ff
3304 #define GPIO_IN_ENABLE6_WMAC_IN4_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) >> GPIO_IN_ENABLE6_WMAC_IN4_LSB)
3305 #define GPIO_IN_ENABLE6_WMAC_IN4_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN4_LSB) & GPIO_IN_ENABLE6_WMAC_IN4_MASK)
3306 #define GPIO_IN_ENABLE6_WMAC_IN4_RESET 0x80 // 128
3307 #define GPIO_IN_ENABLE6_ADDRESS 0x1804005c
3309 #define GPIO_IN_ENABLE7_WMAC_IN11_MSB 31
3310 #define GPIO_IN_ENABLE7_WMAC_IN11_LSB 24
3311 #define GPIO_IN_ENABLE7_WMAC_IN11_MASK 0xff000000
3312 #define GPIO_IN_ENABLE7_WMAC_IN11_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) >> GPIO_IN_ENABLE7_WMAC_IN11_LSB)
3313 #define GPIO_IN_ENABLE7_WMAC_IN11_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN11_LSB) & GPIO_IN_ENABLE7_WMAC_IN11_MASK)
3314 #define GPIO_IN_ENABLE7_WMAC_IN11_RESET 0x80 // 128
3315 #define GPIO_IN_ENABLE7_WMAC_IN10_MSB 23
3316 #define GPIO_IN_ENABLE7_WMAC_IN10_LSB 16
3317 #define GPIO_IN_ENABLE7_WMAC_IN10_MASK 0x00ff0000
3318 #define GPIO_IN_ENABLE7_WMAC_IN10_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) >> GPIO_IN_ENABLE7_WMAC_IN10_LSB)
3319 #define GPIO_IN_ENABLE7_WMAC_IN10_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN10_LSB) & GPIO_IN_ENABLE7_WMAC_IN10_MASK)
3320 #define GPIO_IN_ENABLE7_WMAC_IN10_RESET 0x80 // 128
3321 #define GPIO_IN_ENABLE7_WMAC_IN9_MSB 15
3322 #define GPIO_IN_ENABLE7_WMAC_IN9_LSB 8
3323 #define GPIO_IN_ENABLE7_WMAC_IN9_MASK 0x0000ff00
3324 #define GPIO_IN_ENABLE7_WMAC_IN9_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) >> GPIO_IN_ENABLE7_WMAC_IN9_LSB)
3325 #define GPIO_IN_ENABLE7_WMAC_IN9_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN9_LSB) & GPIO_IN_ENABLE7_WMAC_IN9_MASK)
3326 #define GPIO_IN_ENABLE7_WMAC_IN9_RESET 0x80 // 128
3327 #define GPIO_IN_ENABLE7_WMAC_IN8_MSB 7
3328 #define GPIO_IN_ENABLE7_WMAC_IN8_LSB 0
3329 #define GPIO_IN_ENABLE7_WMAC_IN8_MASK 0x000000ff
3330 #define GPIO_IN_ENABLE7_WMAC_IN8_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) >> GPIO_IN_ENABLE7_WMAC_IN8_LSB)
3331 #define GPIO_IN_ENABLE7_WMAC_IN8_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN8_LSB) & GPIO_IN_ENABLE7_WMAC_IN8_MASK)
3332 #define GPIO_IN_ENABLE7_WMAC_IN8_RESET 0x80 // 128
3333 #define GPIO_IN_ENABLE7_ADDRESS 0x18040060
3335 #define GPIO_IN_ENABLE8_SRIF_SRESET_MSB 31
3336 #define GPIO_IN_ENABLE8_SRIF_SRESET_LSB 24
3337 #define GPIO_IN_ENABLE8_SRIF_SRESET_MASK 0xff000000
3338 #define GPIO_IN_ENABLE8_SRIF_SRESET_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) >> GPIO_IN_ENABLE8_SRIF_SRESET_LSB)
3339 #define GPIO_IN_ENABLE8_SRIF_SRESET_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SRESET_LSB) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK)
3340 #define GPIO_IN_ENABLE8_SRIF_SRESET_RESET 0x80 // 128
3341 #define GPIO_IN_ENABLE8_SRIF_SIN_MSB 23
3342 #define GPIO_IN_ENABLE8_SRIF_SIN_LSB 16
3343 #define GPIO_IN_ENABLE8_SRIF_SIN_MASK 0x00ff0000
3344 #define GPIO_IN_ENABLE8_SRIF_SIN_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) >> GPIO_IN_ENABLE8_SRIF_SIN_LSB)
3345 #define GPIO_IN_ENABLE8_SRIF_SIN_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SIN_LSB) & GPIO_IN_ENABLE8_SRIF_SIN_MASK)
3346 #define GPIO_IN_ENABLE8_SRIF_SIN_RESET 0x80 // 128
3347 #define GPIO_IN_ENABLE8_SRIF_SOT_MSB 15
3348 #define GPIO_IN_ENABLE8_SRIF_SOT_LSB 8
3349 #define GPIO_IN_ENABLE8_SRIF_SOT_MASK 0x0000ff00
3350 #define GPIO_IN_ENABLE8_SRIF_SOT_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) >> GPIO_IN_ENABLE8_SRIF_SOT_LSB)
3351 #define GPIO_IN_ENABLE8_SRIF_SOT_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SOT_LSB) & GPIO_IN_ENABLE8_SRIF_SOT_MASK)
3352 #define GPIO_IN_ENABLE8_SRIF_SOT_RESET 0x80 // 128
3353 #define GPIO_IN_ENABLE8_SRIF_SCLK_MSB 7
3354 #define GPIO_IN_ENABLE8_SRIF_SCLK_LSB 0
3355 #define GPIO_IN_ENABLE8_SRIF_SCLK_MASK 0x000000ff
3356 #define GPIO_IN_ENABLE8_SRIF_SCLK_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) >> GPIO_IN_ENABLE8_SRIF_SCLK_LSB)
3357 #define GPIO_IN_ENABLE8_SRIF_SCLK_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SCLK_LSB) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK)
3358 #define GPIO_IN_ENABLE8_SRIF_SCLK_RESET 0x80 // 128
3359 #define GPIO_IN_ENABLE8_ADDRESS 0x18040064
3361 #define GPIO_IN_ENABLE9_RES_MSB 31
3362 #define GPIO_IN_ENABLE9_RES_LSB 0
3363 #define GPIO_IN_ENABLE9_RES_MASK 0xffffffff
3364 #define GPIO_IN_ENABLE9_RES_GET(x) (((x) & GPIO_IN_ENABLE9_RES_MASK) >> GPIO_IN_ENABLE9_RES_LSB)
3365 #define GPIO_IN_ENABLE9_RES_SET(x) (((x) << GPIO_IN_ENABLE9_RES_LSB) & GPIO_IN_ENABLE9_RES_MASK)
3366 #define GPIO_IN_ENABLE9_RES_RESET 0x0 // 0
3367 #define GPIO_IN_ENABLE9_ADDRESS 0x18040068
3369 #define GPIO_FUNCTION_EXT_MDIO_SEL_MSB 11
3370 #define GPIO_FUNCTION_EXT_MDIO_SEL_LSB 11
3371 #define GPIO_FUNCTION_EXT_MDIO_SEL_MASK 0x00000800
3372 #define GPIO_FUNCTION_EXT_MDIO_SEL_GET(x) (((x) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) >> GPIO_FUNCTION_EXT_MDIO_SEL_LSB)
3373 #define GPIO_FUNCTION_EXT_MDIO_SEL_SET(x) (((x) << GPIO_FUNCTION_EXT_MDIO_SEL_LSB) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK)
3374 #define GPIO_FUNCTION_EXT_MDIO_SEL_RESET 0x0 // 0
3375 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8
3376 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8
3377 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100
3378 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB)
3379 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK)
3380 #define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0
3381 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7
3382 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7
3383 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080
3384 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB)
3385 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK)
3386 #define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x0 // 0
3387 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6
3388 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6
3389 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040
3390 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB)
3391 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK)
3392 #define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0
3393 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5
3394 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5
3395 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020
3396 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB)
3397 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK)
3398 #define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x1 // 1
3399 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4
3400 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4
3401 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010
3402 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB)
3403 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK)
3404 #define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0
3405 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3
3406 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3
3407 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008
3408 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB)
3409 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK)
3410 #define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0
3411 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2
3412 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2
3413 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004
3414 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB)
3415 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK)
3416 #define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0
3417 #define GPIO_FUNCTION_DISABLE_JTAG_MSB 1
3418 #define GPIO_FUNCTION_DISABLE_JTAG_LSB 1
3419 #define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002
3420 #define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB)
3421 #define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK)
3422 #define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0
3423 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0
3424 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0
3425 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001
3426 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB)
3427 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK)
3428 #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0
3429 #define GPIO_FUNCTION_ADDRESS 0x1804006c
3431 #define PCIE_RESET_EP_RESET_L_MSB 2
3432 #define PCIE_RESET_EP_RESET_L_LSB 2
3433 #define PCIE_RESET_EP_RESET_L_MASK 0x00000004
3434 #define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB)
3435 #define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK)
3436 #define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0
3437 #define PCIE_RESET_LINK_REQ_RESET_MSB 1
3438 #define PCIE_RESET_LINK_REQ_RESET_LSB 1
3439 #define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002
3440 #define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB)
3441 #define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK)
3442 #define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0
3443 #define PCIE_RESET_LINK_UP_MSB 0
3444 #define PCIE_RESET_LINK_UP_LSB 0
3445 #define PCIE_RESET_LINK_UP_MASK 0x00000001
3446 #define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB)
3447 #define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK)
3448 #define PCIE_RESET_LINK_UP_RESET 0x0 // 0
3449 #define PCIE_RESET_ADDRESS 0x180f0018
3451 #define ETH_CFG_ETH_SPARE_MSB 31
3452 #define ETH_CFG_ETH_SPARE_LSB 22
3453 #define ETH_CFG_ETH_SPARE_MASK 0xffc00000
3454 #define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)
3455 #define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)
3456 #define ETH_CFG_ETH_SPARE_RESET 0x0 // 0
3457 #define ETH_CFG_SW_ACC_MSB_FIRST_MSB 13
3458 #define ETH_CFG_SW_ACC_MSB_FIRST_LSB 13
3459 #define ETH_CFG_SW_ACC_MSB_FIRST_MASK 0x00002000
3460 #define ETH_CFG_SW_ACC_MSB_FIRST_GET(x) (((x) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) >> ETH_CFG_SW_ACC_MSB_FIRST_LSB)
3461 #define ETH_CFG_SW_ACC_MSB_FIRST_SET(x) (((x) << ETH_CFG_SW_ACC_MSB_FIRST_LSB) & ETH_CFG_SW_ACC_MSB_FIRST_MASK)
3462 #define ETH_CFG_SW_ACC_MSB_FIRST_RESET 0x1 // 1
3463 #define ETH_CFG_SW_APB_ACCESS_MSB 9
3464 #define ETH_CFG_SW_APB_ACCESS_LSB 9
3465 #define ETH_CFG_SW_APB_ACCESS_MASK 0x00000200
3466 #define ETH_CFG_SW_APB_ACCESS_GET(x) (((x) & ETH_CFG_SW_APB_ACCESS_MASK) >> ETH_CFG_SW_APB_ACCESS_LSB)
3467 #define ETH_CFG_SW_APB_ACCESS_SET(x) (((x) << ETH_CFG_SW_APB_ACCESS_LSB) & ETH_CFG_SW_APB_ACCESS_MASK)
3468 #define ETH_CFG_SW_APB_ACCESS_RESET 0x0 // 0
3469 #define ETH_CFG_SW_PHY_ADDR_SWAP_MSB 8
3470 #define ETH_CFG_SW_PHY_ADDR_SWAP_LSB 8
3471 #define ETH_CFG_SW_PHY_ADDR_SWAP_MASK 0x00000100
3472 #define ETH_CFG_SW_PHY_ADDR_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) >> ETH_CFG_SW_PHY_ADDR_SWAP_LSB)
3473 #define ETH_CFG_SW_PHY_ADDR_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_ADDR_SWAP_LSB) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK)
3474 #define ETH_CFG_SW_PHY_ADDR_SWAP_RESET 0x0 // 0
3475 #define ETH_CFG_SW_PHY_SWAP_MSB 7
3476 #define ETH_CFG_SW_PHY_SWAP_LSB 7
3477 #define ETH_CFG_SW_PHY_SWAP_MASK 0x00000080
3478 #define ETH_CFG_SW_PHY_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_SWAP_MASK) >> ETH_CFG_SW_PHY_SWAP_LSB)
3479 #define ETH_CFG_SW_PHY_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_SWAP_LSB) & ETH_CFG_SW_PHY_SWAP_MASK)
3480 #define ETH_CFG_SW_PHY_SWAP_RESET 0x0 // 0
3481 #define ETH_CFG_SW_ONLY_MODE_MSB 6
3482 #define ETH_CFG_SW_ONLY_MODE_LSB 6
3483 #define ETH_CFG_SW_ONLY_MODE_MASK 0x00000040
3484 #define ETH_CFG_SW_ONLY_MODE_GET(x) (((x) & ETH_CFG_SW_ONLY_MODE_MASK) >> ETH_CFG_SW_ONLY_MODE_LSB)
3485 #define ETH_CFG_SW_ONLY_MODE_SET(x) (((x) << ETH_CFG_SW_ONLY_MODE_LSB) & ETH_CFG_SW_ONLY_MODE_MASK)
3486 #define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0
3487 #define ETH_CFG_ADDRESS 0x18070000
3492 #define ATH_PCI_MEM_BASE 0x10000000 /* 128M */
3493 #define ATH_APB_BASE 0x18000000 /* 384M */
3494 #define ATH_GE0_BASE 0x19000000 /* 16M */
3495 #define ATH_GE1_BASE 0x1a000000 /* 16M */
3496 #define ATH_USB_OHCI_BASE 0x1b000000
3497 #define ATH_USB_EHCI_BASE 0x1b000000
3498 #define ATH_USB_EHCI_BASE_1 0x1b000000
3499 #define ATH_USB_EHCI_BASE_2 0x1b400000
3500 #define ATH_SPI_BASE 0x1f000000
3503 * Added the PCI LCL RESET register from u-boot
3504 * ath_soc.h so that we can query the PCI LCL RESET
3505 * register for the presence of WLAN H/W.
3507 #define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x000f0000)
3508 #define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00)
3509 #define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18)
3514 #define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000
3515 #define ATH_CPU_BASE ATH_APB_BASE+0x00010000
3516 #define ATH_UART_BASE ATH_APB_BASE+0x00020000
3517 #define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000
3518 #define ATH_GPIO_BASE ATH_APB_BASE+0x00040000
3519 #define ATH_PLL_BASE ATH_APB_BASE+0x00050000
3520 #define ATH_RESET_BASE ATH_APB_BASE+0x00060000
3521 #define ATH_DMA_BASE ATH_APB_BASE+0x000A0000
3522 #define ATH_SLIC_BASE ATH_APB_BASE+0x000A9000
3523 #define ATH_STEREO_BASE ATH_APB_BASE+0x000B0000
3524 #define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x000F0000
3525 #define ATH_OTP_BASE ATH_APB_BASE+0x00130000
3526 //#define ATH_NAND_FLASH_BASE 0x1b800000u
3532 #define ATH_DDR_CONFIG_16BIT (1 << 31)
3533 #define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30)
3534 #define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27
3535 #define ATH_DDR_CONFIG_TMRD_SHIFT 23
3536 #define ATH_DDR_CONFIG_TRFC_SHIFT 17
3537 #define ATH_DDR_CONFIG_TRRD_SHIFT 13
3538 #define ATH_DDR_CONFIG_TRP_SHIFT 9
3539 #define ATH_DDR_CONFIG_TRCD_SHIFT 5
3540 #define ATH_DDR_CONFIG_TRAS_SHIFT 0
3542 #define ATH_DDR_CONFIG2_BL2 (2 << 0)
3543 #define ATH_DDR_CONFIG2_BL4 (4 << 0)
3544 #define ATH_DDR_CONFIG2_BL8 (8 << 0)
3546 #define ATH_DDR_CONFIG2_BT_IL (1 << 4)
3547 #define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5)
3548 #define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6)
3549 #define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7)
3550 #define ATH_DDR_CONFIG2_TWR_SHIFT 8
3551 #define ATH_DDR_CONFIG2_TRTW_SHIFT 12
3552 #define ATH_DDR_CONFIG2_TRTP_SHIFT 17
3553 #define ATH_DDR_CONFIG2_TWTR_SHIFT 21
3554 #define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31)
3556 #define ATH_DDR_TAP_DEFAULT 0x18
3559 * DDR block, gmac flushing
3561 #define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c
3562 #define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0
3563 #define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4
3564 #define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0x88
3566 #define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000
3567 #define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006
3573 #define ATH_PLL_CONFIG ATH_PLL_BASE+0x0
3574 #define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x8
3577 #define PLL_DIV_SHIFT 0
3578 #define PLL_DIV_MASK 0x3ff
3579 #define REF_DIV_SHIFT 10
3580 #define REF_DIV_MASK 0xf
3581 #define AHB_DIV_SHIFT 19
3582 #define AHB_DIV_MASK 0x1
3583 #define DDR_DIV_SHIFT 22
3584 #define DDR_DIV_MASK 0x1
3585 #define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x4
3586 #define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x2c
3587 #define ATH_AUDIO_PLL_CONFIG ATH_PLL_BASE+0x30
3589 #define ATH_ETH_INT0_CLK ATH_PLL_BASE+0x14
3590 #define ATH_ETH_INT1_CLK ATH_PLL_BASE+0x18
3596 #define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE
3597 #define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4
3598 #define ATH_USB_WINDOW 0x10000
3599 #define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8
3604 #define ATH_PCI_WINDOW 0x8000000 /* 128MB */
3605 #define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c
3606 #define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80
3607 #define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84
3608 #define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88
3609 #define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c
3610 #define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90
3611 #define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94
3612 #define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98
3614 #define ATH_PCI_WINDOW0_VAL 0x10000000
3615 #define ATH_PCI_WINDOW1_VAL 0x11000000
3616 #define ATH_PCI_WINDOW2_VAL 0x12000000
3617 #define ATH_PCI_WINDOW3_VAL 0x13000000
3618 #define ATH_PCI_WINDOW4_VAL 0x14000000
3619 #define ATH_PCI_WINDOW5_VAL 0x15000000
3620 #define ATH_PCI_WINDOW6_VAL 0x16000000
3621 #define ATH_PCI_WINDOW7_VAL 0x07000000
3623 #define ath_write_pci_window(_no) \
3624 ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL);
3627 * CRP. To access the host controller config and status registers
3629 #define ATH_PCI_CRP 0x180c0000
3630 #define ATH_PCI_DEV_CFGBASE 0x14000000
3631 #define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP
3632 #define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4
3633 #define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8
3634 #define ATH_PCI_ERROR ATH_PCI_CRP+0x1c
3635 #define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20
3636 #define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24
3637 #define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28
3639 #define ATH_CRP_CMD_WRITE 0x00010000
3640 #define ATH_CRP_CMD_READ 0x00000000
3643 * PCI CFG. To generate config cycles
3645 #define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc
3646 #define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10
3647 #define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14
3648 #define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18
3649 #define ATH_CFG_CMD_READ 0x0000000a
3650 #define ATH_CFG_CMD_WRITE 0x0000000b
3652 #define ATH_PCI_IDSEL_ADLINE_START 17
3654 #define ATH_SPI_FS (ATH_SPI_BASE+0x00)
3655 #define ATH_SPI_READ (ATH_SPI_BASE+0x00)
3656 #define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04)
3657 #define ATH_SPI_WRITE (ATH_SPI_BASE+0x08)
3658 #define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c)
3659 #define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10)
3660 #define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14)
3661 #define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18)
3662 #define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */
3663 #define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */
3665 #define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */
3666 #define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */
3667 #define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */
3668 #define ATH_SPI_CS_DIS 0x70000
3669 #define ATH_SPI_CE_LOW 0x60000
3670 #define ATH_SPI_CE_HIGH 0x60100
3672 #define ATH_SPI_SECTOR_SIZE (1024*64)
3673 #define ATH_SPI_PAGE_SIZE 256
3675 #define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1)
3676 #define ATH_RESET_GE0_PHY RST_RESET_ETH_SWITCH_RESET_SET(1)
3677 #define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1)
3678 #define ATH_RESET_GE1_PHY RST_RESET_ETH_SWITCH_ARESET_SET(1)
3679 #define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1)
3680 #define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1)
3685 #define ATH_SPI_CMD_WRITE_SR 0x01
3686 #define ATH_SPI_CMD_WREN 0x06
3687 #define ATH_SPI_CMD_RD_STATUS 0x05
3688 #define ATH_SPI_CMD_FAST_READ 0x0b
3689 #define ATH_SPI_CMD_PAGE_PROG 0x02
3690 #define ATH_SPI_CMD_SECTOR_ERASE 0xd8
3691 #define ATH_SPI_CMD_CHIP_ERASE 0xc7
3692 #define ATH_SPI_CMD_RDID 0x9f
3694 #define CPU_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(0)
3695 #define CPU_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
3697 #define DDR_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
3698 #define DDR_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(0)
3700 #if CPU_DDR_SYNC_MODE
3702 # define both_from_cpu 0
3703 # define both_from_ddr 1
3706 # define CLK_SRC_CONTROL (CPU_CLK_FROM_DDR_PLL | DDR_CLK_FROM_DDR_PLL)
3707 # define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
3708 # elif both_from_cpu
3709 # define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_CPU_PLL)
3710 # define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
3712 # error "Invalid sync mode settings"
3715 # define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_DDR_PLL)
3721 // 32'h18070034 (SGMII_CONFIG)
3722 #define SGMII_CONFIG_BERT_ENABLE_MSB 14
3723 #define SGMII_CONFIG_BERT_ENABLE_LSB 14
3724 #define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000
3725 #define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB)
3726 #define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK)
3727 #define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0
3728 #define SGMII_CONFIG_PRBS_ENABLE_MSB 13
3729 #define SGMII_CONFIG_PRBS_ENABLE_LSB 13
3730 #define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000
3731 #define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB)
3732 #define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK)
3733 #define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0
3734 #define SGMII_CONFIG_MDIO_COMPLETE_MSB 12
3735 #define SGMII_CONFIG_MDIO_COMPLETE_LSB 12
3736 #define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000
3737 #define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB)
3738 #define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK)
3739 #define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0
3740 #define SGMII_CONFIG_MDIO_PULSE_MSB 11
3741 #define SGMII_CONFIG_MDIO_PULSE_LSB 11
3742 #define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800
3743 #define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB)
3744 #define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK)
3745 #define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0
3746 #define SGMII_CONFIG_MDIO_ENABLE_MSB 10
3747 #define SGMII_CONFIG_MDIO_ENABLE_LSB 10
3748 #define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400
3749 #define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB)
3750 #define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK)
3751 #define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0
3752 #define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9
3753 #define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9
3754 #define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200
3755 #define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB)
3756 #define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK)
3757 #define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0
3758 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8
3759 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8
3760 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100
3761 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB)
3762 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK)
3763 #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0
3764 #define SGMII_CONFIG_SPEED_MSB 7
3765 #define SGMII_CONFIG_SPEED_LSB 6
3766 #define SGMII_CONFIG_SPEED_MASK 0x000000c0
3767 #define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB)
3768 #define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK)
3769 #define SGMII_CONFIG_SPEED_RESET 0x0 // 0
3770 #define SGMII_CONFIG_FORCE_SPEED_MSB 5
3771 #define SGMII_CONFIG_FORCE_SPEED_LSB 5
3772 #define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020
3773 #define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB)
3774 #define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK)
3775 #define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0
3776 #define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4
3777 #define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4
3778 #define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010
3779 #define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB)
3780 #define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK)
3781 #define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0
3782 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3
3783 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3
3784 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008
3785 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB)
3786 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK)
3787 #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0
3788 #define SGMII_CONFIG_MODE_CTRL_MSB 2
3789 #define SGMII_CONFIG_MODE_CTRL_LSB 0
3790 #define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007
3791 #define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB)
3792 #define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK)
3793 #define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0
3794 #define SGMII_CONFIG_ADDRESS 0x18070034
3798 // 32'h1807001c (MR_AN_CONTROL)
3799 #define MR_AN_CONTROL_PHY_RESET_MSB 15
3800 #define MR_AN_CONTROL_PHY_RESET_LSB 15
3801 #define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000
3802 #define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB)
3803 #define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK)
3804 #define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0
3805 #define MR_AN_CONTROL_LOOPBACK_MSB 14
3806 #define MR_AN_CONTROL_LOOPBACK_LSB 14
3807 #define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000
3808 #define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB)
3809 #define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK)
3810 #define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0
3811 #define MR_AN_CONTROL_SPEED_SEL0_MSB 13
3812 #define MR_AN_CONTROL_SPEED_SEL0_LSB 13
3813 #define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000
3814 #define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB)
3815 #define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK)
3816 #define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0
3817 #define MR_AN_CONTROL_AN_ENABLE_MSB 12
3818 #define MR_AN_CONTROL_AN_ENABLE_LSB 12
3819 #define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000
3820 #define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB)
3821 #define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK)
3822 #define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1
3823 #define MR_AN_CONTROL_POWER_DOWN_MSB 11
3824 #define MR_AN_CONTROL_POWER_DOWN_LSB 11
3825 #define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800
3826 #define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB)
3827 #define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK)
3828 #define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0
3829 #define MR_AN_CONTROL_RESTART_AN_MSB 9
3830 #define MR_AN_CONTROL_RESTART_AN_LSB 9
3831 #define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200
3832 #define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB)
3833 #define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK)
3834 #define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0
3835 #define MR_AN_CONTROL_DUPLEX_MODE_MSB 8
3836 #define MR_AN_CONTROL_DUPLEX_MODE_LSB 8
3837 #define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100
3838 #define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB)
3839 #define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK)
3840 #define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1
3841 #define MR_AN_CONTROL_SPEED_SEL1_MSB 6
3842 #define MR_AN_CONTROL_SPEED_SEL1_LSB 6
3843 #define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040
3844 #define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB)
3845 #define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK)
3846 #define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1
3847 #define MR_AN_CONTROL_ADDRESS 0x1807001c
3853 // 32'h18070014 (SGMII_RESET)
3854 #define SGMII_RESET_HW_RX_125M_N_MSB 4
3855 #define SGMII_RESET_HW_RX_125M_N_LSB 4
3856 #define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010
3857 #define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB)
3858 #define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK)
3859 #define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0
3860 #define SGMII_RESET_TX_125M_N_MSB 3
3861 #define SGMII_RESET_TX_125M_N_LSB 3
3862 #define SGMII_RESET_TX_125M_N_MASK 0x00000008
3863 #define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB)
3864 #define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK)
3865 #define SGMII_RESET_TX_125M_N_RESET 0x0 // 0
3866 #define SGMII_RESET_RX_125M_N_MSB 2
3867 #define SGMII_RESET_RX_125M_N_LSB 2
3868 #define SGMII_RESET_RX_125M_N_MASK 0x00000004
3869 #define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB)
3870 #define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK)
3871 #define SGMII_RESET_RX_125M_N_RESET 0x0 // 0
3872 #define SGMII_RESET_TX_CLK_N_MSB 1
3873 #define SGMII_RESET_TX_CLK_N_LSB 1
3874 #define SGMII_RESET_TX_CLK_N_MASK 0x00000002
3875 #define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB)
3876 #define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK)
3877 #define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0
3878 #define SGMII_RESET_RX_CLK_N_MSB 0
3879 #define SGMII_RESET_RX_CLK_N_LSB 0
3880 #define SGMII_RESET_RX_CLK_N_MASK 0x00000001
3881 #define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB)
3882 #define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK)
3883 #define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0
3884 #define SGMII_RESET_ADDRESS 0x18070014
3888 // 32'h18070038 (SGMII_MAC_RX_CONFIG)
3889 #define SGMII_MAC_RX_CONFIG_LINK_MSB 15
3890 #define SGMII_MAC_RX_CONFIG_LINK_LSB 15
3891 #define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000
3892 #define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB)
3893 #define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK)
3894 #define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0
3895 #define SGMII_MAC_RX_CONFIG_ACK_MSB 14
3896 #define SGMII_MAC_RX_CONFIG_ACK_LSB 14
3897 #define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000
3898 #define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB)
3899 #define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK)
3900 #define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0
3901 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12
3902 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12
3903 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000
3904 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB)
3905 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK)
3906 #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0
3907 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11
3908 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10
3909 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00
3910 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB)
3911 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK)
3912 #define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0
3913 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8
3914 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8
3915 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100
3916 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB)
3917 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK)
3918 #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0
3919 #define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7
3920 #define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7
3921 #define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080
3922 #define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB)
3923 #define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK)
3924 #define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0
3925 #define SGMII_MAC_RX_CONFIG_RES0_MSB 0
3926 #define SGMII_MAC_RX_CONFIG_RES0_LSB 0
3927 #define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001
3928 #define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB)
3929 #define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK)
3930 #define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1
3931 #define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038
3933 // 32'h18070058 (SGMII_DEBUG)
3934 #define SGMII_DEBUG_ARB_STATE_MSB 27
3935 #define SGMII_DEBUG_ARB_STATE_LSB 24
3936 #define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000
3937 #define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB)
3938 #define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK)
3939 #define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0
3940 #define SGMII_DEBUG_RX_SYNC_STATE_MSB 23
3941 #define SGMII_DEBUG_RX_SYNC_STATE_LSB 16
3942 #define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000
3943 #define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB)
3944 #define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK)
3945 #define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0
3946 #define SGMII_DEBUG_RX_STATE_MSB 15
3947 #define SGMII_DEBUG_RX_STATE_LSB 8
3948 #define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00
3949 #define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB)
3950 #define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK)
3951 #define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0
3952 #define SGMII_DEBUG_TX_STATE_MSB 7
3953 #define SGMII_DEBUG_TX_STATE_LSB 0
3954 #define SGMII_DEBUG_TX_STATE_MASK 0x000000ff
3955 #define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB)
3956 #define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK)
3957 #define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0
3958 #define SGMII_DEBUG_ADDRESS 0x18070058
3959 #define SGMII_DEBUG_OFFSET 0x0058
3963 // 32'h18070060 (SGMII_INTERRUPT_MASK)
3964 #define SGMII_INTERRUPT_MASK_MASK_MSB 7
3965 #define SGMII_INTERRUPT_MASK_MASK_LSB 0
3966 #define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff
3967 #define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)
3968 #define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)
3969 #define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0
3970 #define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060
3975 // 32'h1807005c (SGMII_INTERRUPT)
3976 #define SGMII_INTERRUPT_INTR_MSB 7
3977 #define SGMII_INTERRUPT_INTR_LSB 0
3978 #define SGMII_INTERRUPT_INTR_MASK 0x000000ff
3979 #define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB)
3980 #define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK)
3981 #define SGMII_INTERRUPT_INTR_RESET 0x0 // 0
3982 #define SGMII_INTERRUPT_ADDRESS 0x1807005c
3983 #define SGMII_INTERRUPT_OFFSET 0x005c
3984 // SW modifiable bits
3985 #define SGMII_INTERRUPT_SW_MASK 0x000000ff
3986 // bits defined at reset
3987 #define SGMII_INTERRUPT_RSTMASK 0xffffffff
3988 // reset value (ignore bits undefined at reset)
3989 #define SGMII_INTERRUPT_RESET 0x00000000
3991 // 32'h18070060 (SGMII_INTERRUPT_MASK)
3992 #define SGMII_INTERRUPT_MASK_MASK_MSB 7
3993 #define SGMII_INTERRUPT_MASK_MASK_LSB 0
3994 #define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff
3995 #define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)
3996 #define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)
3997 #define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0
3998 #define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060
4001 #define SGMII_LINK_FAIL (1 << 0)
4002 #define SGMII_DUPLEX_ERR (1 << 1)
4003 #define SGMII_MR_AN_COMPLETE (1 << 2)
4004 #define SGMII_LINK_MAC_CHANGE (1 << 3)
4005 #define SGMII_DUPLEX_MODE_CHANGE (1 << 4)
4006 #define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5)
4007 #define SGMII_RX_QUIET_CHANGE (1 << 6)
4008 #define SGMII_RX_MDIO_COMP_CHANGE (1 << 7)
4010 #define SGMII_INTR SGMII_LINK_FAIL | \
4011 SGMII_LINK_MAC_CHANGE | \
4012 SGMII_DUPLEX_MODE_CHANGE | \
4013 SGMII_SPEED_MODE_MAC_CHANGE
4016 // 32'h18050048 (ETH_SGMII)
4017 #define ETH_SGMII_TX_INVERT_MSB 31
4018 #define ETH_SGMII_TX_INVERT_LSB 31
4019 #define ETH_SGMII_TX_INVERT_MASK 0x80000000
4020 #define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB)
4021 #define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK)
4022 #define ETH_SGMII_TX_INVERT_RESET 0x0 // 0
4023 #define ETH_SGMII_GIGE_QUAD_MSB 30
4024 #define ETH_SGMII_GIGE_QUAD_LSB 30
4025 #define ETH_SGMII_GIGE_QUAD_MASK 0x40000000
4026 #define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB)
4027 #define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK)
4028 #define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0
4029 #define ETH_SGMII_RX_DELAY_MSB 29
4030 #define ETH_SGMII_RX_DELAY_LSB 28
4031 #define ETH_SGMII_RX_DELAY_MASK 0x30000000
4032 #define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB)
4033 #define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK)
4034 #define ETH_SGMII_RX_DELAY_RESET 0x0 // 0
4035 #define ETH_SGMII_TX_DELAY_MSB 27
4036 #define ETH_SGMII_TX_DELAY_LSB 26
4037 #define ETH_SGMII_TX_DELAY_MASK 0x0c000000
4038 #define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB)
4039 #define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK)
4040 #define ETH_SGMII_TX_DELAY_RESET 0x0 // 0
4041 #define ETH_SGMII_CLK_SEL_MSB 25
4042 #define ETH_SGMII_CLK_SEL_LSB 25
4043 #define ETH_SGMII_CLK_SEL_MASK 0x02000000
4044 #define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB)
4045 #define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK)
4046 #define ETH_SGMII_CLK_SEL_RESET 0x1 // 1
4047 #define ETH_SGMII_GIGE_MSB 24
4048 #define ETH_SGMII_GIGE_LSB 24
4049 #define ETH_SGMII_GIGE_MASK 0x01000000
4050 #define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB)
4051 #define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK)
4052 #define ETH_SGMII_GIGE_RESET 0x1 // 1
4053 #define ETH_SGMII_PHASE1_COUNT_MSB 15
4054 #define ETH_SGMII_PHASE1_COUNT_LSB 8
4055 #define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00
4056 #define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB)
4057 #define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK)
4058 #define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1
4059 #define ETH_SGMII_PHASE0_COUNT_MSB 7
4060 #define ETH_SGMII_PHASE0_COUNT_LSB 0
4061 #define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff
4062 #define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB)
4063 #define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK)
4064 #define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1
4065 #define ETH_SGMII_ADDRESS 0x18050048
4067 #endif /* _QCA953X_H */
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