2 * Qualcomm/Atheros WiSoCs DRAM related common functions
4 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2013 Qualcomm Atheros, Inc.
6 * Copyright (C) 2008-2010 Atheros Communications Inc.
8 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/addrspace.h>
14 #include <soc/qca_soc_common.h>
15 #include <soc/qca_dram.h>
17 #define QCA_DDR_SIZE_INCREMENT (8 * 1024 * 1024)
20 * Returns size (in bytes) of the DRAM memory
22 * DDR wraps around, write a pattern to 0x00000000
23 * at 8M, 16M, 32M etc. and check when it gets overwritten
25 u32 qca_dram_size(void)
33 #define max_i (QCA_DRAM_MAX_SIZE_VAL / QCA_DDR_SIZE_INCREMENT)
35 for (i = 1; (i < max_i); i++) {
36 *(p + i * QCA_DDR_SIZE_INCREMENT) = (u8)i;
43 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
45 (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL);
49 * something is wrong with relocation,
50 * need to fix it for boards with > 32M of RAM
52 * For now just return 1 MB smaller size
55 (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL) - 1024 * 1024;
60 * Return memory type value from BOOT_STRAP register
62 u32 qca_dram_type(void)
64 #if defined(CONFIG_BOARD_DRAM_TYPE_SDR)
65 return RAM_MEMORY_TYPE_SDR;
66 #elif defined(CONFIG_BOARD_DRAM_TYPE_DDR1)
67 return RAM_MEMORY_TYPE_DDR1;
68 #elif defined(CONFIG_BOARD_DRAM_TYPE_DDR2)
69 return RAM_MEMORY_TYPE_DDR2;
73 dram_type = ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG)
74 & QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
77 case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
78 dram_type = RAM_MEMORY_TYPE_SDR;
80 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
81 dram_type = RAM_MEMORY_TYPE_DDR1;
83 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
84 dram_type = RAM_MEMORY_TYPE_DDR2;
87 dram_type = RAM_MEMORY_TYPE_UNKNOWN;