u-boot/cpu/mips/ar7240/qca_dram.c

   1 /*
   2  * Qualcomm/Atheros WiSoCs DRAM related common functions
   3  *
   4  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   5  * Copyright (C) 2013 Qualcomm Atheros, Inc.
   6  * Copyright (C) 2008-2010 Atheros Communications Inc.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <asm/addrspace.h>
  14 #include <soc/qca_soc_common.h>
  15 #include <soc/qca_dram.h>
  16
  17 #define QCA_DDR_SIZE_INCREMENT  (8 * 1024 * 1024)
  18
  19 /*
  20  * Returns size (in bytes) of the DRAM memory
  21  *
  22  * DDR wraps around, write a pattern to 0x00000000
  23  * at 8M, 16M, 32M etc. and check when it gets overwritten
  24  */
  25 u32 qca_dram_size(void)
  26 {
  27         u8 *p = (u8 *)KSEG1;
  28         u8 pattern = 0x77;
  29         u32 i;
  30
  31         *p = pattern;
  32
  33         #define max_i   (QCA_DRAM_MAX_SIZE_VAL / QCA_DDR_SIZE_INCREMENT)
  34
  35         for (i = 1; (i < max_i); i++) {
  36                 *(p + i * QCA_DDR_SIZE_INCREMENT) = (u8)i;
  37
  38                 if (*p != pattern) {
  39                         break;
  40                 }
  41         }
  42
  43 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  44         return ((i < max_i) ?
  45                         (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL);
  46 #else
  47         /*
  48          * TODO:
  49          * something is wrong with relocation,
  50          * need to fix it for boards with > 32M of RAM
  51          *
  52          * For now just return 1 MB smaller size
  53          */
  54         return ((i < max_i) ?
  55                         (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL) - 1024 * 1024;
  56 #endif
  57 }
  58
  59 /*
  60  * Return memory type value from BOOT_STRAP register
  61  */
  62 u32 qca_dram_type(void)
  63 {
  64 #if defined(CONFIG_BOARD_DRAM_TYPE_SDR)
  65         return RAM_MEMORY_TYPE_SDR;
  66 #elif defined(CONFIG_BOARD_DRAM_TYPE_DDR1)
  67         return RAM_MEMORY_TYPE_DDR1;
  68 #elif defined(CONFIG_BOARD_DRAM_TYPE_DDR2)
  69         return RAM_MEMORY_TYPE_DDR2;
  70 #else
  71         u32 dram_type;
  72
  73         dram_type = ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG)
  74                                  & QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
  75
  76         switch (dram_type) {
  77         case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
  78                 dram_type = RAM_MEMORY_TYPE_SDR;
  79                 break;
  80         case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
  81                 dram_type = RAM_MEMORY_TYPE_DDR1;
  82                 break;
  83         case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
  84                 dram_type = RAM_MEMORY_TYPE_DDR2;
  85                 break;
  86         default:
  87                 dram_type = RAM_MEMORY_TYPE_UNKNOWN;
  88                 break;
  89         }
  90
  91         return dram_type;
  92 #endif
  93 }