u-boot/cpu/mips/ar7240/qca_common.c

   1 /*
   2  * Qualcomm/Atheros common/helper functions
   3  *
   4  * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
   5  *
   6  * Partially based on:
   7  * Linux/arch/mips/ath79/setup.c
   8  *
   9  * SPDX-License-Identifier:GPL-2.0
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <asm/addrspace.h>
  15 #include <soc/qca_soc_common.h>
  16
  17 /*
  18  * Returns 1 if reference clock is 40 MHz
  19  */
  20 inline u32 qca_xtal_is_40mhz(void)
  21 {
  22         return ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
  23                         QCA_RST_BOOTSTRAP_REF_CLK_MASK) >> QCA_RST_BOOTSTRAP_REF_CLK_SHIFT);
  24 }
  25
  26 /*
  27  * Return memory type value from BOOT_STRAP register
  28  */
  29 u32 qca_dram_type(void)
  30 {
  31 #if defined(CONFIG_BOARD_CONST_DRAM_TYPE_SDR)
  32         return RAM_MEMORY_TYPE_SDR;
  33 #elif defined(CONFIG_BOARD_CONST_DRAM_TYPE_DDR1)
  34         return RAM_MEMORY_TYPE_DDR1;
  35 #elif defined(CONFIG_BOARD_CONST_DRAM_TYPE_DDR2)
  36         return RAM_MEMORY_TYPE_DDR2;
  37 #else
  38         static u32 dram_type = 0;
  39
  40         if (dram_type == 0) {
  41                 dram_type = ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
  42                                          QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
  43
  44                 switch (dram_type) {
  45                 case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
  46                         dram_type = RAM_MEMORY_TYPE_SDR;
  47                         break;
  48                 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
  49                         dram_type = RAM_MEMORY_TYPE_DDR1;
  50                         break;
  51                 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
  52                         dram_type = RAM_MEMORY_TYPE_DDR2;
  53                         break;
  54                 default:
  55                         dram_type = RAM_MEMORY_TYPE_UNKNOWN;
  56                         break;
  57                 }
  58         }
  59
  60         return dram_type;
  61 #endif
  62 }
  63
  64 /*
  65  * Put QCA SOC name, version and revision in buffer
  66  */
  67 void qca_soc_name_rev(char *buf)
  68 {
  69         u32 id;
  70         u32 major;
  71         u32 rev = 0;
  72
  73         if (buf == NULL)
  74                 return;
  75
  76         /* Get revision ID value */
  77         id = qca_soc_reg_read(QCA_RST_REVISION_ID_REG);
  78
  79         major = id & QCA_RST_REVISION_ID_MAJOR_MASK;
  80         rev = id & QCA_RST_REVISION_ID_REV_MASK;
  81
  82         switch (major) {
  83 #if (SOC_TYPE & QCA_AR933X_SOC)
  84         case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL:
  85                 sprintf(buf, "AR9330 rev. %d", rev);
  86                 break;
  87         case QCA_RST_REVISION_ID_MAJOR_AR9331_VAL:
  88                 sprintf(buf, "AR9331 rev. %d", rev);
  89                 break;
  90 #endif
  91 #if (SOC_TYPE & QCA_AR934X_SOC)
  92         case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
  93                 sprintf(buf, "AR9341 rev. %d", rev);
  94                 break;
  95         case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
  96                 sprintf(buf, "AR9344 rev. %d", rev);
  97                 break;
  98 #endif
  99 #if (SOC_TYPE & QCA_QCA953X_SOC)
 100         case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL:
 101                 sprintf(buf, "QCA953x ver. 1 rev. %d", rev);
 102                 break;
 103         case QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL:
 104                 sprintf(buf, "QCA953x ver. 2 rev. %d", rev);
 105                 break;
 106 #endif
 107 #if (SOC_TYPE & QCA_QCA955X_SOC)
 108         case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL:
 109                 sprintf(buf, "QCA9558 rev. %d", rev);
 110                 break;
 111 #endif
 112         default:
 113                 sprintf(buf, "Unknown");
 114                 break;
 115         }
 116 }
 117
 118 /*
 119  * Performs full chip reset
 120  */
 121 void qca_full_chip_reset(void)
 122 {
 123         volatile u32 i = 1;
 124
 125         do {
 126                 qca_soc_reg_write(QCA_RST_RST_REG,
 127                                                   QCA_RST_RESET_FULL_CHIP_RST_MASK
 128                                                   | QCA_RST_RESET_DDR_RST_MASK);
 129         } while (i);
 130 }