u-boot/common/cmd_custom.c

   1 /*
   2  * (C) Copyright 2013
   3  * Piotr Dymacz (pepe2k), Real Time Systems, piotr@realtimesystems.pl, pepe2k@gmail.com
   4  * Custom commands for U-Boot 1.1.4 modification.
   5  *
   6  * See file CREDITS for list of people who contributed to U-Boot project.
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <common.h>
  23 #include <command.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/addrspace.h>
  26 #include <ar7240_soc.h>
  27 #include "../board/ar7240/common/ar7240_flash.h"
  28
  29 extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
  30
  31 #if defined(OFFSET_MAC_ADDRESS)
  32 /*
  33  * Show MAC address(es)
  34  */
  35 int do_print_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
  36         char buffer[6];
  37 #if defined(OFFSET_MAC_ADDRESS2)
  38         char buffer2[6];
  39 #endif
  40
  41 #if defined(OFFSET_MAC_ADDRESS2)
  42         // get MAC1 and MAC2 addresses from flash and print them
  43         memcpy(buffer,  (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS),  6);
  44         memcpy(buffer2, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS2), 6);
  45
  46         puts("Current MAC addresses stored in flash:\n");
  47         printf("MAC1 at 0x%X: %02X:%02X:%02X:%02X:%02X:%02X\n", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS,
  48                                                                                                                         buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF);
  49
  50         printf("MAC2 at 0x%X: %02X:%02X:%02X:%02X:%02X:%02X\n\n", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS2,
  51                                                                                                                           buffer2[0] & 0xFF, buffer2[1] & 0xFF, buffer2[2] & 0xFF, buffer2[3] & 0xFF, buffer2[4] & 0xFF, buffer2[5] & 0xFF);
  52 #else
  53         // get MAC address from flash and print it
  54         memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
  55
  56         printf("Current MAC address stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS);
  57         printf("%02X:%02X:%02X:%02X:%02X:%02X\n\n", buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF);
  58 #endif
  59
  60         return(0);
  61 }
  62
  63 #if defined(OFFSET_MAC_ADDRESS2)
  64 U_BOOT_CMD(printmac, 1, 1, do_print_mac, "print MAC addresses stored in flash\n", NULL);
  65 #else
  66 U_BOOT_CMD(printmac, 1, 1, do_print_mac, "print MAC address stored in flash\n", NULL);
  67 #endif
  68
  69 /*
  70  * Change MAC address(es)
  71  */
  72 int do_set_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
  73         unsigned char *data_pointer;
  74         char buf[128];
  75         int i = 0, j = 0;
  76
  77         // allow only 2 arg (command name + mac), second argument length should be 17 (xx:xx:xx:xx:xx:xx)
  78         if(argc != 2 || strlen(argv[1]) != 17){
  79 #if defined(CFG_LONGHELP)
  80                 if(cmdtp->help != NULL){
  81                         printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help);
  82                 } else {
  83                         printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage);
  84                 }
  85 #else
  86                 printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage);
  87 #endif
  88                 return(1);
  89         }
  90
  91         // count ':'
  92         for(i = 0; i< 17; i++){
  93                 if(argv[1][i] == ':'){
  94                         j++;
  95                 }
  96         }
  97
  98         if(j != 5){
  99                 puts("## Error: given MAC address has wrong format (should be: xx:xx:xx:xx:xx:xx)!\n");
 100                 return(1);
 101         }
 102
 103         // backup block with MAC address from flash in RAM
 104         data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
 105
 106         if(!data_pointer){
 107                 puts("## Error: couldn't allocate RAM for data block backup!\n");
 108                 return(1);
 109         }
 110
 111         puts("** Notice:\n   you should always make a backup of your device\n           entire FLASH content before making any changes\n\n");
 112
 113         memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK), OFFSET_MAC_DATA_BLOCK_LENGTH);
 114
 115         // store new MAC address in RAM
 116         for(i = 0; i < 6; i++){
 117                 data_pointer[OFFSET_MAC_ADDRESS + i] = simple_strtoul((char *)(argv[1] + i*3), NULL, 16);
 118         }
 119
 120         // now we can erase flash and write data from RAM
 121         sprintf(buf,
 122                         "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
 123                         CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK,
 124                         OFFSET_MAC_DATA_BLOCK_LENGTH,
 125                         WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
 126                         CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK,
 127                         OFFSET_MAC_DATA_BLOCK_LENGTH);
 128
 129         printf("Executing: %s\n\n", buf);
 130
 131         return(run_command(buf, 0));
 132 }
 133
 134 U_BOOT_CMD(setmac, 2, 0, do_set_mac, "save new MAC address in flash\n", "xx:xx:xx:xx:xx:xx\n\t- change MAC address stored in flash (xx - value in hex format)\n");
 135
 136 #endif /* if defined(OFFSET_MAC_ADDRESS) */
 137
 138 #if defined(OFFSET_ROUTER_MODEL)
 139 /*
 140  * Show TP-Link router model
 141  */
 142 int do_print_model(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 143         unsigned char buffer[8];
 144
 145         // get router model from flash and print it
 146         memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_ROUTER_MODEL), 8);
 147
 148         printf("Router model stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_ROUTER_MODEL);
 149         printf("%02X%02X%02X%02X%02X%02X%02X%02X\n\n", buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF, buffer[6] & 0xFF, buffer[7] & 0xFF);
 150
 151         return(0);
 152 }
 153
 154 U_BOOT_CMD(printmodel, 1, 1, do_print_model, "print router model stored in flash\n", NULL);
 155
 156 #endif /* if defined(OFFSET_ROUTER_MODEL) */
 157
 158 #if defined(OFFSET_PIN_NUMBER)
 159 /*
 160  * Show pin number
 161  */
 162 int do_print_pin(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 163         unsigned char buffer[9];
 164
 165         // get pin number from flash and print it
 166         memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_PIN_NUMBER), 8);
 167         buffer[8] = 0;
 168
 169         printf("Router pin number stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_PIN_NUMBER);
 170         printf("%s\n\n", buffer);
 171
 172         return(0);
 173 }
 174
 175 U_BOOT_CMD(printpin, 1, 1, do_print_pin, "print WPS pin stored in flash\n", NULL);
 176
 177 #endif /* if defined(OFFSET_PIN_NUMBER) */
 178
 179 #if defined(CONFIG_NETCONSOLE)
 180 /*
 181  * Start NetConsole
 182  */
 183 int do_start_nc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 184         return(run_command("setenv stdin nc;setenv stdout nc;setenv stderr nc;version;", 0));
 185 }
 186
 187 U_BOOT_CMD(startnc, 1, 0, do_start_nc, "start net console\n", NULL);
 188
 189 /*
 190  * Start Serial Console
 191  */
 192 int do_start_sc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 193         return(run_command("setenv stdin serial;setenv stdout serial;setenv stderr serial;version;", 0));
 194 }
 195
 196 U_BOOT_CMD(startsc, 1, 0, do_start_sc, "start serial console\n", NULL);
 197
 198 #endif /* if defined(CONFIG_NETCONSOLE) */
 199
 200 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
 201     defined(CONFIG_FOR_DRAGINO_V2)
 202 /*
 203  * Erase environment sector
 204  */
 205 int do_erase_env(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 206         char buf[64];
 207
 208         sprintf(buf,
 209                         "erase 0x%lX +0x%lX",
 210                         CFG_ENV_ADDR,
 211                         CFG_ENV_SIZE);
 212
 213         printf("Executing: %s\n\n", buf);
 214
 215         return(run_command(buf, 0));
 216 }
 217
 218 U_BOOT_CMD(eraseenv, 1, 1, do_erase_env, "erase environment sector in flash\n", NULL);
 219 #endif /* if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || defined(CONFIG_FOR_DRAGINO_V2) */
 220
 221 #if defined(PLL_IN_FLASH_MAGIC_OFFSET)
 222
 223 typedef struct {
 224         // Clocks in MHz
 225         unsigned short cpu_clock;
 226         unsigned short ram_clock;
 227         unsigned short ahb_clock;
 228         unsigned short spi_clock;
 229
 230         // Registers values
 231         // (more info in includes/configs/ap121.h)
 232         unsigned int cpu_clk_control;
 233         unsigned int cpu_pll_config;
 234         unsigned int spi_control;
 235 } ar9331_clock_profile;
 236
 237 static const ar9331_clock_profile oc_profiles[] = {
 238         {
 239          200, 200, 100, 25,
 240          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 241 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 242          MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2),
 243 #else
 244          MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2),
 245 #endif
 246          MAKE_AR9331_SPI_CONTROL_VAL(4)
 247         },
 248
 249         {
 250          200, 200, 200, 33,
 251          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
 252 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 253          MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2),
 254 #else
 255          MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2),
 256 #endif
 257          MAKE_AR9331_SPI_CONTROL_VAL(6)
 258         },
 259
 260 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 261         {
 262          225, 225, 112, 28,
 263          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 264          MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2),
 265          MAKE_AR9331_SPI_CONTROL_VAL(4)
 266         },
 267
 268         {
 269          225, 225, 225, 28,
 270          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
 271          MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2),
 272          MAKE_AR9331_SPI_CONTROL_VAL(8)
 273         },
 274 #endif
 275
 276         {
 277          250, 250, 125, 31,
 278          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 279 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 280          MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2),
 281 #else
 282          MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1),
 283 #endif
 284          MAKE_AR9331_SPI_CONTROL_VAL(4)
 285         },
 286
 287         {
 288          250, 250, 250, 31,
 289          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
 290 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 291          MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2),
 292 #else
 293          MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1),
 294 #endif
 295          MAKE_AR9331_SPI_CONTROL_VAL(8)
 296         },
 297
 298         {
 299          300, 300, 150, 25,
 300          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 301 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 302          MAKE_AR9331_CPU_PLL_CONFIG_VAL(15, 1, 0, 1),
 303 #else
 304          MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1),
 305 #endif
 306          MAKE_AR9331_SPI_CONTROL_VAL(6)
 307         },
 308
 309 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 310         {
 311          325, 325, 162, 27,
 312          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 313          MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1),
 314          MAKE_AR9331_SPI_CONTROL_VAL(6)
 315         },
 316
 317         {
 318          350, 350, 175, 29,
 319          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 320          MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1),
 321          MAKE_AR9331_SPI_CONTROL_VAL(6)
 322         },
 323 #endif
 324
 325         {
 326          360, 360, 180, 30,
 327          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 328 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 329          MAKE_AR9331_CPU_PLL_CONFIG_VAL(18, 1, 0, 1),
 330 #else
 331          MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1),
 332 #endif
 333          MAKE_AR9331_SPI_CONTROL_VAL(6)
 334         },
 335
 336 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 337         {
 338          380, 380, 190, 32,
 339          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 340          MAKE_AR9331_CPU_PLL_CONFIG_VAL(19, 1, 0, 1),
 341          MAKE_AR9331_SPI_CONTROL_VAL(6)
 342         },
 343 #endif
 344
 345         {
 346          400, 400, 200, 33,
 347          CPU_CLK_CONTROL_VAL_DEFAULT,
 348          CPU_PLL_CONFIG_VAL_DEFAULT,
 349          AR7240_SPI_CONTROL_DEFAULT
 350         },
 351
 352 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 353         {
 354          412, 412, 206, 34,
 355          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 356          MAKE_AR9331_CPU_PLL_CONFIG_VAL(33, 1, 0, 1),
 357          MAKE_AR9331_SPI_CONTROL_VAL(6)
 358         },
 359 #endif
 360
 361 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 362         {
 363          420, 420, 210, 35,
 364          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 365          MAKE_AR9331_CPU_PLL_CONFIG_VAL(21, 1, 0, 1),
 366          MAKE_AR9331_SPI_CONTROL_VAL(6)
 367         },
 368 #endif
 369
 370 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 371         {
 372          425, 425, 212, 35,
 373          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 374          MAKE_AR9331_CPU_PLL_CONFIG_VAL(34, 1, 0, 1),
 375          MAKE_AR9331_SPI_CONTROL_VAL(6)
 376         },
 377
 378         {
 379          437, 437, 218, 27,
 380          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 381          MAKE_AR9331_CPU_PLL_CONFIG_VAL(35, 1, 0, 1),
 382          MAKE_AR9331_SPI_CONTROL_VAL(8)
 383         },
 384 #endif
 385
 386 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 387         {
 388          440, 440, 220, 27,
 389          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 390          MAKE_AR9331_CPU_PLL_CONFIG_VAL(22, 1, 0, 1),
 391          MAKE_AR9331_SPI_CONTROL_VAL(8)
 392         },
 393 #endif
 394
 395 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 396         {
 397          450, 450, 225, 28,
 398          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 399          MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 1),
 400          MAKE_AR9331_SPI_CONTROL_VAL(8)
 401         },
 402 #endif
 403
 404         {
 405          460, 460, 230, 29,
 406          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 407 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 408          MAKE_AR9331_CPU_PLL_CONFIG_VAL(23, 1, 0, 1),
 409 #else
 410          MAKE_AR9331_CPU_PLL_CONFIG_VAL(37, 1, 0, 1),
 411 #endif
 412          MAKE_AR9331_SPI_CONTROL_VAL(8)
 413         },
 414
 415 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 416         {
 417          475, 475, 237, 30,
 418          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 419          MAKE_AR9331_CPU_PLL_CONFIG_VAL(38, 1, 0, 1),
 420          MAKE_AR9331_SPI_CONTROL_VAL(8)
 421         },
 422 #endif
 423
 424 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 425         {
 426          480, 480, 240, 30,
 427          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 428          MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1),
 429          MAKE_AR9331_SPI_CONTROL_VAL(8)
 430         },
 431 #endif
 432
 433 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 434         {
 435          487, 487, 243, 30,
 436          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 437          MAKE_AR9331_CPU_PLL_CONFIG_VAL(39, 1, 0, 1),
 438          MAKE_AR9331_SPI_CONTROL_VAL(8)
 439         },
 440 #endif
 441
 442         {
 443          500, 500, 250, 31,
 444          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 445 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 446          MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1),
 447 #else
 448          MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1),
 449 #endif
 450          MAKE_AR9331_SPI_CONTROL_VAL(8)
 451         },
 452
 453         {
 454          500, 250, 250, 31,
 455          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 2),
 456 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 457          MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1),
 458 #else
 459          MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1),
 460 #endif
 461          MAKE_AR9331_SPI_CONTROL_VAL(8)
 462         },
 463
 464 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 465         {
 466          520, 520, 260, 32,
 467          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
 468          MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1),
 469          MAKE_AR9331_SPI_CONTROL_VAL(8)
 470         },
 471 #endif
 472
 473 #if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
 474         {
 475          525, 262, 131, 33,
 476          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
 477          MAKE_AR9331_CPU_PLL_CONFIG_VAL(42, 1, 0, 1),
 478          MAKE_AR9331_SPI_CONTROL_VAL(4)
 479         },
 480 #endif
 481
 482         {
 483          560, 280, 140, 35,
 484          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
 485 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 486          MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1),
 487 #else
 488          MAKE_AR9331_CPU_PLL_CONFIG_VAL(45, 1, 0, 1),
 489 #endif
 490          MAKE_AR9331_SPI_CONTROL_VAL(4)
 491         },
 492
 493 #if defined(CONFIG_40MHZ_XTAL_SUPPORT)
 494         {
 495          580, 290, 145, 36,
 496          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
 497          MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1),
 498          MAKE_AR9331_SPI_CONTROL_VAL(4)
 499         },
 500 #endif
 501
 502         {
 503          600, 300, 200, 33,
 504          MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 3),
 505 #if CONFIG_40MHZ_XTAL_SUPPORT
 506          MAKE_AR9331_CPU_PLL_CONFIG_VAL(30, 1, 0, 1),
 507 #else
 508          MAKE_AR9331_CPU_PLL_CONFIG_VAL(48, 1, 0, 1),
 509 #endif
 510          MAKE_AR9331_SPI_CONTROL_VAL(6)
 511         },
 512 };
 513
 514 /*
 515  * Set and store PLL configuration in FLASH
 516  */
 517 int do_set_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 518         unsigned int cpu_pll_config_flash, cpu_clock_control_flash, spi_control_flash, reg;
 519         unsigned int ahb_freq, ddr_freq, cpu_freq, spi_freq;
 520         unsigned int *data_pointer;
 521         int i, index, profiles_count;
 522         char buf[128];
 523
 524         profiles_count = sizeof(oc_profiles) / sizeof(ar9331_clock_profile);
 525
 526         // print all available profiles and current settings
 527         if(argc == 1){
 528
 529                 // read clocks
 530                 ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
 531
 532                 // calculate SPI clock (we need to set bit 0 to 1 in SPI_FUNC_SELECT to access SPI registers)
 533                 ar7240_reg_wr(AR7240_SPI_FS, 0x01);
 534                 spi_freq = ahb_freq / (((ar7240_reg_rd(AR7240_SPI_CLOCK) & 0x3F) + 1) * 2);
 535                 ar7240_reg_wr(AR7240_SPI_FS, 0x0);
 536
 537                 // make MHz from Hz
 538                 cpu_freq /= 1000000;
 539                 ddr_freq /= 1000000;
 540                 ahb_freq /= 1000000;
 541                 spi_freq /= 1000000;
 542
 543                 printf("Current clocks (approximated):\n- CPU: %3d MHz\n", cpu_freq);
 544                 printf("- RAM: %3d MHz\n", ddr_freq);
 545                 printf("- AHB: %3d MHz\n", ahb_freq);
 546                 printf("- SPI: %3d MHz\n", spi_freq);
 547
 548                 // reference clock
 549                 if(ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_SEL_25M_40M_MASK){
 550                         puts("- REF:  40 MHz\n\n");
 551                 } else {
 552                         puts("- REF:  25 MHz\n\n");
 553                 }
 554
 555                 // do we have PLL_MAGIC in FLASH?
 556                 reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
 557
 558                 // read all register values stored in FLASH
 559                 cpu_pll_config_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 4);
 560                 cpu_clock_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 8);
 561                 spi_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 12);
 562
 563                 printf("Available PLL and clocks configurations: %d\n\n", profiles_count);
 564
 565                 puts("      | CPU | RAM | AHB | SPI | [ ]\n  ---------------------------------\n");
 566
 567                 for(i = 0; i <  profiles_count; i++){
 568                         printf("%4d. |%4d |%4d |%4d |%4d | ", i + 1,
 569                                                                                                   oc_profiles[i].cpu_clock,
 570                                                                                                   oc_profiles[i].ram_clock,
 571                                                                                                   oc_profiles[i].ahb_clock,
 572                                                                                                   oc_profiles[i].spi_clock);
 573
 574                         if(reg == PLL_IN_FLASH_MAGIC &&
 575                            oc_profiles[i].cpu_pll_config == cpu_pll_config_flash &&
 576                            oc_profiles[i].cpu_clk_control == cpu_clock_control_flash &&
 577                            oc_profiles[i].spi_control == spi_control_flash){
 578                                 puts("[*]\n");
 579                         } else {
 580                                 puts("[ ]\n");
 581                         }
 582                 }
 583
 584                 puts("\n[*] = currently selected profile (stored in FLASH).\nAll clocks in MHz, run 'setclocks X' to choose one.\n\n");
 585                 puts("** Notice:\n   you should always make a backup of your device\n   entire FLASH content before making any changes\n\n");
 586
 587                 return(0);
 588         } else {
 589                 // selected index
 590                 index = simple_strtoul(argv[1], NULL, 10);
 591
 592                 if(index > profiles_count || index < 1){
 593                         printf("## Error: selected index should be in range 1..%d!\n", profiles_count);
 594                         return(1);
 595                 }
 596
 597                 printf("You have selected profile: %d.\n\n", index);
 598
 599                 // array is zero-based indexing
 600                 index--;
 601
 602                 // backup entire block in which we store PLL/CLK settings
 603                 data_pointer = (unsigned int *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
 604
 605                 if(!data_pointer){
 606                         puts("## Error: couldn't allocate RAM for data block backup!\n");
 607                         return(1);
 608                 }
 609
 610                 memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
 611
 612                 // save PLL_IN_FLASH_MAGIC and PLL/clocks registers values
 613                 data_pointer = (unsigned int *)(WEBFAILSAFE_UPLOAD_RAM_ADDRESS + PLL_IN_FLASH_MAGIC_OFFSET);
 614                 *data_pointer = PLL_IN_FLASH_MAGIC;
 615
 616                 data_pointer++;
 617                 *data_pointer = oc_profiles[index].cpu_pll_config;
 618
 619                 data_pointer++;
 620                 *data_pointer = oc_profiles[index].cpu_clk_control;
 621
 622                 data_pointer++;
 623                 *data_pointer = oc_profiles[index].spi_control;
 624
 625                 // erase FLASH, copy data from RAM
 626                 sprintf(buf,
 627                                 "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
 628                                 CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
 629                                 PLL_IN_FLASH_DATA_BLOCK_LENGTH,
 630                                 WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
 631                                 CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
 632                                 PLL_IN_FLASH_DATA_BLOCK_LENGTH);
 633
 634                 printf("Executing: %s\n\n", buf);
 635
 636                 return(run_command(buf, 0));
 637         }
 638 }
 639
 640 U_BOOT_CMD(setclocks, 2, 0, do_set_clocks, "select clocks configuration from predefined list\n",
 641                 "index\n"
 642                 "\t- save 'index' configuration in FLASH\n"
 643                 "setclocks\n"
 644                 "\t- prints available clocks configurations and current settings");
 645
 646 /*
 647  * Remove (clear) PLL and clock settings in FLASH
 648  */
 649 int do_clear_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
 650         unsigned char *data_pointer;
 651         int i;
 652         char buf[128];
 653         unsigned int reg = 0;
 654
 655         // do we have PLL_MAGIC in FLASH?
 656         reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
 657
 658         if(reg == PLL_IN_FLASH_MAGIC){
 659                 // backup entire block in which we store PLL/CLK settings
 660                 data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
 661
 662                 if(!data_pointer){
 663                         puts("## Error: couldn't allocate RAM for data block backup!\n");
 664                         return(1);
 665                 }
 666
 667                 memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
 668
 669                 // 16 bytes (4x 32-bit values)
 670                 for(i = 0; i < 16; i++){
 671                         data_pointer[PLL_IN_FLASH_MAGIC_OFFSET + i] = 0xFF;
 672                 }
 673
 674                 // erase FLASH, copy data from RAM
 675                 sprintf(buf,
 676                                 "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
 677                                 CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
 678                                 PLL_IN_FLASH_DATA_BLOCK_LENGTH,
 679                                 WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
 680                                 CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
 681                                 PLL_IN_FLASH_DATA_BLOCK_LENGTH);
 682
 683                 printf("Executing: %s\n\n", buf);
 684
 685                 return(run_command(buf, 0));
 686         } else {
 687                 puts("** Warning: there is no PLL and clocks configuration in FLASH!\n");
 688                 return(1);
 689         }
 690 }
 691
 692 U_BOOT_CMD(clearclocks, 1, 0, do_clear_clocks, "remove PLL and clocks configuration from FLASH\n", NULL);
 693 #endif /* #if defined(PLL_IN_FLASH_MAGIC_OFFSET) */