u-boot/board/ar7240/common/tap-953x.S

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <config.h>
  24 #include <version.h>
  25 #include <asm/regdef.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/addrspace.h>
  28 #include <atheros.h>
  29
  30 .globl ath_ddr_tap_cal
  31         .type   ath_ddr_tap_cal,        @function
  32         .text
  33         .align 4
  34 ath_ddr_tap_cal:
  35         li      a0,     0xbd001f00
  36         sw      zero,   0x0(a0)                 // Place where the tap values are saved and used for SWEEP
  37         sw      zero,   0x4(a0)                 // Place where the number of passing taps are saved.
  38         sw      zero,   0x14(a0)                // Place where the last pass tap value is stored
  39         li      a1,     0xaa55aa55              // Indicates that the First pass tap value is not found
  40         sw      a1,     0x10(a0)                // Place where the First pass tap value is stored
  41         nop
  42
  43         li      a0,     0xb8060000              // RESET_BASE_ADDRESS
  44         lw      a1,     0x1c(a0)                // Reading the RST_RESET_ADDRESS
  45         li      a2,     0x08000000              // Setting the RST_RESET_RTC_RESET
  46         or      a1,     a1,     a2
  47         sw      a1,     0x1c(a0)
  48
  49         li      a3,     0xffffffff
  50         xor     a2,     a2,     a3
  51         and     a1,     a1,     a2
  52         sw      a1,     0x1c(a0)                // Taking the RTC out of RESET
  53         nop
  54
  55         li      a0,     0xb8107000              // RTC_BASE_ADDRESS
  56         li      a1,     0x1
  57         sw      a1,     0x0040(a0)              // RTC_SYNC_RESET_ADDRESS
  58
  59         li      a2,     0x2
  60
  61 _poll_for_RTC_ON:
  62         lw      a1,     0x0044(a0)              // RTC_SYNC_STATUS_ADDRESS
  63         and     a1,     a2,     a1
  64         bne     a1,     a2,     _poll_for_RTC_ON
  65
  66
  67 _CHANGE_TAPS:
  68
  69         li      t0,     0xbd001f00              // Read the current value of the TAP for programming
  70         lw      t1,     0x0(t0)
  71         li      t2,     0x00000000
  72         or      t3,     t1,     t2
  73
  74
  75         li      t0,     0xb8000000              // DDR_BASE_ADDRESS
  76
  77         sw      t3,     0x1c(t0)                // TAP_CONTROL_0_ADDRESS
  78         sw      t3,     0x20(t0)                // TAP_CONTROL_1_ADDRESS
  79         sw      t3,     0x24(t0)                // TAP_CONTROL_2_ADDRESS
  80         sw      t3,     0x28(t0)                // TAP_CONTROL_3_ADDRESS
  81
  82         li      t1,     0x00000010              // Running the test 8 times
  83         sw      t1,     0x0068(t0)              // PERF_COMP_ADDR_1_ADDRESS
  84
  85         li      t1,     0xfa5de83f              // 4 Row Address Bits, 4 Column Address Bits, 2 BA bits
  86         sw      t1,     0x002c(t0)              // PERF_MASK_ADDR_0_ADDRESS
  87
  88         li      t1,     0x0000ffff
  89         sw      t1,     0x0070(t0)              // PERF_COMP_AHB_GE0_1_ADDRESS
  90
  91         li      t1,     0x0000ffff
  92         sw      t1,     0x0040(t0)              // PERF_COMP_AHB_GE1_0_ADDRESS
  93
  94         li      t1,     0x0000ffff
  95         sw      t1,     0x0078(t0)              // PERF_COMP_AHB_GE1_1_ADDRESS
  96
  97         li      t1,     0x0000ffff
  98         sw      t1,     0x0034(t0)              // PERF_MASK_AHB_GE0_0_ADDRESS
  99
 100         li      t1,     0x0000ffff
 101         sw      t1,     0x006c(t0)              // PERF_MASK_AHB_GE0_1_ADDRESS
 102
 103         li      t1,     0x0000ffff
 104         sw      t1,     0x003c(t0)              // PERF_MASK_AHB_GE1_0_ADDRESS
 105
 106         li      t1,     0x0000ffff
 107         sw      t1,     0x0074(t0)              // PERF_MASK_AHB_GE1_1_ADDRESS
 108
 109         li      t1,     0x0000ffff
 110         sw      t1,     0x0038(t0)              // PERF_COMP_AHB_GE0_0_ADDRESS
 111
 112         li      t1,     0x00000001
 113         sw      t1,     0x011c(t0)              // DDR_BIST_ADDRESS
 114
 115         li      t2,     0x1
 116 _bist_done_poll:
 117         lw      t1,     0x0120(t0)              // DDR_BIST_STATUS_ADDRESS
 118         and     t1,     t1,     t2
 119         bne     t1,     t2,     _bist_done_poll
 120
 121         lw      t1,     0x0120(t0)              // DDR_BIST_STATUS_ADDRESS
 122         li      t4,     0x000001fe
 123         and     t2,     t1,     t4
 124         srl     t2,     t2,     0x1             // no. of Pass Runs
 125
 126         li      t5,     0x00000000
 127         sw      t5,     0x011c(t0)              //DDR_BIST_ADDRESS      - Stop the DDR BIST test
 128
 129         li      t5,     0x0001fe00
 130         and     t5,     t5,     t1
 131         bnez    t5,     _iterate_tap            // This is a redundant compare but nevertheless - Comparing the FAILS
 132
 133         lw      t1,     0x0068(t0)              // PERF_COMP_ADDR_1_ADDRESS
 134         li      t3,     0x000001fe
 135         and     t3,     t3,     t1
 136         srl     t3,     t3,     0x1             // No. of runs in the config register.
 137
 138         bne     t3,     t2,     _iterate_tap
 139
 140 pass_tap:
 141         li      t0,     0xbd001f00
 142         lw      t1,     0x4(t0)
 143         addiu   t1,     t1,     0x1
 144         sw      t1,     0x4(t0)
 145
 146         li      t0,     0xbd001f10
 147         lw      t1,     0x0(t0)
 148         li      t2,     0xaa55aa55
 149         beq     t1,     t2,     _first_pass
 150         nop
 151         li      t0,     0xbd001f00
 152         lw      t1,     0x0(t0)
 153         li      t0,     0xbd001f10
 154         sw      t1,     0x4(t0)
 155         nop
 156         b       _iterate_tap
 157         nop
 158
 159 _first_pass:
 160         li      t0,     0xbd001f00
 161         lw      t1,     0x0(t0)
 162         li      t0,     0xbd001f10
 163         sw      t1,     0x0(t0)
 164         sw      t1,     0x4(t0)
 165         nop
 166
 167 _iterate_tap:
 168
 169         li      t0,     0xbd001f00
 170         lw      t1,     0x0(t0)
 171         li      t2,     0x3f
 172         beq     t1,     t2,     _STOP_TEST
 173         nop
 174         addiu   t1,     t1,     0x1
 175         sw      t1,     0x0(t0)
 176         nop
 177         b       _CHANGE_TAPS
 178
 179 _STOP_TEST:
 180         li      t0,     0xbd001f00
 181         lw      t1,     0x4(t0)
 182         bnez    t1,     _load_center_tap
 183         nop
 184         li      t3,     0x8                     // Default Tap to be used
 185         b       _load_tap_into_reg
 186
 187 _load_center_tap:
 188         li      t0,     0xbd001f10
 189         lw      t1,     0x0(t0)
 190         lw      t2,     0x4(t0)
 191         add     t3,     t1,     t2
 192         srl     t3,     t3,     0x1
 193         li      t4,     0x3f
 194         and     t3,     t3,     t4
 195 _load_tap_into_reg:
 196         li      t0,     0xb8000000
 197         sw      t3,     0x1c(t0)                // TAP_CONTROL_0_ADDRESS
 198         sw      t3,     0x20(t0)                // TAP_CONTROL_1_ADDRESS
 199         sw      t3,     0x24(t0)                // TAP_CONTROL_2_ADDRESS
 200         sw      t3,     0x28(t0)                // TAP_CONTROL_3_ADDRESS
 201
 202         jr      ra
 203         nop
 204