2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/regdef.h>
26 #include <asm/mipsregs.h>
27 #include <asm/addrspace.h>
30 .globl ath_ddr_tap_cal
31 .type ath_ddr_tap_cal, @function
36 sw zero, 0x0(a0) // Place where the tap values are saved and used for SWEEP
37 sw zero, 0x4(a0) // Place where the number of passing taps are saved.
38 sw zero, 0x14(a0) // Place where the last pass tap value is stored
39 li a1, 0xaa55aa55 // Indicates that the First pass tap value is not found
40 sw a1, 0x10(a0) // Place where the First pass tap value is stored
43 li a0, 0xb8060000 // RESET_BASE_ADDRESS
44 lw a1, 0x1c(a0) // Reading the RST_RESET_ADDRESS
45 li a2, 0x08000000 // Setting the RST_RESET_RTC_RESET
52 sw a1, 0x1c(a0) // Taking the RTC out of RESET
55 li a0, 0xb8107000 // RTC_BASE_ADDRESS
57 sw a1, 0x0040(a0) // RTC_SYNC_RESET_ADDRESS
62 lw a1, 0x0044(a0) // RTC_SYNC_STATUS_ADDRESS
64 bne a1, a2, _poll_for_RTC_ON
69 li t0, 0xbd001f00 // Read the current value of the TAP for programming
75 li t0, 0xb8000000 // DDR_BASE_ADDRESS
77 sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS
78 sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS
79 sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS
80 sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS
82 li t1, 0x00000010 // Running the test 8 times
83 sw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS
85 li t1, 0xfa5de83f // 4 Row Address Bits, 4 Column Address Bits, 2 BA bits
86 sw t1, 0x002c(t0) // PERF_MASK_ADDR_0_ADDRESS
89 sw t1, 0x0070(t0) // PERF_COMP_AHB_GE0_1_ADDRESS
92 sw t1, 0x0040(t0) // PERF_COMP_AHB_GE1_0_ADDRESS
95 sw t1, 0x0078(t0) // PERF_COMP_AHB_GE1_1_ADDRESS
98 sw t1, 0x0034(t0) // PERF_MASK_AHB_GE0_0_ADDRESS
101 sw t1, 0x006c(t0) // PERF_MASK_AHB_GE0_1_ADDRESS
104 sw t1, 0x003c(t0) // PERF_MASK_AHB_GE1_0_ADDRESS
107 sw t1, 0x0074(t0) // PERF_MASK_AHB_GE1_1_ADDRESS
110 sw t1, 0x0038(t0) // PERF_COMP_AHB_GE0_0_ADDRESS
113 sw t1, 0x011c(t0) // DDR_BIST_ADDRESS
117 lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS
119 bne t1, t2, _bist_done_poll
121 lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS
124 srl t2, t2, 0x1 // no. of Pass Runs
127 sw t5, 0x011c(t0) //DDR_BIST_ADDRESS - Stop the DDR BIST test
131 bnez t5, _iterate_tap // This is a redundant compare but nevertheless - Comparing the FAILS
133 lw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS
136 srl t3, t3, 0x1 // No. of runs in the config register.
138 bne t3, t2, _iterate_tap
149 beq t1, t2, _first_pass
172 beq t1, t2, _STOP_TEST
182 bnez t1, _load_center_tap
184 li t3, 0x8 // Default Tap to be used
197 sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS
198 sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS
199 sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS
200 sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS