u-boot/board/ar7240/common/lowlevel_init_934x.S

   1 #include <config.h>
   2 #include <version.h>
   3 #include <asm/regdef.h>
   4 #include <asm/mipsregs.h>
   5 #include <asm/addrspace.h>
   6 #include <ar7240_soc.h>
   7
   8 /*
   9  * Helper macros.
  10  * These Clobber t7, t8 and t9
  11  */
  12 #define cpu_ddr_control_set(_mask, _val)        set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val)
  13
  14 #define set_val(_reg, _mask, _val)      \
  15         li              t7,     KSEG1ADDR(_reg);        \
  16         lw              t8,     0(t7);                          \
  17         li              t9,     ~_mask;                         \
  18         and             t8,     t8,     t9;                             \
  19         li              t9,     _val;                           \
  20         or              t8,     t8,     t9;                             \
  21         sw              t8,     0(t7)
  22
  23 #define set_bb_pll(reg, val)            \
  24         li              t7,     KSEG1ADDR(reg);         \
  25         li              t8,     val;                            \
  26         sw              t8,     0(t7);
  27
  28 #define set_srif_pll(reg, val)          \
  29         li              t7,     KSEG1ADDR(reg);         \
  30         li              t8,     val;                            \
  31         sw              t8,     0(t7);
  32
  33 #define set_srif_pll_reg(reg, _r)       \
  34         li              t7,     KSEG1ADDR(reg);         \
  35         sw              _r,     0(t7);
  36
  37 #define inc_loop_count(loc)                     \
  38         li              t9,     loc;                            \
  39         lw              t7,     0(t9);                          \
  40         addi    t7,     t7,     1;                              \
  41         sw              t7,     0(t9);
  42
  43 #define clear_loop_count(loc)           \
  44         li              t9,             loc;                    \
  45         sw              zero,   0(t9);
  46
  47 /******************************************************************************
  48  * first level initialization:
  49  *
  50  * 0) If clock cntrl reset switch is already set, we're recovering from
  51  *    "divider reset"; goto 3.
  52  * 1) Setup divide ratios.
  53  * 2) Reset.
  54  * 3) Setup pll's, wait for lock.
  55  *
  56  *****************************************************************************/
  57
  58 .globl lowlevel_init
  59         .type   lowlevel_init, @function
  60         .text
  61         .align 4
  62
  63 lowlevel_init:
  64         set_bb_pll(DPLL2_ADDRESS_c4, 0x13210f00);       // 0x181161c4 (AR934X_SRIF_CPU_DPLL2_REG)
  65         set_bb_pll(DPLL3_ADDRESS_c8, 0x03000000);       // 0x181161c8 (AR934X_SRIF_CPU_DPLL3_REG)
  66         set_bb_pll(DPLL2_ADDRESS_44, 0x13210f00);       // 0x18116244 (AR934X_SRIF_DDR_DPLL2_REG)
  67         set_bb_pll(DPLL3_ADDRESS_48, 0x03000000);       // 0x18116248 (AR934X_SRIF_DDR_DPLL3_REG)
  68         set_bb_pll(DPLL3_ADDRESS_88, 0x03000000);       // 0x18116188 (??)
  69
  70 ref_recognition:
  71         li      t5,     KSEG1ADDR(WASP_BOOTSTRAP_REG);
  72         li      t6,     WASP_REF_CLK_25
  73         lw      t7,     0(t5);
  74         and     t6,     t7,     t6
  75         beq     zero,   t6,     setup_ref25_val
  76         nop
  77
  78 setup_ref40_val:
  79         li      t5,     CPU_PLL_CONFIG_NINT_VAL_40
  80         li      t6,     DDR_PLL_CONFIG_NINT_VAL_40
  81         li      t7,     CPU_PLL_NFRAC_40
  82         li      t9,     DDR_PLL_NFRAC_40
  83         b       1f
  84         nop
  85
  86 setup_ref25_val:
  87         li      t5,     CPU_PLL_CONFIG_NINT_VAL_25
  88         li      t6,     DDR_PLL_CONFIG_NINT_VAL_25
  89         li      t7,     CPU_PLL_NFRAC_25
  90         li      t9,     DDR_PLL_NFRAC_25
  91
  92 1:
  93         li      t4,     (CPU_PLL_DITHER_DITHER_EN_SET(0) | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf));
  94         or      t4,     t4,     t7
  95
  96         li      t8,     (CPU_PLL_CONFIG_REF_DIV_VAL | CPU_PLL_CONFIG_RANGE_VAL | CPU_PLL_CONFIG_OUT_DIV_VAL2);
  97         or      t5,     t5,     t8
  98
  99         li      t8,     (DDR_PLL_CONFIG_REF_DIV_VAL | DDR_PLL_CONFIG_RANGE_VAL | DDR_PLL_CONFIG_OUT_DIV_VAL2);
 100         or      t6,     t6,     t8
 101
 102         li      t3,     (DDR_PLL_DITHER_DITHER_EN_SET(0) | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf));
 103         or      t3,     t3,     t9
 104
 105 pll_bypass_set:
 106         cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
 107         cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
 108         cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
 109
 110 init_cpu_pll:
 111         li      t7,     KSEG1ADDR(AR934X_CPU_PLL_CONFIG);
 112         li      t8,     CPU_PLL_CONFIG_PLLPWD_SET(1)
 113         or      t8,     t8,     t5
 114         sw      t8,     0(t7);
 115
 116 init_ddr_pll:
 117         li      t7,     KSEG1ADDR(AR934X_DDR_PLL_CONFIG);
 118         li      t8,     DDR_PLL_CONFIG_PLLPWD_SET(1)
 119         or      t8,     t8,     t6
 120         sw      t8,     0(t7);
 121
 122 init_ahb_pll:
 123         li      t7,     KSEG1ADDR(AR934X_CPU_DDR_CLOCK_CONTROL);
 124         li      t8,     (CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | \
 125                         CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR | \
 126                         CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR | \
 127                         CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU | \
 128                         CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | \
 129                         CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | \
 130                         CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | \
 131                         CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | \
 132                         CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
 133         sw      t8,     0(t7);
 134
 135         /* Use built in values, based on ref clock */
 136         li      t5,     KSEG1ADDR(WASP_BOOTSTRAP_REG);
 137         li      t6,     WASP_REF_CLK_25
 138         lw      t7,     0(t5);
 139         and     t6,     t7,     t6
 140         beq     zero,   t6,     1f
 141         nop
 142 #if !defined(CONFIG_AP123)
 143         /*              refdiv          nint            nfrac */
 144         li      t4,     ((0x8 << 27) | (112 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint
 145         li      t5,     ((0x8 << 27) | (90 << 18) | 0); // ddr freq = (40 MHz refclk/refdiv 8) * Nint
 146         j       2f
 147         nop
 148 1:
 149         li      t4,     ((0x5 << 27) | (112 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint
 150         li      t5,     ((0x5 << 27) | (90 << 18) | 0); // ddr freq = (25 MHz refclk/refdiv 5) * Nint
 151         j       2f
 152         nop
 153 #else   /* defined(CONFIG_AP123) */
 154         /*              refdiv          nint            nfrac */
 155         li      t4,     ((0x8 << 27) | (107 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint
 156         li      t5,     ((0x8 << 27) | (160 << 18) | 0);// ddr freq = (40 MHz refclk/refdiv 8) * Nint
 157         j       2f
 158         nop
 159 1:
 160         li      t4,     ((0x5 << 27) | (107 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint
 161         li      t5,     ((0x5 << 27) | (160 << 18) | 0);// ddr freq = (25 MHz refclk/refdiv 5) * Nint
 162         j       2f
 163         nop
 164 #endif  /* !defined(CONFIG_AP123) */
 165
 166 /* CPU */
 167 2:
 168         clear_loop_count(ATH_CPU_COUNT_LOC);
 169
 170 cpu_pll_is_not_locked:
 171         inc_loop_count(ATH_CPU_COUNT_LOC);
 172         set_srif_pll(0xb81161c4, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
 173         set_srif_pll_reg(0xb81161c0, t4);
 174         set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
 175         set_srif_pll(0xb81161c8, (6 << 23));
 176         set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7));
 177
 178 cpu_clear_do_meas1:
 179         li      t7,     KSEG1ADDR(CPU_DPLL3_ADDRESS)
 180         lw      t8,     0(t7)
 181         li      t9,     ~CPU_DPLL3_DO_MEAS_SET(1)
 182         and     t8,     t8,     t9
 183         sw      t8,     0(t7)
 184
 185 cpu_set_do_meas:
 186         li      t7,     KSEG1ADDR(CPU_DPLL3_ADDRESS)
 187         lw      t8,     0(t7)
 188         li      t9,     CPU_DPLL3_DO_MEAS_SET(1)
 189         or      t8,     t8,     t9
 190         sw      t8,     0(t7)
 191         li      t7,     KSEG1ADDR(CPU_DPLL4_ADDRESS)
 192
 193 cpu_wait_for_meas_done:
 194         lw      t8,     0(t7)
 195         andi    t8,     t8,     CPU_DPLL4_MEAS_DONE_SET(1)
 196         beqz    t8,     cpu_wait_for_meas_done
 197         nop
 198
 199 cpu_clear_do_meas2:
 200         li      t7,     KSEG1ADDR(CPU_DPLL3_ADDRESS)
 201         lw      t8,     0(t7)
 202         li      t9,     ~CPU_DPLL3_DO_MEAS_SET(1)
 203         and     t8,     t8,     t9
 204         sw      t8,     0(t7)
 205
 206 cpu_read_sqsum_dvc:
 207         li      t7,     KSEG1ADDR(CPU_DPLL3_ADDRESS)
 208         lw      t8,     0(t7)
 209         li      t9,     CPU_DPLL3_SQSUM_DVC_MASK
 210         and     t8,     t8,     t9
 211         sra     t8,     t8,     CPU_DPLL3_SQSUM_DVC_LSB
 212         li      t9,     0x40000
 213         subu    t8,     t8,     t9
 214         bgez    t8,     cpu_pll_is_not_locked
 215         nop
 216
 217 /* DDR */
 218         clear_loop_count(ATH_DDR_COUNT_LOC)
 219
 220 ddr_pll_is_not_locked:
 221         inc_loop_count(ATH_DDR_COUNT_LOC)
 222 #if !defined(CONFIG_AP123)
 223         set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
 224         set_srif_pll_reg(0xb8116240, t5);
 225         set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
 226         set_srif_pll(0xb8116248, (6 << 23));
 227         set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7));
 228 #else /* defined(CONFIG_AP123) */
 229         /* AP123 uses outdiv = 1 for ddr pll */
 230         set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16));
 231         set_srif_pll_reg(0xb8116240, t5);
 232         set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16));
 233         set_srif_pll(0xb8116248, (6 << 23));
 234         set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7));
 235 #endif /* !defined(CONFIG_AP123) */
 236
 237 ddr_clear_do_meas1:
 238         li      t7,     KSEG1ADDR(DDR_DPLL3_ADDRESS)
 239         lw      t8,     0(t7)
 240         li      t9,     ~DDR_DPLL3_DO_MEAS_SET(1)
 241         and     t8,     t8,     t9
 242         sw      t8,     0(t7)
 243
 244 ddr_set_do_meas:
 245         li      t7,     KSEG1ADDR(DDR_DPLL3_ADDRESS)
 246         lw      t8,     0(t7)
 247         li      t9,     DDR_DPLL3_DO_MEAS_SET(1)
 248         or      t8,     t8,     t9
 249         sw      t8,     0(t7)
 250         li      t7,     KSEG1ADDR(DDR_DPLL4_ADDRESS)
 251
 252 ddr_wait_for_meas_done:
 253         lw      t8,     0(t7)
 254         andi    t8,     t8,     DDR_DPLL4_MEAS_DONE_SET(1)
 255         beqz    t8,     ddr_wait_for_meas_done
 256         nop
 257
 258 ddr_clear_do_meas2:
 259         li      t7,     KSEG1ADDR(DDR_DPLL3_ADDRESS)
 260         lw      t8,     0(t7)
 261         li      t9,     ~DDR_DPLL3_DO_MEAS_SET(1)
 262         and     t8,     t8,     t9
 263         sw      t8,     0(t7)
 264
 265 ddr_read_sqsum_dvc:
 266         li      t7,     KSEG1ADDR(DDR_DPLL3_ADDRESS)
 267         lw      t8,     0(t7)
 268         li      t9,     DDR_DPLL3_SQSUM_DVC_MASK
 269         and     t8,     t8,     t9
 270         sra     t8,     t8,     DDR_DPLL3_SQSUM_DVC_LSB
 271         li      t9,     0x40000
 272         subu    t8,     t8,     t9
 273         bgez    t8,     ddr_pll_is_not_locked
 274         nop
 275
 276 pll_bypass_unset:
 277         cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
 278         cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
 279         cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
 280
 281 ddr_pll_dither_unset:
 282         li      t7,     KSEG1ADDR(AR934X_DDR_PLL_DITHER);
 283         sw      t3,     0(t7);
 284
 285 cpu_pll_dither_unset:
 286         li      t7,     KSEG1ADDR(AR934X_CPU_PLL_DITHER);
 287         sw      t4,     0(t7);
 288
 289         jr ra
 290         nop