2 * Common functions for QC/A WiSoCs based boards support
4 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
7 * Linux/arch/mips/ath79/setup.c
9 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/mipsregs.h>
16 #include <asm/addrspace.h>
17 #include <soc/qca_soc_common.h>
19 #ifndef CONFIG_BOARD_CUSTOM_STRING
20 #define CONFIG_BOARD_CUSTOM_STRING "Unknown/OEM"
23 #define ALIGN_SIZE "8"
25 DECLARE_GLOBAL_DATA_PTR;
27 static u32 mac_is_not_valid = 1;
30 * Put QCA SOC name, version and revision in buffer
32 void qca_soc_name_rev(char *buf)
41 /* Get revision ID value */
42 id = qca_soc_reg_read(QCA_RST_REVISION_ID_REG);
44 major = id & QCA_RST_REVISION_ID_MAJOR_MASK;
45 rev = id & QCA_RST_REVISION_ID_REV_MASK;
48 #if (SOC_TYPE & QCA_AR933X_SOC)
49 case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL:
50 sprintf(buf, "AR9330 rev. %d", rev);
52 case QCA_RST_REVISION_ID_MAJOR_AR9331_VAL:
53 sprintf(buf, "AR9331 rev. %d", rev);
56 #if (SOC_TYPE & QCA_AR934X_SOC)
57 case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
58 sprintf(buf, "AR9341 rev. %d", rev);
60 case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
61 sprintf(buf, "AR9344 rev. %d", rev);
64 #if (SOC_TYPE & QCA_QCA953X_SOC)
65 case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL:
66 sprintf(buf, "QCA953x ver. 1 rev. %d", rev);
68 case QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL:
69 sprintf(buf, "QCA953x ver. 2 rev. %d", rev);
72 #if (SOC_TYPE & QCA_QCA955X_SOC)
73 case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL:
74 sprintf(buf, "QCA9558 rev. %d", rev);
78 sprintf(buf, "Unknown");
84 * Prints available information about the board
86 void print_board_info(void)
88 u32 ahb_clk, cpu_clk, ddr_clk, spi_clk, ref_clk;
94 printf("%" ALIGN_SIZE "s %s\n", "BOARD:", CONFIG_BOARD_CUSTOM_STRING);
96 /* SOC name, version and revision */
97 qca_soc_name_rev(buffer);
98 printf("%" ALIGN_SIZE "s %s\n", "SOC:", buffer);
102 printf("%" ALIGN_SIZE "s %s\n", "CPU:", buffer);
104 /* RAM size and type */
105 printf("%" ALIGN_SIZE "s ", "RAM:");
106 print_size(bd->bi_memsize, "");
108 switch (qca_dram_type()) {
109 case RAM_MEMORY_TYPE_SDR:
112 case RAM_MEMORY_TYPE_DDR1:
115 case RAM_MEMORY_TYPE_DDR2:
122 /* DDR interface width */
123 printf("%d-bit ", qca_dram_ddr_width());
126 printf("CL%d\n", qca_dram_cas_lat());
128 /* SPI NOR FLASH sizes and types */
129 printf("%" ALIGN_SIZE "s ", "FLASH:");
131 for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
132 if (flash_info[bank].size == 0)
136 printf("%" ALIGN_SIZE "s ", " ");
138 print_size(flash_info[bank].size, "");
140 if (flash_info[bank].manuf_name != NULL)
141 printf(" %s", flash_info[bank].manuf_name);
143 if (flash_info[bank].model_name != NULL)
144 printf(" %s", flash_info[bank].model_name);
150 printf("%" ALIGN_SIZE "s %02X:%02X:%02X:%02X:%02X:%02X", "MAC:",
151 bd->bi_enetaddr[0],bd->bi_enetaddr[1], bd->bi_enetaddr[2],
152 bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
154 if (mac_is_not_valid) {
161 printf("%" ALIGN_SIZE "s CPU/RAM/AHB/SPI/REF\n", "CLOCKS:");
163 qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
164 cpu_clk = cpu_clk / 1000000;
165 ddr_clk = ddr_clk / 1000000;
166 ahb_clk = ahb_clk / 1000000;
167 spi_clk = spi_clk / 1000000;
168 ref_clk = ref_clk / 1000000;
170 printf("%" ALIGN_SIZE "s %3d/%3d/%3d/%3d/%3d MHz\n",
171 " ", cpu_clk, ddr_clk, ahb_clk, spi_clk, ref_clk);
177 * Reads MAC address if available or uses fixed one
179 void macaddr_init(u8 *mac_addr)
182 u8 fixed_mac[6] = {0x00, 0x03, 0x7F, 0x09, 0x0B, 0xAD};
184 #if defined(OFFSET_MAC_ADDRESS)
185 memcpy(buffer, (void *)(CFG_FLASH_BASE
186 + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
189 * Check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
190 * both of them should be 0:
191 * I/G bit == 0 -> Individual MAC address (unicast address)
192 * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
194 if (CHECK_BIT((buffer[0] & 0xFF), 0) != 0 ||
195 CHECK_BIT((buffer[0] & 0xFF), 1) != 0) {
196 memcpy(buffer, fixed_mac, 6);
198 mac_is_not_valid = 0;
201 memcpy(buffer, fixed_mac, 6);
204 memcpy(mac_addr, buffer, 6);
208 * Returns "reset button" status:
209 * 1 -> button is pressed
210 * 0 -> button is not pressed
212 int reset_button_status(void)
214 #ifdef CONFIG_GPIO_RESET_BTN
217 gpio = qca_soc_reg_read(QCA_GPIO_IN_REG);
219 if (gpio & (1 << CONFIG_GPIO_RESET_BTN)) {
220 #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
226 #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
238 * Returns main CPU clock in Hz
240 u32 main_cpu_clk(void)
244 qca_sys_clocks(&cpu_clk, NULL, NULL, NULL, NULL);
250 * Calls full chip reset
252 void full_reset(void)
254 qca_full_chip_reset();