u-boot/board/ar7240/common/common.c

   1 /*
   2  * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * SPDX-License-Identifier:GPL-2.0
   5  */
   6
   7 #include <config.h>
   8 #include <common.h>
   9 #include <flash.h>
  10 #include <asm/mipsregs.h>
  11 #include <asm/addrspace.h>
  12 #include <soc/qca_soc_common.h>
  13
  14 #define ALIGN_SIZE              "8"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static u32 mac_is_not_valid = 1;
  19
  20 /*
  21  * Prints available information about the board
  22  */
  23 void print_board_info(void)
  24 {
  25         u32 ahb_clk, cpu_clk, ddr_clk, spi_clk, ref_clk;
  26         u32 bank;
  27         bd_t *bd = gd->bd;
  28         char buffer[24];
  29
  30         /* Board name */
  31 #ifdef BOARD_CUSTOM_STRING
  32         printf("%" ALIGN_SIZE "s %s\n", "BOARD:", BOARD_CUSTOM_STRING);
  33 #endif
  34
  35         /* SOC name, version and revision */
  36         qca_soc_name_rev(buffer);
  37         printf("%" ALIGN_SIZE "s %s\n", "SOC:", buffer);
  38
  39         /* MIPS CPU type */
  40         cpu_name(buffer);
  41         printf("%" ALIGN_SIZE "s %s\n", "CPU:", buffer);
  42
  43         /* RAM size and type */
  44         printf("%" ALIGN_SIZE "s ", "RAM:");
  45         print_size(bd->bi_memsize, "");
  46
  47         switch (qca_mem_type()) {
  48                 case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
  49                         puts(" SDR\n");
  50                         break;
  51                 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
  52                         puts(" DDR1\n");
  53                         break;
  54                 case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
  55                         puts(" DDR2\n");
  56                         break;
  57                 default:
  58                         puts("\n");
  59                         break;
  60         }
  61
  62         /* SPI NOR FLASH sizes and types */
  63         printf("%" ALIGN_SIZE "s ", "FLASH:");
  64
  65         for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
  66                 if (flash_info[bank].size == 0)
  67                         continue;
  68
  69                 if (bank > 0)
  70                         printf("%" ALIGN_SIZE "s ", " ");
  71
  72                 print_size(flash_info[bank].size, "");
  73
  74                 if (flash_info[bank].manuf_name != NULL)
  75                         printf(" %s", flash_info[bank].manuf_name);
  76
  77                 if (flash_info[bank].model_name != NULL)
  78                         printf(" %s", flash_info[bank].model_name);
  79
  80                 puts("\n");
  81         }
  82
  83         /* MAC address */
  84         printf("%" ALIGN_SIZE "s %02X:%02X:%02X:%02X:%02X:%02X", "MAC:",
  85                 bd->bi_enetaddr[0],bd->bi_enetaddr[1], bd->bi_enetaddr[2],
  86                 bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
  87
  88         if (mac_is_not_valid) {
  89                 puts(" (fixed)\n");
  90         } else {
  91                 puts("\n");
  92         }
  93
  94         /* System clocks */
  95         printf("%" ALIGN_SIZE "s CPU/RAM/AHB/SPI/REF\n", "CLOCKS:");
  96
  97         qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
  98         cpu_clk = cpu_clk / 1000000;
  99         ddr_clk = ddr_clk / 1000000;
 100         ahb_clk = ahb_clk / 1000000;
 101         spi_clk = spi_clk / 1000000;
 102         ref_clk = ref_clk / 1000000;
 103
 104         printf("%" ALIGN_SIZE "s %d/%d/%d/%3d/%3d MHz\n",
 105                 " ", cpu_clk, ddr_clk, ahb_clk, spi_clk, ref_clk);
 106
 107         puts("\n");
 108 }
 109
 110 /*
 111  * Reads MAC address if available or uses fixed one
 112  */
 113 void macaddr_init(u8 *mac_addr)
 114 {
 115         u8 buffer[6];
 116         u8 fixed_mac[6] = {0x00, 0x03, 0x7F, 0x09, 0x0B, 0xAD};
 117
 118 #if defined(OFFSET_MAC_ADDRESS)
 119         memcpy(buffer, (void *)(CFG_FLASH_BASE
 120                 + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
 121
 122         /*
 123          * Check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
 124          * both of them should be 0:
 125          * I/G bit == 0 -> Individual MAC address (unicast address)
 126          * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
 127          */
 128         if (CHECK_BIT((buffer[0] & 0xFF), 0) != 0 ||
 129                 CHECK_BIT((buffer[0] & 0xFF), 1) != 0) {
 130                 memcpy(buffer, fixed_mac, 6);
 131         } else {
 132                 mac_is_not_valid = 0;
 133         }
 134 #else
 135         memcpy(buffer, fixed_mac, 6);
 136 #endif
 137
 138         memcpy(mac_addr, buffer, 6);
 139 }
 140
 141 /*
 142  * Returns main CPU clock in Hz
 143  */
 144 u32 main_cpu_clk(void)
 145 {
 146         u32 cpu_clk;
 147
 148         qca_sys_clocks(&cpu_clk, NULL, NULL, NULL, NULL);
 149
 150         return cpu_clk;
 151 }
 152
 153 /*
 154  * Calls full chip reset
 155  */
 156 void full_reset(void)
 157 {
 158         qca_full_chip_reset();
 159 }