u-boot/board/ar7240/common/ath_pci.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/addrspace.h>
  27 #include <config.h>
  28 #include <version.h>
  29 #include <pci.h>
  30 #include <atheros.h>
  31
  32 /*
  33 ** PCI controller "hose" value
  34 */
  35
  36 static struct pci_controller hose;
  37
  38 static int ath_local_read_config(int where, int size, uint32_t *value);
  39 static int ath_local_write_config(int where, int size, uint32_t value);
  40
  41 static int
  42 ath_local_read_config(int where, int size, uint32_t *value)
  43 {
  44         *value = ath_reg_rd(ATH_PCI_CRP + where);
  45         return 0;
  46 }
  47
  48 static int
  49 ath_local_write_config(int where, int size, uint32_t value)
  50 {
  51         ath_reg_wr((ATH_PCI_CRP + where),value);
  52         return 0;
  53 }
  54
  55 static int
  56 ath_pci_read_config(struct pci_controller *hose,
  57                         pci_dev_t dev, int where, uint32_t *value)
  58 {
  59         *value = ath_reg_rd(ATH_PCI_DEV_CFGBASE + where);
  60         return 0;
  61 }
  62
  63 static int
  64 ath_pci_write_config(struct pci_controller *hose,
  65                         pci_dev_t dev, int where, uint32_t value)
  66 {
  67         ath_reg_wr((ATH_PCI_DEV_CFGBASE + where), value);
  68         return 0;
  69 }
  70
  71 #ifdef PCIE2_APP_ADDRESS
  72 static int
  73 ath_local_read_config_rc2(int where, int size, uint32_t *value)
  74 {
  75         *value = ath_reg_rd(0x18250000 + where);
  76         return 0;
  77 }
  78
  79 static int
  80 ath_local_write_config_rc2(int where, int size, uint32_t value)
  81 {
  82         ath_reg_wr((0x18250000 + where),value);
  83         return 0;
  84 }
  85
  86 static int
  87 ath_pci_read_config_rc2(struct pci_controller *hose,
  88                         pci_dev_t dev, int where, uint32_t *value)
  89 {
  90         *value = ath_reg_rd(0xb6000000 + where);
  91         return 0;
  92 }
  93
  94 static int
  95 ath_pci_write_config_rc2(struct pci_controller *hose,
  96                         pci_dev_t dev, int where, uint32_t value)
  97 {
  98         ath_reg_wr((0xb6000000 + where), value);
  99         return 0;
 100 }
 101 #endif
 102
 103 /*
 104 ** We will use the ART configuration information stored in flash to initialize
 105 ** these devices as required.
 106 */
 107
 108 void plat_dev_init(void)
 109 {
 110         u32     val;
 111         u32     addr;
 112         u32     BaseAddr = 0x10000000;
 113         u32     CalAddr = WLANCAL;
 114         volatile u16 *calData;
 115
 116         /*
 117          * Copy the device ID from Flash to device config space.
 118          */
 119
 120         calData = (u16 *)CalAddr;
 121
 122 #ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP
 123         if (calData[0] != 0xa55a && calData[0] != 0x5aa5)
 124         {
 125 #ifndef COMPRESSED_UBOOT
 126                 prmsg("BOARD IS NOT CALIBRATED!!!\n");
 127 #endif
 128                 return;
 129         }
 130 #else
 131         return;
 132 #endif
 133         /*
 134         ** Need to setup the PCI device to access the internal registers
 135         */
 136         if ((is_ar7241() || is_ar7242()))
 137                 ath_pci_write_config(&hose, NULL, 0x10, 0x1000ffff);
 138         else
 139                 ath_pci_write_config(&hose, NULL, 0x10, 0xffff);
 140
 141         ath_pci_write_config(&hose, NULL, 0x04, 0x6);
 142
 143 #ifdef PCIE2_APP_ADDRESS
 144         ath_pci_write_config_rc2(&hose, NULL, 0x10, 0xffff);
 145
 146         ath_pci_write_config_rc2(&hose, NULL, 0x04, 0x6);
 147 #endif
 148
 149         /*
 150         ** Set pointer to first reg address
 151         */
 152
 153         calData += ATH_ART_PCICFG_OFFSET;
 154
 155         while(*calData != 0xffff)
 156         {
 157                 u16 cd;
 158
 159                 cd = *calData++;
 160                 addr = BaseAddr + cd;
 161                 val = *calData++;
 162                 val |= (*calData++) << 16;
 163
 164                 ath_reg_wr_nf(addr,val);
 165                 udelay(100);
 166         }
 167
 168         return;
 169 }
 170
 171
 172 /******************************************************************************/
 173 /*!
 174 ** \brief pci host initialization
 175 **
 176 ** Sets up the PCI controller on the host. For AR7240 this may not be necessary,
 177 ** but this function is required for board support.
 178 **
 179 ** We want a 1:1 mapping between PCI and DDR for inbound and outbound.
 180 ** The PCI<---AHB decoding works as follows:
 181 **
 182 ** 8 registers in the DDR unit provide software configurable 32 bit offsets
 183 ** for each of the eight 16MB PCI windows in the 128MB. The offsets will be
 184 ** added to any address in the 16MB segment before being sent to the PCI unit.
 185 **
 186 ** Essentially for any AHB address generated by the CPU,
 187 ** 1. the MSB four bits are stripped off, [31:28],
 188 ** 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of
 189 **    the AHB space
 190 ** 3. Bits 26:24 are used to access one of the 8 window registers and are
 191 **    masked off.
 192 ** 4. If it is a PCI address, then the WINDOW offset in the WINDOW register
 193 **    corresponding to the next 3 bits (bit 26:24) is ADDED to the address,
 194 **    to generate the address to PCI unit.
 195 **
 196 **     eg. CPU address = 0x100000ff
 197 **         window 0 offset = 0x10000000
 198 **         This points to lowermost 16MB window in PCI space.
 199 **         So the resulting address would be 0x000000ff+0x10000000
 200 **         = 0x100000ff
 201 **
 202 **         eg2. CPU address = 0x120000ff
 203 **         WINDOW 2 offset = 0x12000000
 204 **         resulting address would be 0x000000ff+0x12000000
 205 **                         = 0x120000ff
 206 **
 207 ** There is no translation for inbound access (PCI device as a master)
 208 **
 209 **  \return N/A
 210 */
 211
 212 #ifdef  COMPRESSED_UBOOT
 213 #       define PCI_INIT_RET_TYPE        int
 214 #       define PCI_INIT_RETURN          return 0
 215 #else
 216 #       define PCI_INIT_RET_TYPE        void
 217 #       define PCI_INIT_RETURN          return
 218 #endif
 219
 220 PCI_INIT_RET_TYPE
 221 pci_init_board (void)
 222 {
 223
 224         /**
 225          * We never used pci & pci-e, and sometimes should not initialize with
 226          * it, or fail to startup
 227          *               20141216
 228          */
 229         return 0;
 230
 231 #ifdef CONFIG_ATH_EMULATION
 232         prmsg("--- Skipping %s for emulation\n", __func__);
 233 #else
 234         uint32_t cmd;
 235
 236         if (is_drqfn() && !is_qca953x()) {
 237                 /*
 238                  * Dont enable PCIe in DRQFN package as it has some issues
 239                  * related to PCIe
 240                  */
 241                 PCI_INIT_RETURN;
 242         }
 243
 244 #if defined(CONFIG_MACH_QCA953x)
 245         if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
 246                 ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
 247
 248                 ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
 249                 ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
 250
 251                 ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
 252
 253                 ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
 254
 255                 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
 256                 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
 257
 258                 ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
 259
 260                 PCI_INIT_RETURN;
 261         } else {
 262                  /* Honeybee -The PCIe reference clock frequency is being changed
 263                     to vary from 99.968MHz to 99.999MHz using SS modulation */
 264                 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
 265                         PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
 266                         PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
 267                         PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
 268                         PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
 269
 270                 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
 271                         PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
 272                         PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
 273         }
 274 #else
 275
 276 #if defined(CONFIG_MACH_QCA956x)
 277
 278         ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
 279
 280         ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
 281                       PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
 282                       PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
 283                       PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
 284
 285         ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
 286                       PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
 287                       PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
 288 #else
 289         // common for rc1 and rc2
 290         ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
 291                 PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
 292                 PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
 293                 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
 294                 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
 295
 296         ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
 297                 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
 298 #endif
 299
 300 #endif
 301
 302         ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
 303                 PCIE_PLL_CONFIG_REFDIV_SET(1) |
 304                 PCIE_PLL_CONFIG_BYPASS_SET(1) |
 305                 PCIE_PLL_CONFIG_PLLPWD_SET(1));
 306         udelay(10000);
 307
 308         ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
 309         udelay(1000);
 310         ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
 311         udelay(1000);
 312
 313 #if !defined(CONFIG_MACH_QCA956x)
 314
 315 #ifdef PCIE2_APP_ADDRESS
 316         if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
 317                 pci_rc2_init_board();
 318                 return;
 319         }
 320 #endif
 321
 322         ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
 323         udelay(10000);
 324
 325         ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
 326         udelay(10000);
 327
 328 #ifdef PCIE2_APP_ADDRESS
 329         ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
 330         udelay(10000);
 331 #endif
 332
 333         ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0);   // Put endpoint in reset
 334         udelay(100000);
 335
 336 #ifdef PCIE2_APP_ADDRESS
 337         ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
 338         udelay(10000);
 339 #endif
 340
 341         ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
 342         udelay(10000);
 343
 344         ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
 345         udelay(10000);
 346
 347         ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
 348                                         PCIE_APP_CFG_BE_SET(0xf) |
 349                                         PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
 350                                         PCIE_APP_LTSSM_ENABLE_SET(1));
 351
 352         cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 353                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 354
 355         ath_local_write_config(PCI_COMMAND, 4, cmd);
 356         ath_local_write_config(0x20, 4, 0x1ff01000);
 357         ath_local_write_config(0x24, 4, 0x1ff01000);
 358
 359         ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4);   // Pull endpoint out of reset
 360         udelay(100000);
 361
 362         /*
 363          * Check if the WLAN PCI-E H/W is present, If the
 364          * WLAN H/W is not present, skip the PCI platform
 365          * initialization code and return
 366          */
 367         if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
 368                 prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
 369         }
 370 #endif
 371
 372 #ifdef PCIE2_APP_ADDRESS
 373         pci_rc2_init_board();
 374 #endif
 375
 376 #ifndef COMPRESSED_UBOOT
 377         /*
 378          * Now, configure for u-boot tools
 379          */
 380
 381         hose.first_busno = 0;
 382         hose.last_busno = 0xff;
 383
 384         /* System space */
 385         pci_set_region( &hose.regions[0],
 386                         0x80000000,
 387                         0x00000000,
 388                         32 * 1024 * 1024,
 389                         PCI_REGION_MEM | PCI_REGION_MEMORY);
 390
 391         /* PCI memory space */
 392         pci_set_region( &hose.regions[1],
 393                         0x10000000,
 394                         0x10000000,
 395                         128 * 1024 * 1024,
 396                         PCI_REGION_MEM);
 397
 398         hose.region_count = 2;
 399
 400         pci_register_hose(&hose);
 401
 402         pci_set_ops(    &hose,
 403                         pci_hose_read_config_byte_via_dword,
 404                         pci_hose_read_config_word_via_dword,
 405                         ath_pci_read_config,
 406                         pci_hose_write_config_byte_via_dword,
 407                         pci_hose_write_config_word_via_dword,
 408                         ath_pci_write_config);
 409 #endif
 410         plat_dev_init();
 411 #endif /* CONFIG_ATH_EMULATION */
 412
 413         PCI_INIT_RETURN;
 414 }
 415
 416 #ifdef PCIE2_APP_ADDRESS
 417 void
 418 pci_rc2_init_board (void)
 419 {
 420 #if defined(CONFIG_MACH_QCA956x)
 421         ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1);
 422         udelay(10000);
 423         ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73));
 424         udelay(10000);
 425         ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
 426                                           RST_RESET_PCIE_RESET_SET(1));
 427
 428         udelay(10000);
 429         ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
 430                                             RST_RESET_PCIE_RESET_SET(1));
 431
 432         udelay(10000);
 433         ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
 434                                            RST_RESET_PCIE_RESET_SET(1));
 435
 436         udelay(10000);
 437         ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
 438                                              RST_RESET_PCIE_RESET_SET(1));
 439
 440         udelay(10000);
 441         ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1));
 442         udelay(10000);
 443         ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6);
 444         udelay(10000);
 445         ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) |
 446                                     PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
 447                                     PCIE_APP_CFG_BE_SET(0xf) |
 448                                     PCIE_APP_PCIE_BAR_MSN_SET(1));
 449         udelay(10000);
 450         ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) |
 451                                          PCIE_INT_MASK_NONFATAL_ERR_SET(1) |
 452                                          PCIE_INT_MASK_FATAL_ERR_SET(1) |
 453                                          PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) |
 454                                          PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) |
 455                                          PCIE_INT_MASK_INTA_SET(1) |
 456                                          PCIE_INT_MASK_INTB_SET(1) |
 457                                          PCIE_INT_MASK_INTC_SET(1) |
 458                                          PCIE_INT_MASK_INTD_SET(1) |
 459                                          PCIE_INT_MASK_MSI_SET(1) |
 460                                          PCIE_INT_MASK_MSI_ERR_SET(1) |
 461                                          PCIE_INT_MASK_AER_INT_SET(1) |
 462                                          PCIE_INT_MASK_AER_MSI_SET(1) |
 463                                          PCIE_INT_MASK_SYS_ERR_SET(1) |
 464                                          PCIE_INT_MASK_INTAL_SET(1) |
 465                                          PCIE_INT_MASK_INTBL_SET(1) |
 466                                          PCIE_INT_MASK_INTCL_SET(1) |
 467                                          PCIE_INT_MASK_INTDL_SET(1));
 468         udelay(10000);
 469         ath_local_write_config_rc2(0x70c, 4, 0x1b403200);
 470         udelay(10000);
 471         ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1));
 472         udelay(10000);
 473
 474         ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc));
 475         udelay(10000);
 476         ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) |
 477                                               PCIe_DPLL2_KD_SET(0xF));
 478         udelay(10000);
 479         ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4));
 480         udelay(10000);
 481
 482 #else
 483
 484         uint32_t        cmd;
 485
 486         ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1));
 487         udelay(10000);
 488
 489         ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1));
 490         udelay(10000);
 491
 492         ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
 493         udelay(10000);
 494
 495         ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0);  // Put endpoint in reset
 496         udelay(100000);
 497
 498         ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
 499         udelay(10000);
 500
 501         ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
 502         udelay(10000);
 503
 504         ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
 505         udelay(10000);
 506
 507         ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) |
 508                                         PCIE2_APP_CFG_BE_SET(0xf) |
 509                                         PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
 510                                         PCIE2_APP_LTSSM_ENABLE_SET(1));
 511
 512         cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 513                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 514
 515         ath_local_write_config_rc2(PCI_COMMAND, 4, cmd);
 516         ath_local_write_config_rc2(0x20, 4, 0x1ff01000);
 517         ath_local_write_config_rc2(0x24, 4, 0x1ff01000);
 518
 519         ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4);  // Pull endpoint out of reset
 520         udelay(100000);
 521
 522 #endif
 523         /*
 524          * Check if the WLAN PCI-E H/W is present, If the
 525          * WLAN H/W is not present, skip the PCI platform
 526          * initialization code and return
 527          */
 528         if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) {
 529                 prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
 530                 return;
 531         }
 532 }
 533 #endif