2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/mipsregs.h>
26 #include <asm/addrspace.h>
33 ** PCI controller "hose" value
36 static struct pci_controller hose;
38 static int ath_local_read_config(int where, int size, uint32_t *value);
39 static int ath_local_write_config(int where, int size, uint32_t value);
42 ath_local_read_config(int where, int size, uint32_t *value)
44 *value = ath_reg_rd(ATH_PCI_CRP + where);
49 ath_local_write_config(int where, int size, uint32_t value)
51 ath_reg_wr((ATH_PCI_CRP + where),value);
56 ath_pci_read_config(struct pci_controller *hose,
57 pci_dev_t dev, int where, uint32_t *value)
59 *value = ath_reg_rd(ATH_PCI_DEV_CFGBASE + where);
64 ath_pci_write_config(struct pci_controller *hose,
65 pci_dev_t dev, int where, uint32_t value)
67 ath_reg_wr((ATH_PCI_DEV_CFGBASE + where), value);
71 #ifdef PCIE2_APP_ADDRESS
73 ath_local_read_config_rc2(int where, int size, uint32_t *value)
75 *value = ath_reg_rd(0x18250000 + where);
80 ath_local_write_config_rc2(int where, int size, uint32_t value)
82 ath_reg_wr((0x18250000 + where),value);
87 ath_pci_read_config_rc2(struct pci_controller *hose,
88 pci_dev_t dev, int where, uint32_t *value)
90 *value = ath_reg_rd(0xb6000000 + where);
95 ath_pci_write_config_rc2(struct pci_controller *hose,
96 pci_dev_t dev, int where, uint32_t value)
98 ath_reg_wr((0xb6000000 + where), value);
104 ** We will use the ART configuration information stored in flash to initialize
105 ** these devices as required.
108 void plat_dev_init(void)
112 u32 BaseAddr = 0x10000000;
113 u32 CalAddr = WLANCAL;
114 volatile u16 *calData;
117 * Copy the device ID from Flash to device config space.
120 calData = (u16 *)CalAddr;
122 #ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP
123 if (calData[0] != 0xa55a && calData[0] != 0x5aa5)
125 #ifndef COMPRESSED_UBOOT
126 prmsg("BOARD IS NOT CALIBRATED!!!\n");
134 ** Need to setup the PCI device to access the internal registers
136 if ((is_ar7241() || is_ar7242()))
137 ath_pci_write_config(&hose, NULL, 0x10, 0x1000ffff);
139 ath_pci_write_config(&hose, NULL, 0x10, 0xffff);
141 ath_pci_write_config(&hose, NULL, 0x04, 0x6);
143 #ifdef PCIE2_APP_ADDRESS
144 ath_pci_write_config_rc2(&hose, NULL, 0x10, 0xffff);
146 ath_pci_write_config_rc2(&hose, NULL, 0x04, 0x6);
150 ** Set pointer to first reg address
153 calData += ATH_ART_PCICFG_OFFSET;
155 while(*calData != 0xffff)
160 addr = BaseAddr + cd;
162 val |= (*calData++) << 16;
164 ath_reg_wr_nf(addr,val);
172 /******************************************************************************/
174 ** \brief pci host initialization
176 ** Sets up the PCI controller on the host. For AR7240 this may not be necessary,
177 ** but this function is required for board support.
179 ** We want a 1:1 mapping between PCI and DDR for inbound and outbound.
180 ** The PCI<---AHB decoding works as follows:
182 ** 8 registers in the DDR unit provide software configurable 32 bit offsets
183 ** for each of the eight 16MB PCI windows in the 128MB. The offsets will be
184 ** added to any address in the 16MB segment before being sent to the PCI unit.
186 ** Essentially for any AHB address generated by the CPU,
187 ** 1. the MSB four bits are stripped off, [31:28],
188 ** 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of
190 ** 3. Bits 26:24 are used to access one of the 8 window registers and are
192 ** 4. If it is a PCI address, then the WINDOW offset in the WINDOW register
193 ** corresponding to the next 3 bits (bit 26:24) is ADDED to the address,
194 ** to generate the address to PCI unit.
196 ** eg. CPU address = 0x100000ff
197 ** window 0 offset = 0x10000000
198 ** This points to lowermost 16MB window in PCI space.
199 ** So the resulting address would be 0x000000ff+0x10000000
202 ** eg2. CPU address = 0x120000ff
203 ** WINDOW 2 offset = 0x12000000
204 ** resulting address would be 0x000000ff+0x12000000
207 ** There is no translation for inbound access (PCI device as a master)
212 #ifdef COMPRESSED_UBOOT
213 # define PCI_INIT_RET_TYPE int
214 # define PCI_INIT_RETURN return 0
216 # define PCI_INIT_RET_TYPE void
217 # define PCI_INIT_RETURN return
221 pci_init_board (void)
225 * We never used pci & pci-e, and sometimes should not initialize with
226 * it, or fail to startup
231 #ifdef CONFIG_ATH_EMULATION
232 prmsg("--- Skipping %s for emulation\n", __func__);
236 if (is_drqfn() && !is_qca953x()) {
238 * Dont enable PCIe in DRQFN package as it has some issues
244 #if defined(CONFIG_MACH_QCA953x)
245 if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
246 ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
248 ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
249 ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
251 ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
253 ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
255 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
256 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
258 ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
262 /* Honeybee -The PCIe reference clock frequency is being changed
263 to vary from 99.968MHz to 99.999MHz using SS modulation */
264 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
265 PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
266 PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
267 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
268 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
270 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
271 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
272 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
276 #if defined(CONFIG_MACH_QCA956x)
278 ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
280 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
281 PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
282 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
283 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
285 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
286 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
287 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
289 // common for rc1 and rc2
290 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
291 PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
292 PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
293 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
294 PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
296 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
297 PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
302 ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
303 PCIE_PLL_CONFIG_REFDIV_SET(1) |
304 PCIE_PLL_CONFIG_BYPASS_SET(1) |
305 PCIE_PLL_CONFIG_PLLPWD_SET(1));
308 ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
310 ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
313 #if !defined(CONFIG_MACH_QCA956x)
315 #ifdef PCIE2_APP_ADDRESS
316 if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
317 pci_rc2_init_board();
322 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
325 ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
328 #ifdef PCIE2_APP_ADDRESS
329 ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
333 ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
336 #ifdef PCIE2_APP_ADDRESS
337 ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
341 ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
344 ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
347 ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
348 PCIE_APP_CFG_BE_SET(0xf) |
349 PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
350 PCIE_APP_LTSSM_ENABLE_SET(1));
352 cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
353 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
355 ath_local_write_config(PCI_COMMAND, 4, cmd);
356 ath_local_write_config(0x20, 4, 0x1ff01000);
357 ath_local_write_config(0x24, 4, 0x1ff01000);
359 ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
363 * Check if the WLAN PCI-E H/W is present, If the
364 * WLAN H/W is not present, skip the PCI platform
365 * initialization code and return
367 if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
368 prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
372 #ifdef PCIE2_APP_ADDRESS
373 pci_rc2_init_board();
376 #ifndef COMPRESSED_UBOOT
378 * Now, configure for u-boot tools
381 hose.first_busno = 0;
382 hose.last_busno = 0xff;
385 pci_set_region( &hose.regions[0],
389 PCI_REGION_MEM | PCI_REGION_MEMORY);
391 /* PCI memory space */
392 pci_set_region( &hose.regions[1],
398 hose.region_count = 2;
400 pci_register_hose(&hose);
403 pci_hose_read_config_byte_via_dword,
404 pci_hose_read_config_word_via_dword,
406 pci_hose_write_config_byte_via_dword,
407 pci_hose_write_config_word_via_dword,
408 ath_pci_write_config);
411 #endif /* CONFIG_ATH_EMULATION */
416 #ifdef PCIE2_APP_ADDRESS
418 pci_rc2_init_board (void)
420 #if defined(CONFIG_MACH_QCA956x)
421 ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1);
423 ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73));
425 ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
426 RST_RESET_PCIE_RESET_SET(1));
429 ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
430 RST_RESET_PCIE_RESET_SET(1));
433 ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
434 RST_RESET_PCIE_RESET_SET(1));
437 ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
438 RST_RESET_PCIE_RESET_SET(1));
441 ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1));
443 ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6);
445 ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) |
446 PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
447 PCIE_APP_CFG_BE_SET(0xf) |
448 PCIE_APP_PCIE_BAR_MSN_SET(1));
450 ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) |
451 PCIE_INT_MASK_NONFATAL_ERR_SET(1) |
452 PCIE_INT_MASK_FATAL_ERR_SET(1) |
453 PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) |
454 PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) |
455 PCIE_INT_MASK_INTA_SET(1) |
456 PCIE_INT_MASK_INTB_SET(1) |
457 PCIE_INT_MASK_INTC_SET(1) |
458 PCIE_INT_MASK_INTD_SET(1) |
459 PCIE_INT_MASK_MSI_SET(1) |
460 PCIE_INT_MASK_MSI_ERR_SET(1) |
461 PCIE_INT_MASK_AER_INT_SET(1) |
462 PCIE_INT_MASK_AER_MSI_SET(1) |
463 PCIE_INT_MASK_SYS_ERR_SET(1) |
464 PCIE_INT_MASK_INTAL_SET(1) |
465 PCIE_INT_MASK_INTBL_SET(1) |
466 PCIE_INT_MASK_INTCL_SET(1) |
467 PCIE_INT_MASK_INTDL_SET(1));
469 ath_local_write_config_rc2(0x70c, 4, 0x1b403200);
471 ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1));
474 ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc));
476 ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) |
477 PCIe_DPLL2_KD_SET(0xF));
479 ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4));
486 ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1));
489 ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1));
492 ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
495 ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset
498 ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
501 ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
504 ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
507 ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) |
508 PCIE2_APP_CFG_BE_SET(0xf) |
509 PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
510 PCIE2_APP_LTSSM_ENABLE_SET(1));
512 cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
513 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
515 ath_local_write_config_rc2(PCI_COMMAND, 4, cmd);
516 ath_local_write_config_rc2(0x20, 4, 0x1ff01000);
517 ath_local_write_config_rc2(0x24, 4, 0x1ff01000);
519 ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset
524 * Check if the WLAN PCI-E H/W is present, If the
525 * WLAN H/W is not present, skip the PCI platform
526 * initialization code and return
528 if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) {
529 prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");