tools/perf/pmu-events/arch/x86/skylake/memory.json

   1 [
   2     {
   3         "PublicDescription": "Number of times a TSX line had a cache conflict.",
   4         "EventCode": "0x54",
   5         "Counter": "0,1,2,3",
   6         "UMask": "0x1",
   7         "EventName": "TX_MEM.ABORT_CONFLICT",
   8         "SampleAfterValue": "2000003",
   9         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "EventCode": "0x54",
  14         "Counter": "0,1,2,3",
  15         "UMask": "0x2",
  16         "EventName": "TX_MEM.ABORT_CAPACITY",
  17         "SampleAfterValue": "2000003",
  18         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
  19         "CounterHTOff": "0,1,2,3,4,5,6,7"
  20     },
  21     {
  22         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
  23         "EventCode": "0x54",
  24         "Counter": "0,1,2,3",
  25         "UMask": "0x4",
  26         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
  27         "SampleAfterValue": "2000003",
  28         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
  29         "CounterHTOff": "0,1,2,3,4,5,6,7"
  30     },
  31     {
  32         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
  33         "EventCode": "0x54",
  34         "Counter": "0,1,2,3",
  35         "UMask": "0x8",
  36         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
  37         "SampleAfterValue": "2000003",
  38         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
  39         "CounterHTOff": "0,1,2,3,4,5,6,7"
  40     },
  41     {
  42         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
  43         "EventCode": "0x54",
  44         "Counter": "0,1,2,3",
  45         "UMask": "0x10",
  46         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
  47         "SampleAfterValue": "2000003",
  48         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
  49         "CounterHTOff": "0,1,2,3,4,5,6,7"
  50     },
  51     {
  52         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
  53         "EventCode": "0x54",
  54         "Counter": "0,1,2,3",
  55         "UMask": "0x20",
  56         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
  57         "SampleAfterValue": "2000003",
  58         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
  59         "CounterHTOff": "0,1,2,3,4,5,6,7"
  60     },
  61     {
  62         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
  63         "EventCode": "0x54",
  64         "Counter": "0,1,2,3",
  65         "UMask": "0x40",
  66         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
  67         "SampleAfterValue": "2000003",
  68         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
  69         "CounterHTOff": "0,1,2,3,4,5,6,7"
  70     },
  71     {
  72         "EventCode": "0x5d",
  73         "Counter": "0,1,2,3",
  74         "UMask": "0x1",
  75         "EventName": "TX_EXEC.MISC1",
  76         "SampleAfterValue": "2000003",
  77         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
  78         "CounterHTOff": "0,1,2,3,4,5,6,7"
  79     },
  80     {
  81         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
  82         "EventCode": "0x5d",
  83         "Counter": "0,1,2,3",
  84         "UMask": "0x2",
  85         "EventName": "TX_EXEC.MISC2",
  86         "SampleAfterValue": "2000003",
  87         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
  88         "CounterHTOff": "0,1,2,3,4,5,6,7"
  89     },
  90     {
  91         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
  92         "EventCode": "0x5d",
  93         "Counter": "0,1,2,3",
  94         "UMask": "0x4",
  95         "EventName": "TX_EXEC.MISC3",
  96         "SampleAfterValue": "2000003",
  97         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
  98         "CounterHTOff": "0,1,2,3,4,5,6,7"
  99     },
 100     {
 101         "PublicDescription": "RTM region detected inside HLE.",
 102         "EventCode": "0x5d",
 103         "Counter": "0,1,2,3",
 104         "UMask": "0x8",
 105         "EventName": "TX_EXEC.MISC4",
 106         "SampleAfterValue": "2000003",
 107         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
 108         "CounterHTOff": "0,1,2,3,4,5,6,7"
 109     },
 110     {
 111         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
 112         "EventCode": "0x5d",
 113         "Counter": "0,1,2,3",
 114         "UMask": "0x10",
 115         "EventName": "TX_EXEC.MISC5",
 116         "SampleAfterValue": "2000003",
 117         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
 118         "CounterHTOff": "0,1,2,3,4,5,6,7"
 119     },
 120     {
 121         "EventCode": "0x60",
 122         "Counter": "0,1,2,3",
 123         "UMask": "0x10",
 124         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
 125         "SampleAfterValue": "2000003",
 126         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
 127         "CounterHTOff": "0,1,2,3,4,5,6,7"
 128     },
 129     {
 130         "EventCode": "0x60",
 131         "Counter": "0,1,2,3",
 132         "UMask": "0x10",
 133         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
 134         "SampleAfterValue": "2000003",
 135         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
 136         "CounterMask": "1",
 137         "CounterHTOff": "0,1,2,3,4,5,6,7"
 138     },
 139     {
 140         "EventCode": "0x60",
 141         "Counter": "0,1,2,3",
 142         "UMask": "0x10",
 143         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
 144         "SampleAfterValue": "2000003",
 145         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
 146         "CounterMask": "6",
 147         "CounterHTOff": "0,1,2,3,4,5,6,7"
 148     },
 149     {
 150         "EventCode": "0xA3",
 151         "Counter": "0,1,2,3",
 152         "UMask": "0x2",
 153         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
 154         "SampleAfterValue": "2000003",
 155         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
 156         "CounterMask": "2",
 157         "CounterHTOff": "0,1,2,3,4,5,6,7"
 158     },
 159     {
 160         "EventCode": "0xA3",
 161         "Counter": "0,1,2,3",
 162         "UMask": "0x6",
 163         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
 164         "SampleAfterValue": "2000003",
 165         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
 166         "CounterMask": "6",
 167         "CounterHTOff": "0,1,2,3,4,5,6,7"
 168     },
 169     {
 170         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
 171         "EventCode": "0xB0",
 172         "Counter": "0,1,2,3",
 173         "UMask": "0x10",
 174         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
 175         "SampleAfterValue": "100003",
 176         "BriefDescription": "Demand Data Read requests who miss L3 cache",
 177         "CounterHTOff": "0,1,2,3,4,5,6,7"
 178     },
 179     {
 180         "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
 181         "EventCode": "0xC3",
 182         "Counter": "0,1,2,3",
 183         "UMask": "0x2",
 184         "Errata": "SKL089",
 185         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
 186         "SampleAfterValue": "100003",
 187         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
 188         "CounterHTOff": "0,1,2,3,4,5,6,7"
 189     },
 190     {
 191         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
 192         "EventCode": "0xC8",
 193         "Counter": "0,1,2,3",
 194         "UMask": "0x1",
 195         "EventName": "HLE_RETIRED.START",
 196         "SampleAfterValue": "2000003",
 197         "BriefDescription": "Number of times an HLE execution started.",
 198         "CounterHTOff": "0,1,2,3,4,5,6,7"
 199     },
 200     {
 201         "PublicDescription": "Number of times HLE commit succeeded.",
 202         "EventCode": "0xC8",
 203         "Counter": "0,1,2,3",
 204         "UMask": "0x2",
 205         "EventName": "HLE_RETIRED.COMMIT",
 206         "SampleAfterValue": "2000003",
 207         "BriefDescription": "Number of times an HLE execution successfully committed",
 208         "CounterHTOff": "0,1,2,3,4,5,6,7"
 209     },
 210     {
 211         "PEBS": "1",
 212         "PublicDescription": "Number of times HLE abort was triggered. (PEBS)",
 213         "EventCode": "0xC8",
 214         "Counter": "0,1,2,3",
 215         "UMask": "0x4",
 216         "EventName": "HLE_RETIRED.ABORTED",
 217         "SampleAfterValue": "2000003",
 218         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
 219         "CounterHTOff": "0,1,2,3,4,5,6,7"
 220     },
 221     {
 222         "EventCode": "0xC8",
 223         "Counter": "0,1,2,3",
 224         "UMask": "0x8",
 225         "EventName": "HLE_RETIRED.ABORTED_MEM",
 226         "SampleAfterValue": "2000003",
 227         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
 228         "CounterHTOff": "0,1,2,3,4,5,6,7"
 229     },
 230     {
 231         "EventCode": "0xC8",
 232         "Counter": "0,1,2,3",
 233         "UMask": "0x10",
 234         "EventName": "HLE_RETIRED.ABORTED_TIMER",
 235         "SampleAfterValue": "2000003",
 236         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
 237         "CounterHTOff": "0,1,2,3,4,5,6,7"
 238     },
 239     {
 240         "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
 241         "EventCode": "0xC8",
 242         "Counter": "0,1,2,3",
 243         "UMask": "0x20",
 244         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
 245         "SampleAfterValue": "2000003",
 246         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
 247         "CounterHTOff": "0,1,2,3,4,5,6,7"
 248     },
 249     {
 250         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
 251         "EventCode": "0xC8",
 252         "Counter": "0,1,2,3",
 253         "UMask": "0x40",
 254         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
 255         "SampleAfterValue": "2000003",
 256         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
 257         "CounterHTOff": "0,1,2,3,4,5,6,7"
 258     },
 259     {
 260         "EventCode": "0xC8",
 261         "Counter": "0,1,2,3",
 262         "UMask": "0x80",
 263         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
 264         "SampleAfterValue": "2000003",
 265         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
 266         "CounterHTOff": "0,1,2,3,4,5,6,7"
 267     },
 268     {
 269         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
 270         "EventCode": "0xC9",
 271         "Counter": "0,1,2,3",
 272         "UMask": "0x1",
 273         "EventName": "RTM_RETIRED.START",
 274         "SampleAfterValue": "2000003",
 275         "BriefDescription": "Number of times an RTM execution started.",
 276         "CounterHTOff": "0,1,2,3,4,5,6,7"
 277     },
 278     {
 279         "PublicDescription": "Number of times RTM commit succeeded.",
 280         "EventCode": "0xC9",
 281         "Counter": "0,1,2,3",
 282         "UMask": "0x2",
 283         "EventName": "RTM_RETIRED.COMMIT",
 284         "SampleAfterValue": "2000003",
 285         "BriefDescription": "Number of times an RTM execution successfully committed",
 286         "CounterHTOff": "0,1,2,3,4,5,6,7"
 287     },
 288     {
 289         "PEBS": "1",
 290         "PublicDescription": "Number of times RTM abort was triggered. (PEBS)",
 291         "EventCode": "0xC9",
 292         "Counter": "0,1,2,3",
 293         "UMask": "0x4",
 294         "EventName": "RTM_RETIRED.ABORTED",
 295         "SampleAfterValue": "2000003",
 296         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
 297         "CounterHTOff": "0,1,2,3,4,5,6,7"
 298     },
 299     {
 300         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
 301         "EventCode": "0xC9",
 302         "Counter": "0,1,2,3",
 303         "UMask": "0x8",
 304         "EventName": "RTM_RETIRED.ABORTED_MEM",
 305         "SampleAfterValue": "2000003",
 306         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
 307         "CounterHTOff": "0,1,2,3,4,5,6,7"
 308     },
 309     {
 310         "EventCode": "0xC9",
 311         "Counter": "0,1,2,3",
 312         "UMask": "0x10",
 313         "EventName": "RTM_RETIRED.ABORTED_TIMER",
 314         "SampleAfterValue": "2000003",
 315         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
 316         "CounterHTOff": "0,1,2,3,4,5,6,7"
 317     },
 318     {
 319         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
 320         "EventCode": "0xC9",
 321         "Counter": "0,1,2,3",
 322         "UMask": "0x20",
 323         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
 324         "SampleAfterValue": "2000003",
 325         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
 326         "CounterHTOff": "0,1,2,3,4,5,6,7"
 327     },
 328     {
 329         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
 330         "EventCode": "0xC9",
 331         "Counter": "0,1,2,3",
 332         "UMask": "0x40",
 333         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
 334         "SampleAfterValue": "2000003",
 335         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
 336         "CounterHTOff": "0,1,2,3,4,5,6,7"
 337     },
 338     {
 339         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
 340         "EventCode": "0xC9",
 341         "Counter": "0,1,2,3",
 342         "UMask": "0x80",
 343         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
 344         "SampleAfterValue": "2000003",
 345         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
 346         "CounterHTOff": "0,1,2,3,4,5,6,7"
 347     },
 348     {
 349         "PEBS": "2",
 350         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
 351         "EventCode": "0xCD",
 352         "MSRValue": "0x4",
 353         "Counter": "0,1,2,3",
 354         "UMask": "0x1",
 355         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 356         "MSRIndex": "0x3F6",
 357         "SampleAfterValue": "100003",
 358         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
 359         "TakenAlone": "1",
 360         "CounterHTOff": "0,1,2,3"
 361     },
 362     {
 363         "PEBS": "2",
 364         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
 365         "EventCode": "0xCD",
 366         "MSRValue": "0x8",
 367         "Counter": "0,1,2,3",
 368         "UMask": "0x1",
 369         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 370         "MSRIndex": "0x3F6",
 371         "SampleAfterValue": "50021",
 372         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
 373         "TakenAlone": "1",
 374         "CounterHTOff": "0,1,2,3"
 375     },
 376     {
 377         "PEBS": "2",
 378         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
 379         "EventCode": "0xCD",
 380         "MSRValue": "0x10",
 381         "Counter": "0,1,2,3",
 382         "UMask": "0x1",
 383         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 384         "MSRIndex": "0x3F6",
 385         "SampleAfterValue": "20011",
 386         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
 387         "TakenAlone": "1",
 388         "CounterHTOff": "0,1,2,3"
 389     },
 390     {
 391         "PEBS": "2",
 392         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
 393         "EventCode": "0xCD",
 394         "MSRValue": "0x20",
 395         "Counter": "0,1,2,3",
 396         "UMask": "0x1",
 397         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 398         "MSRIndex": "0x3F6",
 399         "SampleAfterValue": "100007",
 400         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
 401         "TakenAlone": "1",
 402         "CounterHTOff": "0,1,2,3"
 403     },
 404     {
 405         "PEBS": "2",
 406         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
 407         "EventCode": "0xCD",
 408         "MSRValue": "0x40",
 409         "Counter": "0,1,2,3",
 410         "UMask": "0x1",
 411         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 412         "MSRIndex": "0x3F6",
 413         "SampleAfterValue": "2003",
 414         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
 415         "TakenAlone": "1",
 416         "CounterHTOff": "0,1,2,3"
 417     },
 418     {
 419         "PEBS": "2",
 420         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
 421         "EventCode": "0xCD",
 422         "MSRValue": "0x80",
 423         "Counter": "0,1,2,3",
 424         "UMask": "0x1",
 425         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 426         "MSRIndex": "0x3F6",
 427         "SampleAfterValue": "1009",
 428         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
 429         "TakenAlone": "1",
 430         "CounterHTOff": "0,1,2,3"
 431     },
 432     {
 433         "PEBS": "2",
 434         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
 435         "EventCode": "0xCD",
 436         "MSRValue": "0x100",
 437         "Counter": "0,1,2,3",
 438         "UMask": "0x1",
 439         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 440         "MSRIndex": "0x3F6",
 441         "SampleAfterValue": "503",
 442         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
 443         "TakenAlone": "1",
 444         "CounterHTOff": "0,1,2,3"
 445     },
 446     {
 447         "PEBS": "2",
 448         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
 449         "EventCode": "0xCD",
 450         "MSRValue": "0x200",
 451         "Counter": "0,1,2,3",
 452         "UMask": "0x1",
 453         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 454         "MSRIndex": "0x3F6",
 455         "SampleAfterValue": "101",
 456         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
 457         "TakenAlone": "1",
 458         "CounterHTOff": "0,1,2,3"
 459     },
 460     {
 461         "PublicDescription": "Counts any other requests",
 462         "EventCode": "0xB7, 0xBB",
 463         "MSRValue": "0x3FFC408000",
 464         "Counter": "0,1,2,3",
 465         "UMask": "0x1",
 466         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
 467         "MSRIndex": "0x1a6, 0x1a7",
 468         "SampleAfterValue": "100003",
 469         "BriefDescription": "Counts any other requests",
 470         "Offcore": "1",
 471         "CounterHTOff": "0,1,2,3"
 472     },
 473     {
 474         "PublicDescription": "Counts any other requests",
 475         "EventCode": "0xB7, 0xBB",
 476         "MSRValue": "0x203C408000",
 477         "Counter": "0,1,2,3",
 478         "UMask": "0x1",
 479         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
 480         "MSRIndex": "0x1a6, 0x1a7",
 481         "SampleAfterValue": "100003",
 482         "BriefDescription": "Counts any other requests",
 483         "Offcore": "1",
 484         "CounterHTOff": "0,1,2,3"
 485     },
 486     {
 487         "PublicDescription": "Counts any other requests",
 488         "EventCode": "0xB7, 0xBB",
 489         "MSRValue": "0x103C408000",
 490         "Counter": "0,1,2,3",
 491         "UMask": "0x1",
 492         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
 493         "MSRIndex": "0x1a6, 0x1a7",
 494         "SampleAfterValue": "100003",
 495         "BriefDescription": "Counts any other requests",
 496         "Offcore": "1",
 497         "CounterHTOff": "0,1,2,3"
 498     },
 499     {
 500         "PublicDescription": "Counts any other requests",
 501         "EventCode": "0xB7, 0xBB",
 502         "MSRValue": "0x043C408000",
 503         "Counter": "0,1,2,3",
 504         "UMask": "0x1",
 505         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
 506         "MSRIndex": "0x1a6, 0x1a7",
 507         "SampleAfterValue": "100003",
 508         "BriefDescription": "Counts any other requests",
 509         "Offcore": "1",
 510         "CounterHTOff": "0,1,2,3"
 511     },
 512     {
 513         "PublicDescription": "Counts any other requests",
 514         "EventCode": "0xB7, 0xBB",
 515         "MSRValue": "0x023C408000",
 516         "Counter": "0,1,2,3",
 517         "UMask": "0x1",
 518         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
 519         "MSRIndex": "0x1a6, 0x1a7",
 520         "SampleAfterValue": "100003",
 521         "BriefDescription": "Counts any other requests",
 522         "Offcore": "1",
 523         "CounterHTOff": "0,1,2,3"
 524     },
 525     {
 526         "PublicDescription": "Counts any other requests",
 527         "EventCode": "0xB7, 0xBB",
 528         "MSRValue": "0x013C408000",
 529         "Counter": "0,1,2,3",
 530         "UMask": "0x1",
 531         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
 532         "MSRIndex": "0x1a6, 0x1a7",
 533         "SampleAfterValue": "100003",
 534         "BriefDescription": "Counts any other requests",
 535         "Offcore": "1",
 536         "CounterHTOff": "0,1,2,3"
 537     },
 538     {
 539         "PublicDescription": "Counts any other requests",
 540         "EventCode": "0xB7, 0xBB",
 541         "MSRValue": "0x00BC408000",
 542         "Counter": "0,1,2,3",
 543         "UMask": "0x1",
 544         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
 545         "MSRIndex": "0x1a6, 0x1a7",
 546         "SampleAfterValue": "100003",
 547         "BriefDescription": "Counts any other requests",
 548         "Offcore": "1",
 549         "CounterHTOff": "0,1,2,3"
 550     },
 551     {
 552         "PublicDescription": "Counts any other requests",
 553         "EventCode": "0xB7, 0xBB",
 554         "MSRValue": "0x007C408000",
 555         "Counter": "0,1,2,3",
 556         "UMask": "0x1",
 557         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
 558         "MSRIndex": "0x1a6, 0x1a7",
 559         "SampleAfterValue": "100003",
 560         "BriefDescription": "Counts any other requests",
 561         "Offcore": "1",
 562         "CounterHTOff": "0,1,2,3"
 563     },
 564     {
 565         "PublicDescription": "Counts any other requests",
 566         "EventCode": "0xB7, 0xBB",
 567         "MSRValue": "0x3FC4008000",
 568         "Counter": "0,1,2,3",
 569         "UMask": "0x1",
 570         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 571         "MSRIndex": "0x1a6, 0x1a7",
 572         "SampleAfterValue": "100003",
 573         "BriefDescription": "Counts any other requests",
 574         "Offcore": "1",
 575         "CounterHTOff": "0,1,2,3"
 576     },
 577     {
 578         "PublicDescription": "Counts any other requests",
 579         "EventCode": "0xB7, 0xBB",
 580         "MSRValue": "0x2004008000",
 581         "Counter": "0,1,2,3",
 582         "UMask": "0x1",
 583         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 584         "MSRIndex": "0x1a6, 0x1a7",
 585         "SampleAfterValue": "100003",
 586         "BriefDescription": "Counts any other requests",
 587         "Offcore": "1",
 588         "CounterHTOff": "0,1,2,3"
 589     },
 590     {
 591         "PublicDescription": "Counts any other requests",
 592         "EventCode": "0xB7, 0xBB",
 593         "MSRValue": "0x1004008000",
 594         "Counter": "0,1,2,3",
 595         "UMask": "0x1",
 596         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 597         "MSRIndex": "0x1a6, 0x1a7",
 598         "SampleAfterValue": "100003",
 599         "BriefDescription": "Counts any other requests",
 600         "Offcore": "1",
 601         "CounterHTOff": "0,1,2,3"
 602     },
 603     {
 604         "PublicDescription": "Counts any other requests",
 605         "EventCode": "0xB7, 0xBB",
 606         "MSRValue": "0x0404008000",
 607         "Counter": "0,1,2,3",
 608         "UMask": "0x1",
 609         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 610         "MSRIndex": "0x1a6, 0x1a7",
 611         "SampleAfterValue": "100003",
 612         "BriefDescription": "Counts any other requests",
 613         "Offcore": "1",
 614         "CounterHTOff": "0,1,2,3"
 615     },
 616     {
 617         "PublicDescription": "Counts any other requests",
 618         "EventCode": "0xB7, 0xBB",
 619         "MSRValue": "0x0204008000",
 620         "Counter": "0,1,2,3",
 621         "UMask": "0x1",
 622         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 623         "MSRIndex": "0x1a6, 0x1a7",
 624         "SampleAfterValue": "100003",
 625         "BriefDescription": "Counts any other requests",
 626         "Offcore": "1",
 627         "CounterHTOff": "0,1,2,3"
 628     },
 629     {
 630         "PublicDescription": "Counts any other requests",
 631         "EventCode": "0xB7, 0xBB",
 632         "MSRValue": "0x0104008000",
 633         "Counter": "0,1,2,3",
 634         "UMask": "0x1",
 635         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 636         "MSRIndex": "0x1a6, 0x1a7",
 637         "SampleAfterValue": "100003",
 638         "BriefDescription": "Counts any other requests",
 639         "Offcore": "1",
 640         "CounterHTOff": "0,1,2,3"
 641     },
 642     {
 643         "PublicDescription": "Counts any other requests",
 644         "EventCode": "0xB7, 0xBB",
 645         "MSRValue": "0x0084008000",
 646         "Counter": "0,1,2,3",
 647         "UMask": "0x1",
 648         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 649         "MSRIndex": "0x1a6, 0x1a7",
 650         "SampleAfterValue": "100003",
 651         "BriefDescription": "Counts any other requests",
 652         "Offcore": "1",
 653         "CounterHTOff": "0,1,2,3"
 654     },
 655     {
 656         "PublicDescription": "Counts any other requests",
 657         "EventCode": "0xB7, 0xBB",
 658         "MSRValue": "0x0044008000",
 659         "Counter": "0,1,2,3",
 660         "UMask": "0x1",
 661         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
 662         "MSRIndex": "0x1a6, 0x1a7",
 663         "SampleAfterValue": "100003",
 664         "BriefDescription": "Counts any other requests",
 665         "Offcore": "1",
 666         "CounterHTOff": "0,1,2,3"
 667     },
 668     {
 669         "PublicDescription": "Counts any other requests",
 670         "EventCode": "0xB7, 0xBB",
 671         "MSRValue": "0x2000408000",
 672         "Counter": "0,1,2,3",
 673         "UMask": "0x1",
 674         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 675         "MSRIndex": "0x1a6, 0x1a7",
 676         "SampleAfterValue": "100003",
 677         "BriefDescription": "Counts any other requests",
 678         "Offcore": "1",
 679         "CounterHTOff": "0,1,2,3"
 680     },
 681     {
 682         "PublicDescription": "Counts any other requests",
 683         "EventCode": "0xB7, 0xBB",
 684         "MSRValue": "0x20001C8000",
 685         "Counter": "0,1,2,3",
 686         "UMask": "0x1",
 687         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
 688         "MSRIndex": "0x1a6, 0x1a7",
 689         "SampleAfterValue": "100003",
 690         "BriefDescription": "Counts any other requests",
 691         "Offcore": "1",
 692         "CounterHTOff": "0,1,2,3"
 693     },
 694     {
 695         "PublicDescription": "Counts any other requests",
 696         "EventCode": "0xB7, 0xBB",
 697         "MSRValue": "0x2000108000",
 698         "Counter": "0,1,2,3",
 699         "UMask": "0x1",
 700         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
 701         "MSRIndex": "0x1a6, 0x1a7",
 702         "SampleAfterValue": "100003",
 703         "BriefDescription": "Counts any other requests",
 704         "Offcore": "1",
 705         "CounterHTOff": "0,1,2,3"
 706     },
 707     {
 708         "PublicDescription": "Counts any other requests",
 709         "EventCode": "0xB7, 0xBB",
 710         "MSRValue": "0x2000088000",
 711         "Counter": "0,1,2,3",
 712         "UMask": "0x1",
 713         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
 714         "MSRIndex": "0x1a6, 0x1a7",
 715         "SampleAfterValue": "100003",
 716         "BriefDescription": "Counts any other requests",
 717         "Offcore": "1",
 718         "CounterHTOff": "0,1,2,3"
 719     },
 720     {
 721         "PublicDescription": "Counts any other requests",
 722         "EventCode": "0xB7, 0xBB",
 723         "MSRValue": "0x2000048000",
 724         "Counter": "0,1,2,3",
 725         "UMask": "0x1",
 726         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
 727         "MSRIndex": "0x1a6, 0x1a7",
 728         "SampleAfterValue": "100003",
 729         "BriefDescription": "Counts any other requests",
 730         "Offcore": "1",
 731         "CounterHTOff": "0,1,2,3"
 732     },
 733     {
 734         "PublicDescription": "Counts any other requests",
 735         "EventCode": "0xB7, 0xBB",
 736         "MSRValue": "0x2000028000",
 737         "Counter": "0,1,2,3",
 738         "UMask": "0x1",
 739         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
 740         "MSRIndex": "0x1a6, 0x1a7",
 741         "SampleAfterValue": "100003",
 742         "BriefDescription": "Counts any other requests",
 743         "Offcore": "1",
 744         "CounterHTOff": "0,1,2,3"
 745     },
 746     {
 747         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 748         "EventCode": "0xB7, 0xBB",
 749         "MSRValue": "0x3FFC400004",
 750         "Counter": "0,1,2,3",
 751         "UMask": "0x1",
 752         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
 753         "MSRIndex": "0x1a6, 0x1a7",
 754         "SampleAfterValue": "100003",
 755         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 756         "Offcore": "1",
 757         "CounterHTOff": "0,1,2,3"
 758     },
 759     {
 760         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 761         "EventCode": "0xB7, 0xBB",
 762         "MSRValue": "0x203C400004",
 763         "Counter": "0,1,2,3",
 764         "UMask": "0x1",
 765         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
 766         "MSRIndex": "0x1a6, 0x1a7",
 767         "SampleAfterValue": "100003",
 768         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 769         "Offcore": "1",
 770         "CounterHTOff": "0,1,2,3"
 771     },
 772     {
 773         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 774         "EventCode": "0xB7, 0xBB",
 775         "MSRValue": "0x103C400004",
 776         "Counter": "0,1,2,3",
 777         "UMask": "0x1",
 778         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
 779         "MSRIndex": "0x1a6, 0x1a7",
 780         "SampleAfterValue": "100003",
 781         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 782         "Offcore": "1",
 783         "CounterHTOff": "0,1,2,3"
 784     },
 785     {
 786         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 787         "EventCode": "0xB7, 0xBB",
 788         "MSRValue": "0x043C400004",
 789         "Counter": "0,1,2,3",
 790         "UMask": "0x1",
 791         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
 792         "MSRIndex": "0x1a6, 0x1a7",
 793         "SampleAfterValue": "100003",
 794         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 795         "Offcore": "1",
 796         "CounterHTOff": "0,1,2,3"
 797     },
 798     {
 799         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 800         "EventCode": "0xB7, 0xBB",
 801         "MSRValue": "0x023C400004",
 802         "Counter": "0,1,2,3",
 803         "UMask": "0x1",
 804         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
 805         "MSRIndex": "0x1a6, 0x1a7",
 806         "SampleAfterValue": "100003",
 807         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 808         "Offcore": "1",
 809         "CounterHTOff": "0,1,2,3"
 810     },
 811     {
 812         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 813         "EventCode": "0xB7, 0xBB",
 814         "MSRValue": "0x013C400004",
 815         "Counter": "0,1,2,3",
 816         "UMask": "0x1",
 817         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
 818         "MSRIndex": "0x1a6, 0x1a7",
 819         "SampleAfterValue": "100003",
 820         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 821         "Offcore": "1",
 822         "CounterHTOff": "0,1,2,3"
 823     },
 824     {
 825         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 826         "EventCode": "0xB7, 0xBB",
 827         "MSRValue": "0x00BC400004",
 828         "Counter": "0,1,2,3",
 829         "UMask": "0x1",
 830         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
 831         "MSRIndex": "0x1a6, 0x1a7",
 832         "SampleAfterValue": "100003",
 833         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 834         "Offcore": "1",
 835         "CounterHTOff": "0,1,2,3"
 836     },
 837     {
 838         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 839         "EventCode": "0xB7, 0xBB",
 840         "MSRValue": "0x007C400004",
 841         "Counter": "0,1,2,3",
 842         "UMask": "0x1",
 843         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
 844         "MSRIndex": "0x1a6, 0x1a7",
 845         "SampleAfterValue": "100003",
 846         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 847         "Offcore": "1",
 848         "CounterHTOff": "0,1,2,3"
 849     },
 850     {
 851         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 852         "EventCode": "0xB7, 0xBB",
 853         "MSRValue": "0x3FC4000004",
 854         "Counter": "0,1,2,3",
 855         "UMask": "0x1",
 856         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 857         "MSRIndex": "0x1a6, 0x1a7",
 858         "SampleAfterValue": "100003",
 859         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 860         "Offcore": "1",
 861         "CounterHTOff": "0,1,2,3"
 862     },
 863     {
 864         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 865         "EventCode": "0xB7, 0xBB",
 866         "MSRValue": "0x2004000004",
 867         "Counter": "0,1,2,3",
 868         "UMask": "0x1",
 869         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 870         "MSRIndex": "0x1a6, 0x1a7",
 871         "SampleAfterValue": "100003",
 872         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 873         "Offcore": "1",
 874         "CounterHTOff": "0,1,2,3"
 875     },
 876     {
 877         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 878         "EventCode": "0xB7, 0xBB",
 879         "MSRValue": "0x1004000004",
 880         "Counter": "0,1,2,3",
 881         "UMask": "0x1",
 882         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 883         "MSRIndex": "0x1a6, 0x1a7",
 884         "SampleAfterValue": "100003",
 885         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 886         "Offcore": "1",
 887         "CounterHTOff": "0,1,2,3"
 888     },
 889     {
 890         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 891         "EventCode": "0xB7, 0xBB",
 892         "MSRValue": "0x0404000004",
 893         "Counter": "0,1,2,3",
 894         "UMask": "0x1",
 895         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 896         "MSRIndex": "0x1a6, 0x1a7",
 897         "SampleAfterValue": "100003",
 898         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 899         "Offcore": "1",
 900         "CounterHTOff": "0,1,2,3"
 901     },
 902     {
 903         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 904         "EventCode": "0xB7, 0xBB",
 905         "MSRValue": "0x0204000004",
 906         "Counter": "0,1,2,3",
 907         "UMask": "0x1",
 908         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 909         "MSRIndex": "0x1a6, 0x1a7",
 910         "SampleAfterValue": "100003",
 911         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 912         "Offcore": "1",
 913         "CounterHTOff": "0,1,2,3"
 914     },
 915     {
 916         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 917         "EventCode": "0xB7, 0xBB",
 918         "MSRValue": "0x0104000004",
 919         "Counter": "0,1,2,3",
 920         "UMask": "0x1",
 921         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 922         "MSRIndex": "0x1a6, 0x1a7",
 923         "SampleAfterValue": "100003",
 924         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 925         "Offcore": "1",
 926         "CounterHTOff": "0,1,2,3"
 927     },
 928     {
 929         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 930         "EventCode": "0xB7, 0xBB",
 931         "MSRValue": "0x0084000004",
 932         "Counter": "0,1,2,3",
 933         "UMask": "0x1",
 934         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 935         "MSRIndex": "0x1a6, 0x1a7",
 936         "SampleAfterValue": "100003",
 937         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 938         "Offcore": "1",
 939         "CounterHTOff": "0,1,2,3"
 940     },
 941     {
 942         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 943         "EventCode": "0xB7, 0xBB",
 944         "MSRValue": "0x0044000004",
 945         "Counter": "0,1,2,3",
 946         "UMask": "0x1",
 947         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
 948         "MSRIndex": "0x1a6, 0x1a7",
 949         "SampleAfterValue": "100003",
 950         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 951         "Offcore": "1",
 952         "CounterHTOff": "0,1,2,3"
 953     },
 954     {
 955         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 956         "EventCode": "0xB7, 0xBB",
 957         "MSRValue": "0x2000400004",
 958         "Counter": "0,1,2,3",
 959         "UMask": "0x1",
 960         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 961         "MSRIndex": "0x1a6, 0x1a7",
 962         "SampleAfterValue": "100003",
 963         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 964         "Offcore": "1",
 965         "CounterHTOff": "0,1,2,3"
 966     },
 967     {
 968         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 969         "EventCode": "0xB7, 0xBB",
 970         "MSRValue": "0x20001C0004",
 971         "Counter": "0,1,2,3",
 972         "UMask": "0x1",
 973         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
 974         "MSRIndex": "0x1a6, 0x1a7",
 975         "SampleAfterValue": "100003",
 976         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 977         "Offcore": "1",
 978         "CounterHTOff": "0,1,2,3"
 979     },
 980     {
 981         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 982         "EventCode": "0xB7, 0xBB",
 983         "MSRValue": "0x2000100004",
 984         "Counter": "0,1,2,3",
 985         "UMask": "0x1",
 986         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
 987         "MSRIndex": "0x1a6, 0x1a7",
 988         "SampleAfterValue": "100003",
 989         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 990         "Offcore": "1",
 991         "CounterHTOff": "0,1,2,3"
 992     },
 993     {
 994         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
 995         "EventCode": "0xB7, 0xBB",
 996         "MSRValue": "0x2000080004",
 997         "Counter": "0,1,2,3",
 998         "UMask": "0x1",
 999         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
1000         "MSRIndex": "0x1a6, 0x1a7",
1001         "SampleAfterValue": "100003",
1002         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
1003         "Offcore": "1",
1004         "CounterHTOff": "0,1,2,3"
1005     },
1006     {
1007         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
1008         "EventCode": "0xB7, 0xBB",
1009         "MSRValue": "0x2000040004",
1010         "Counter": "0,1,2,3",
1011         "UMask": "0x1",
1012         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
1013         "MSRIndex": "0x1a6, 0x1a7",
1014         "SampleAfterValue": "100003",
1015         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
1016         "Offcore": "1",
1017         "CounterHTOff": "0,1,2,3"
1018     },
1019     {
1020         "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
1021         "EventCode": "0xB7, 0xBB",
1022         "MSRValue": "0x2000020004",
1023         "Counter": "0,1,2,3",
1024         "UMask": "0x1",
1025         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1026         "MSRIndex": "0x1a6, 0x1a7",
1027         "SampleAfterValue": "100003",
1028         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
1029         "Offcore": "1",
1030         "CounterHTOff": "0,1,2,3"
1031     },
1032     {
1033         "PublicDescription": "Counts all demand data writes (RFOs)",
1034         "EventCode": "0xB7, 0xBB",
1035         "MSRValue": "0x3FFC400002",
1036         "Counter": "0,1,2,3",
1037         "UMask": "0x1",
1038         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
1039         "MSRIndex": "0x1a6, 0x1a7",
1040         "SampleAfterValue": "100003",
1041         "BriefDescription": "Counts all demand data writes (RFOs)",
1042         "Offcore": "1",
1043         "CounterHTOff": "0,1,2,3"
1044     },
1045     {
1046         "PublicDescription": "Counts all demand data writes (RFOs)",
1047         "EventCode": "0xB7, 0xBB",
1048         "MSRValue": "0x203C400002",
1049         "Counter": "0,1,2,3",
1050         "UMask": "0x1",
1051         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
1052         "MSRIndex": "0x1a6, 0x1a7",
1053         "SampleAfterValue": "100003",
1054         "BriefDescription": "Counts all demand data writes (RFOs)",
1055         "Offcore": "1",
1056         "CounterHTOff": "0,1,2,3"
1057     },
1058     {
1059         "PublicDescription": "Counts all demand data writes (RFOs)",
1060         "EventCode": "0xB7, 0xBB",
1061         "MSRValue": "0x103C400002",
1062         "Counter": "0,1,2,3",
1063         "UMask": "0x1",
1064         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
1065         "MSRIndex": "0x1a6, 0x1a7",
1066         "SampleAfterValue": "100003",
1067         "BriefDescription": "Counts all demand data writes (RFOs)",
1068         "Offcore": "1",
1069         "CounterHTOff": "0,1,2,3"
1070     },
1071     {
1072         "PublicDescription": "Counts all demand data writes (RFOs)",
1073         "EventCode": "0xB7, 0xBB",
1074         "MSRValue": "0x043C400002",
1075         "Counter": "0,1,2,3",
1076         "UMask": "0x1",
1077         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
1078         "MSRIndex": "0x1a6, 0x1a7",
1079         "SampleAfterValue": "100003",
1080         "BriefDescription": "Counts all demand data writes (RFOs)",
1081         "Offcore": "1",
1082         "CounterHTOff": "0,1,2,3"
1083     },
1084     {
1085         "PublicDescription": "Counts all demand data writes (RFOs)",
1086         "EventCode": "0xB7, 0xBB",
1087         "MSRValue": "0x023C400002",
1088         "Counter": "0,1,2,3",
1089         "UMask": "0x1",
1090         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
1091         "MSRIndex": "0x1a6, 0x1a7",
1092         "SampleAfterValue": "100003",
1093         "BriefDescription": "Counts all demand data writes (RFOs)",
1094         "Offcore": "1",
1095         "CounterHTOff": "0,1,2,3"
1096     },
1097     {
1098         "PublicDescription": "Counts all demand data writes (RFOs)",
1099         "EventCode": "0xB7, 0xBB",
1100         "MSRValue": "0x013C400002",
1101         "Counter": "0,1,2,3",
1102         "UMask": "0x1",
1103         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
1104         "MSRIndex": "0x1a6, 0x1a7",
1105         "SampleAfterValue": "100003",
1106         "BriefDescription": "Counts all demand data writes (RFOs)",
1107         "Offcore": "1",
1108         "CounterHTOff": "0,1,2,3"
1109     },
1110     {
1111         "PublicDescription": "Counts all demand data writes (RFOs)",
1112         "EventCode": "0xB7, 0xBB",
1113         "MSRValue": "0x00BC400002",
1114         "Counter": "0,1,2,3",
1115         "UMask": "0x1",
1116         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
1117         "MSRIndex": "0x1a6, 0x1a7",
1118         "SampleAfterValue": "100003",
1119         "BriefDescription": "Counts all demand data writes (RFOs)",
1120         "Offcore": "1",
1121         "CounterHTOff": "0,1,2,3"
1122     },
1123     {
1124         "PublicDescription": "Counts all demand data writes (RFOs)",
1125         "EventCode": "0xB7, 0xBB",
1126         "MSRValue": "0x007C400002",
1127         "Counter": "0,1,2,3",
1128         "UMask": "0x1",
1129         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
1130         "MSRIndex": "0x1a6, 0x1a7",
1131         "SampleAfterValue": "100003",
1132         "BriefDescription": "Counts all demand data writes (RFOs)",
1133         "Offcore": "1",
1134         "CounterHTOff": "0,1,2,3"
1135     },
1136     {
1137         "PublicDescription": "Counts all demand data writes (RFOs)",
1138         "EventCode": "0xB7, 0xBB",
1139         "MSRValue": "0x3FC4000002",
1140         "Counter": "0,1,2,3",
1141         "UMask": "0x1",
1142         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1143         "MSRIndex": "0x1a6, 0x1a7",
1144         "SampleAfterValue": "100003",
1145         "BriefDescription": "Counts all demand data writes (RFOs)",
1146         "Offcore": "1",
1147         "CounterHTOff": "0,1,2,3"
1148     },
1149     {
1150         "PublicDescription": "Counts all demand data writes (RFOs)",
1151         "EventCode": "0xB7, 0xBB",
1152         "MSRValue": "0x2004000002",
1153         "Counter": "0,1,2,3",
1154         "UMask": "0x1",
1155         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1156         "MSRIndex": "0x1a6, 0x1a7",
1157         "SampleAfterValue": "100003",
1158         "BriefDescription": "Counts all demand data writes (RFOs)",
1159         "Offcore": "1",
1160         "CounterHTOff": "0,1,2,3"
1161     },
1162     {
1163         "PublicDescription": "Counts all demand data writes (RFOs)",
1164         "EventCode": "0xB7, 0xBB",
1165         "MSRValue": "0x1004000002",
1166         "Counter": "0,1,2,3",
1167         "UMask": "0x1",
1168         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1169         "MSRIndex": "0x1a6, 0x1a7",
1170         "SampleAfterValue": "100003",
1171         "BriefDescription": "Counts all demand data writes (RFOs)",
1172         "Offcore": "1",
1173         "CounterHTOff": "0,1,2,3"
1174     },
1175     {
1176         "PublicDescription": "Counts all demand data writes (RFOs)",
1177         "EventCode": "0xB7, 0xBB",
1178         "MSRValue": "0x0404000002",
1179         "Counter": "0,1,2,3",
1180         "UMask": "0x1",
1181         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1182         "MSRIndex": "0x1a6, 0x1a7",
1183         "SampleAfterValue": "100003",
1184         "BriefDescription": "Counts all demand data writes (RFOs)",
1185         "Offcore": "1",
1186         "CounterHTOff": "0,1,2,3"
1187     },
1188     {
1189         "PublicDescription": "Counts all demand data writes (RFOs)",
1190         "EventCode": "0xB7, 0xBB",
1191         "MSRValue": "0x0204000002",
1192         "Counter": "0,1,2,3",
1193         "UMask": "0x1",
1194         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1195         "MSRIndex": "0x1a6, 0x1a7",
1196         "SampleAfterValue": "100003",
1197         "BriefDescription": "Counts all demand data writes (RFOs)",
1198         "Offcore": "1",
1199         "CounterHTOff": "0,1,2,3"
1200     },
1201     {
1202         "PublicDescription": "Counts all demand data writes (RFOs)",
1203         "EventCode": "0xB7, 0xBB",
1204         "MSRValue": "0x0104000002",
1205         "Counter": "0,1,2,3",
1206         "UMask": "0x1",
1207         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1208         "MSRIndex": "0x1a6, 0x1a7",
1209         "SampleAfterValue": "100003",
1210         "BriefDescription": "Counts all demand data writes (RFOs)",
1211         "Offcore": "1",
1212         "CounterHTOff": "0,1,2,3"
1213     },
1214     {
1215         "PublicDescription": "Counts all demand data writes (RFOs)",
1216         "EventCode": "0xB7, 0xBB",
1217         "MSRValue": "0x0084000002",
1218         "Counter": "0,1,2,3",
1219         "UMask": "0x1",
1220         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1221         "MSRIndex": "0x1a6, 0x1a7",
1222         "SampleAfterValue": "100003",
1223         "BriefDescription": "Counts all demand data writes (RFOs)",
1224         "Offcore": "1",
1225         "CounterHTOff": "0,1,2,3"
1226     },
1227     {
1228         "PublicDescription": "Counts all demand data writes (RFOs)",
1229         "EventCode": "0xB7, 0xBB",
1230         "MSRValue": "0x0044000002",
1231         "Counter": "0,1,2,3",
1232         "UMask": "0x1",
1233         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
1234         "MSRIndex": "0x1a6, 0x1a7",
1235         "SampleAfterValue": "100003",
1236         "BriefDescription": "Counts all demand data writes (RFOs)",
1237         "Offcore": "1",
1238         "CounterHTOff": "0,1,2,3"
1239     },
1240     {
1241         "PublicDescription": "Counts all demand data writes (RFOs)",
1242         "EventCode": "0xB7, 0xBB",
1243         "MSRValue": "0x2000400002",
1244         "Counter": "0,1,2,3",
1245         "UMask": "0x1",
1246         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
1247         "MSRIndex": "0x1a6, 0x1a7",
1248         "SampleAfterValue": "100003",
1249         "BriefDescription": "Counts all demand data writes (RFOs)",
1250         "Offcore": "1",
1251         "CounterHTOff": "0,1,2,3"
1252     },
1253     {
1254         "PublicDescription": "Counts all demand data writes (RFOs)",
1255         "EventCode": "0xB7, 0xBB",
1256         "MSRValue": "0x20001C0002",
1257         "Counter": "0,1,2,3",
1258         "UMask": "0x1",
1259         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
1260         "MSRIndex": "0x1a6, 0x1a7",
1261         "SampleAfterValue": "100003",
1262         "BriefDescription": "Counts all demand data writes (RFOs)",
1263         "Offcore": "1",
1264         "CounterHTOff": "0,1,2,3"
1265     },
1266     {
1267         "PublicDescription": "Counts all demand data writes (RFOs)",
1268         "EventCode": "0xB7, 0xBB",
1269         "MSRValue": "0x2000100002",
1270         "Counter": "0,1,2,3",
1271         "UMask": "0x1",
1272         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
1273         "MSRIndex": "0x1a6, 0x1a7",
1274         "SampleAfterValue": "100003",
1275         "BriefDescription": "Counts all demand data writes (RFOs)",
1276         "Offcore": "1",
1277         "CounterHTOff": "0,1,2,3"
1278     },
1279     {
1280         "PublicDescription": "Counts all demand data writes (RFOs)",
1281         "EventCode": "0xB7, 0xBB",
1282         "MSRValue": "0x2000080002",
1283         "Counter": "0,1,2,3",
1284         "UMask": "0x1",
1285         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
1286         "MSRIndex": "0x1a6, 0x1a7",
1287         "SampleAfterValue": "100003",
1288         "BriefDescription": "Counts all demand data writes (RFOs)",
1289         "Offcore": "1",
1290         "CounterHTOff": "0,1,2,3"
1291     },
1292     {
1293         "PublicDescription": "Counts all demand data writes (RFOs)",
1294         "EventCode": "0xB7, 0xBB",
1295         "MSRValue": "0x2000040002",
1296         "Counter": "0,1,2,3",
1297         "UMask": "0x1",
1298         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
1299         "MSRIndex": "0x1a6, 0x1a7",
1300         "SampleAfterValue": "100003",
1301         "BriefDescription": "Counts all demand data writes (RFOs)",
1302         "Offcore": "1",
1303         "CounterHTOff": "0,1,2,3"
1304     },
1305     {
1306         "PublicDescription": "Counts all demand data writes (RFOs)",
1307         "EventCode": "0xB7, 0xBB",
1308         "MSRValue": "0x2000020002",
1309         "Counter": "0,1,2,3",
1310         "UMask": "0x1",
1311         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
1312         "MSRIndex": "0x1a6, 0x1a7",
1313         "SampleAfterValue": "100003",
1314         "BriefDescription": "Counts all demand data writes (RFOs)",
1315         "Offcore": "1",
1316         "CounterHTOff": "0,1,2,3"
1317     },
1318     {
1319         "PublicDescription": "Counts demand data reads",
1320         "EventCode": "0xB7, 0xBB",
1321         "MSRValue": "0x3FFC400001",
1322         "Counter": "0,1,2,3",
1323         "UMask": "0x1",
1324         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
1325         "MSRIndex": "0x1a6, 0x1a7",
1326         "SampleAfterValue": "100003",
1327         "BriefDescription": "Counts demand data reads",
1328         "Offcore": "1",
1329         "CounterHTOff": "0,1,2,3"
1330     },
1331     {
1332         "PublicDescription": "Counts demand data reads",
1333         "EventCode": "0xB7, 0xBB",
1334         "MSRValue": "0x203C400001",
1335         "Counter": "0,1,2,3",
1336         "UMask": "0x1",
1337         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
1338         "MSRIndex": "0x1a6, 0x1a7",
1339         "SampleAfterValue": "100003",
1340         "BriefDescription": "Counts demand data reads",
1341         "Offcore": "1",
1342         "CounterHTOff": "0,1,2,3"
1343     },
1344     {
1345         "PublicDescription": "Counts demand data reads",
1346         "EventCode": "0xB7, 0xBB",
1347         "MSRValue": "0x103C400001",
1348         "Counter": "0,1,2,3",
1349         "UMask": "0x1",
1350         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
1351         "MSRIndex": "0x1a6, 0x1a7",
1352         "SampleAfterValue": "100003",
1353         "BriefDescription": "Counts demand data reads",
1354         "Offcore": "1",
1355         "CounterHTOff": "0,1,2,3"
1356     },
1357     {
1358         "PublicDescription": "Counts demand data reads",
1359         "EventCode": "0xB7, 0xBB",
1360         "MSRValue": "0x043C400001",
1361         "Counter": "0,1,2,3",
1362         "UMask": "0x1",
1363         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
1364         "MSRIndex": "0x1a6, 0x1a7",
1365         "SampleAfterValue": "100003",
1366         "BriefDescription": "Counts demand data reads",
1367         "Offcore": "1",
1368         "CounterHTOff": "0,1,2,3"
1369     },
1370     {
1371         "PublicDescription": "Counts demand data reads",
1372         "EventCode": "0xB7, 0xBB",
1373         "MSRValue": "0x023C400001",
1374         "Counter": "0,1,2,3",
1375         "UMask": "0x1",
1376         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
1377         "MSRIndex": "0x1a6, 0x1a7",
1378         "SampleAfterValue": "100003",
1379         "BriefDescription": "Counts demand data reads",
1380         "Offcore": "1",
1381         "CounterHTOff": "0,1,2,3"
1382     },
1383     {
1384         "PublicDescription": "Counts demand data reads",
1385         "EventCode": "0xB7, 0xBB",
1386         "MSRValue": "0x013C400001",
1387         "Counter": "0,1,2,3",
1388         "UMask": "0x1",
1389         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
1390         "MSRIndex": "0x1a6, 0x1a7",
1391         "SampleAfterValue": "100003",
1392         "BriefDescription": "Counts demand data reads",
1393         "Offcore": "1",
1394         "CounterHTOff": "0,1,2,3"
1395     },
1396     {
1397         "PublicDescription": "Counts demand data reads",
1398         "EventCode": "0xB7, 0xBB",
1399         "MSRValue": "0x00BC400001",
1400         "Counter": "0,1,2,3",
1401         "UMask": "0x1",
1402         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
1403         "MSRIndex": "0x1a6, 0x1a7",
1404         "SampleAfterValue": "100003",
1405         "BriefDescription": "Counts demand data reads",
1406         "Offcore": "1",
1407         "CounterHTOff": "0,1,2,3"
1408     },
1409     {
1410         "PublicDescription": "Counts demand data reads",
1411         "EventCode": "0xB7, 0xBB",
1412         "MSRValue": "0x007C400001",
1413         "Counter": "0,1,2,3",
1414         "UMask": "0x1",
1415         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
1416         "MSRIndex": "0x1a6, 0x1a7",
1417         "SampleAfterValue": "100003",
1418         "BriefDescription": "Counts demand data reads",
1419         "Offcore": "1",
1420         "CounterHTOff": "0,1,2,3"
1421     },
1422     {
1423         "PublicDescription": "Counts demand data reads",
1424         "EventCode": "0xB7, 0xBB",
1425         "MSRValue": "0x3FC4000001",
1426         "Counter": "0,1,2,3",
1427         "UMask": "0x1",
1428         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1429         "MSRIndex": "0x1a6, 0x1a7",
1430         "SampleAfterValue": "100003",
1431         "BriefDescription": "Counts demand data reads",
1432         "Offcore": "1",
1433         "CounterHTOff": "0,1,2,3"
1434     },
1435     {
1436         "PublicDescription": "Counts demand data reads",
1437         "EventCode": "0xB7, 0xBB",
1438         "MSRValue": "0x2004000001",
1439         "Counter": "0,1,2,3",
1440         "UMask": "0x1",
1441         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1442         "MSRIndex": "0x1a6, 0x1a7",
1443         "SampleAfterValue": "100003",
1444         "BriefDescription": "Counts demand data reads",
1445         "Offcore": "1",
1446         "CounterHTOff": "0,1,2,3"
1447     },
1448     {
1449         "PublicDescription": "Counts demand data reads",
1450         "EventCode": "0xB7, 0xBB",
1451         "MSRValue": "0x1004000001",
1452         "Counter": "0,1,2,3",
1453         "UMask": "0x1",
1454         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1455         "MSRIndex": "0x1a6, 0x1a7",
1456         "SampleAfterValue": "100003",
1457         "BriefDescription": "Counts demand data reads",
1458         "Offcore": "1",
1459         "CounterHTOff": "0,1,2,3"
1460     },
1461     {
1462         "PublicDescription": "Counts demand data reads",
1463         "EventCode": "0xB7, 0xBB",
1464         "MSRValue": "0x0404000001",
1465         "Counter": "0,1,2,3",
1466         "UMask": "0x1",
1467         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1468         "MSRIndex": "0x1a6, 0x1a7",
1469         "SampleAfterValue": "100003",
1470         "BriefDescription": "Counts demand data reads",
1471         "Offcore": "1",
1472         "CounterHTOff": "0,1,2,3"
1473     },
1474     {
1475         "PublicDescription": "Counts demand data reads",
1476         "EventCode": "0xB7, 0xBB",
1477         "MSRValue": "0x0204000001",
1478         "Counter": "0,1,2,3",
1479         "UMask": "0x1",
1480         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1481         "MSRIndex": "0x1a6, 0x1a7",
1482         "SampleAfterValue": "100003",
1483         "BriefDescription": "Counts demand data reads",
1484         "Offcore": "1",
1485         "CounterHTOff": "0,1,2,3"
1486     },
1487     {
1488         "PublicDescription": "Counts demand data reads",
1489         "EventCode": "0xB7, 0xBB",
1490         "MSRValue": "0x0104000001",
1491         "Counter": "0,1,2,3",
1492         "UMask": "0x1",
1493         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1494         "MSRIndex": "0x1a6, 0x1a7",
1495         "SampleAfterValue": "100003",
1496         "BriefDescription": "Counts demand data reads",
1497         "Offcore": "1",
1498         "CounterHTOff": "0,1,2,3"
1499     },
1500     {
1501         "PublicDescription": "Counts demand data reads",
1502         "EventCode": "0xB7, 0xBB",
1503         "MSRValue": "0x0084000001",
1504         "Counter": "0,1,2,3",
1505         "UMask": "0x1",
1506         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1507         "MSRIndex": "0x1a6, 0x1a7",
1508         "SampleAfterValue": "100003",
1509         "BriefDescription": "Counts demand data reads",
1510         "Offcore": "1",
1511         "CounterHTOff": "0,1,2,3"
1512     },
1513     {
1514         "PublicDescription": "Counts demand data reads",
1515         "EventCode": "0xB7, 0xBB",
1516         "MSRValue": "0x0044000001",
1517         "Counter": "0,1,2,3",
1518         "UMask": "0x1",
1519         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
1520         "MSRIndex": "0x1a6, 0x1a7",
1521         "SampleAfterValue": "100003",
1522         "BriefDescription": "Counts demand data reads",
1523         "Offcore": "1",
1524         "CounterHTOff": "0,1,2,3"
1525     },
1526     {
1527         "PublicDescription": "Counts demand data reads",
1528         "EventCode": "0xB7, 0xBB",
1529         "MSRValue": "0x2000400001",
1530         "Counter": "0,1,2,3",
1531         "UMask": "0x1",
1532         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
1533         "MSRIndex": "0x1a6, 0x1a7",
1534         "SampleAfterValue": "100003",
1535         "BriefDescription": "Counts demand data reads",
1536         "Offcore": "1",
1537         "CounterHTOff": "0,1,2,3"
1538     },
1539     {
1540         "PublicDescription": "Counts demand data reads",
1541         "EventCode": "0xB7, 0xBB",
1542         "MSRValue": "0x20001C0001",
1543         "Counter": "0,1,2,3",
1544         "UMask": "0x1",
1545         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
1546         "MSRIndex": "0x1a6, 0x1a7",
1547         "SampleAfterValue": "100003",
1548         "BriefDescription": "Counts demand data reads",
1549         "Offcore": "1",
1550         "CounterHTOff": "0,1,2,3"
1551     },
1552     {
1553         "PublicDescription": "Counts demand data reads",
1554         "EventCode": "0xB7, 0xBB",
1555         "MSRValue": "0x2000100001",
1556         "Counter": "0,1,2,3",
1557         "UMask": "0x1",
1558         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
1559         "MSRIndex": "0x1a6, 0x1a7",
1560         "SampleAfterValue": "100003",
1561         "BriefDescription": "Counts demand data reads",
1562         "Offcore": "1",
1563         "CounterHTOff": "0,1,2,3"
1564     },
1565     {
1566         "PublicDescription": "Counts demand data reads",
1567         "EventCode": "0xB7, 0xBB",
1568         "MSRValue": "0x2000080001",
1569         "Counter": "0,1,2,3",
1570         "UMask": "0x1",
1571         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
1572         "MSRIndex": "0x1a6, 0x1a7",
1573         "SampleAfterValue": "100003",
1574         "BriefDescription": "Counts demand data reads",
1575         "Offcore": "1",
1576         "CounterHTOff": "0,1,2,3"
1577     },
1578     {
1579         "PublicDescription": "Counts demand data reads",
1580         "EventCode": "0xB7, 0xBB",
1581         "MSRValue": "0x2000040001",
1582         "Counter": "0,1,2,3",
1583         "UMask": "0x1",
1584         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
1585         "MSRIndex": "0x1a6, 0x1a7",
1586         "SampleAfterValue": "100003",
1587         "BriefDescription": "Counts demand data reads",
1588         "Offcore": "1",
1589         "CounterHTOff": "0,1,2,3"
1590     },
1591     {
1592         "PublicDescription": "Counts demand data reads",
1593         "EventCode": "0xB7, 0xBB",
1594         "MSRValue": "0x2000020001",
1595         "Counter": "0,1,2,3",
1596         "UMask": "0x1",
1597         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1598         "MSRIndex": "0x1a6, 0x1a7",
1599         "SampleAfterValue": "100003",
1600         "BriefDescription": "Counts demand data reads",
1601         "Offcore": "1",
1602         "CounterHTOff": "0,1,2,3"
1603     }
1604 ]