tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json

   1 [
   2    {
   3             "EventCode": "0x02",
   4             "EventName": "uncore_hisi_ddrc.flux_wcmd",
   5             "BriefDescription": "DDRC write commands",
   6             "PublicDescription": "DDRC write commands",
   7             "Unit": "hisi_sccl,ddrc",
   8    },
   9    {
  10             "EventCode": "0x03",
  11             "EventName": "uncore_hisi_ddrc.flux_rcmd",
  12             "BriefDescription": "DDRC read commands",
  13             "PublicDescription": "DDRC read commands",
  14             "Unit": "hisi_sccl,ddrc",
  15    },
  16    {
  17             "EventCode": "0x04",
  18             "EventName": "uncore_hisi_ddrc.flux_wr",
  19             "BriefDescription": "DDRC precharge commands",
  20             "PublicDescription": "DDRC precharge commands",
  21             "Unit": "hisi_sccl,ddrc",
  22    },
  23    {
  24             "EventCode": "0x05",
  25             "EventName": "uncore_hisi_ddrc.act_cmd",
  26             "BriefDescription": "DDRC active commands",
  27             "PublicDescription": "DDRC active commands",
  28             "Unit": "hisi_sccl,ddrc",
  29    },
  30    {
  31             "EventCode": "0x06",
  32             "EventName": "uncore_hisi_ddrc.rnk_chg",
  33             "BriefDescription": "DDRC rank commands",
  34             "PublicDescription": "DDRC rank commands",
  35             "Unit": "hisi_sccl,ddrc",
  36    },
  37    {
  38             "EventCode": "0x07",
  39             "EventName": "uncore_hisi_ddrc.rw_chg",
  40             "BriefDescription": "DDRC read and write changes",
  41             "PublicDescription": "DDRC read and write changes",
  42             "Unit": "hisi_sccl,ddrc",
  43    },
  44 ]