test/dm/clk_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <asm/clk.h>
  11 #include <dm/test.h>
  12 #include <dm/uclass.h>
  13 #include <linux/err.h>
  14 #include <test/ut.h>
  15 #include <sandbox-clk.h>
  16
  17 /* Tests for Common Clock Framework driver */
  18 static int dm_test_clk_ccf(struct unit_test_state *uts)
  19 {
  20         struct clk *clk, *pclk;
  21         struct udevice *dev;
  22         long long rate;
  23         int ret;
  24
  25         /* Get the device using the clk device */
  26         ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
  27
  28         /* Test for clk_get_by_id() */
  29         ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
  30         ut_assertok(ret);
  31         ut_asserteq_str("ecspi_root", clk->dev->name);
  32
  33         /* Test for clk_get_parent_rate() */
  34         ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
  35         ut_assertok(ret);
  36         ut_asserteq_str("ecspi1", clk->dev->name);
  37
  38         rate = clk_get_parent_rate(clk);
  39         ut_asserteq(rate, 20000000);
  40
  41         /* Test the mux of CCF */
  42         ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  43         ut_assertok(ret);
  44         ut_asserteq_str("usdhc1_sel", clk->dev->name);
  45
  46         rate = clk_get_parent_rate(clk);
  47         ut_asserteq(rate, 60000000);
  48
  49         ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
  50         ut_assertok(ret);
  51         ut_asserteq_str("usdhc2_sel", clk->dev->name);
  52
  53         rate = clk_get_parent_rate(clk);
  54         ut_asserteq(rate, 80000000);
  55
  56         pclk = clk_get_parent(clk);
  57         ut_asserteq_str("pll3_80m", pclk->dev->name);
  58
  59         /* Test the composite of CCF */
  60         ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
  61         ut_assertok(ret);
  62         ut_asserteq_str("i2c", clk->dev->name);
  63
  64         rate = clk_get_rate(clk);
  65         ut_asserteq(rate, 60000000);
  66
  67 #if CONFIG_IS_ENABLED(CLK_CCF)
  68         /* Test clk tree enable/disable */
  69         ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
  70         ut_assertok(ret);
  71         ut_asserteq_str("i2c_root", clk->dev->name);
  72
  73         ret = clk_enable(clk);
  74         ut_assertok(ret);
  75
  76         ret = sandbox_clk_enable_count(clk);
  77         ut_asserteq(ret, 1);
  78
  79         ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
  80         ut_assertok(ret);
  81
  82         ret = sandbox_clk_enable_count(pclk);
  83         ut_asserteq(ret, 1);
  84
  85         ret = clk_disable(clk);
  86         ut_assertok(ret);
  87
  88         ret = sandbox_clk_enable_count(clk);
  89         ut_asserteq(ret, 0);
  90
  91         ret = sandbox_clk_enable_count(pclk);
  92         ut_asserteq(ret, 0);
  93 #endif
  94
  95         return 1;
  96 }
  97
  98 DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);