2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #ifndef _DEV_ATH_ATHVAR_H
37 #define _DEV_ATH_ATHVAR_H
40 #include <adf_os_types.h>
41 #include <adf_os_dma.h>
42 #include <adf_os_timer.h>
43 #include <adf_os_lock.h>
44 #include <adf_os_io.h>
45 #include <adf_os_mem.h>
46 #include <adf_os_util.h>
47 #include <adf_os_stdtypes.h>
48 #include <adf_os_defer.h>
49 #include <adf_os_atomic.h>
52 #include <adf_net_types.h>
53 #include <adf_net_wcmd.h>
54 #include <asf_queue.h>
57 #include "ieee80211_var.h"
58 #include "ieee80211_node.h"
59 #include "if_athrate.h"
61 #include <Magpie_api.h>
62 #include <htc_services.h>
67 #define tq_struct adf_os_bh_t
68 #define ATH_INIT_TQUEUE(a,b,c,d) adf_os_init_bh((a),(b),(c),(void *)(d))
69 #define ATH_SCHEDULE_TQUEUE(a,b) adf_os_sched_bh((a),(b))
70 typedef void * TQUEUE_ARG;
72 #define ATH_MIN(a,b) ((a) < (b) ? (a) : (b))
73 #define ATH_AC_2_TXQ(_sc, _ac) (_sc)->sc_ac2q[(_ac)]
74 #define TID_TO_ACTXQ(tidno) sc->sc_ac2q[ TID_TO_WME_AC(tidno)]
76 #define RATE_TABLE_SIZE 32
78 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
80 #define IEEE80211_SEQ_MAX 4096
81 #define SEQNO_FROM_BF_SEQNO(_x) (_x >> IEEE80211_SEQ_SEQ_SHIFT)
82 #define BAW_WITHIN(_start, _bawsz, _seqno) \
83 ((((_seqno) - (_start)) & 4095) < (_bawsz))
85 #define __stats(sc, _x) sc->sc_tx_stats._x ++
86 #define __statsn(sc, _x, _n) sc->sc_tx_stats._x += _n
88 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
92 ATH_TGT_AGGR_BAW_CLOSED,
98 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
99 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
101 #define ATH_DS_BA_SEQ(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_seqnum
102 #define ATH_DS_BA_BITMAP(_ds) (&((struct ath_tx_desc *)_ds)->ds_us.tx.ba_low)
103 #define ATH_DS_TX_BA(_ds) (((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
104 #define ATH_DS_TX_STATUS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_status
105 #define ATH_DS_TX_FLAGS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags
106 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
108 #define ATH_AGGR_DELIM_SZ 4
109 #define ATH_AGGR_MINPLEN 256
110 #define ATH_AGGR_ENCRYPTDELIM 10
112 #define ATH_AGGR_GET_NDELIM(_len) \
113 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
114 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
116 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
117 #define OWLMAX_RETRIES 10
118 #define OWLMAX_BAR_RETRIES 10
120 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
123 #define ATH_TXMAXTRY 11
124 #define TARGET_NODE_MAX ATH_NODE_MAX
125 #define TARGET_VAP_MAX ATH_VAP_MAX
127 #define MAX_RATE_POWER 63
128 #define ATH_COMP_PROC_NO_COMP_NO_CCS 3
130 #define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */
132 #define ATH_AGGR_MIN_QDEPTH 1
134 struct ath_softc_tgt;
138 #define ATH_TXQ(_sc, _qi) (&(_sc)->sc_txq[(_qi)])
139 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
141 #define ATH_NODE_TARGET(_n) ((struct ath_node_target *)(_n))
144 * Built-in implementation for skb free.
146 #define ath_free_rx_skb(_sc,_skb) BUF_Pool_free_buf(_sc->pool_handle, POOL_ID_WLAN_RX_BUF, _skb)
147 #define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb);
149 typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
150 typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
152 struct ath_buf_state {
153 ath_tx_comp_fn_t bfs_comp; /* completion function */
154 ath_txq_add_fn_t bfs_txq_add; /* txq buffer add function */
155 a_uint16_t bfs_pktlen; /* pktlen including crc */
156 a_uint16_t bfs_seqno; /* sequence nuber */
157 a_uint8_t bfs_hdrlen; /* header length */
158 a_uint8_t bfs_keyix; /* key index */
159 a_uint8_t bfs_atype; /* packet type */
160 a_uint8_t bfs_ndelim; /* # delims for padding */
161 a_uint8_t bfs_nframes; /* # frames in aggregate */
162 a_uint8_t bfs_tidno; /* tid of the buffer */
163 a_uint16_t bfs_al; /* length of aggregate */
164 struct ath_rc_series bfs_rcs[4]; /* rate series */
165 struct ath_txq *bfs_txq; /* transmit h/w queue */
166 a_uint8_t bfs_protmode; /* protection mode */
167 a_uint8_t bfs_keytype; /* encr key type */
168 a_uint8_t bfs_retries; /* current retries */
169 a_uint32_t bfs_ismcast : 1; /* is multicast */
170 a_uint32_t bfs_shpream : 1; /* use short preamble */
171 a_uint32_t bfs_isaggr : 1; /* is an aggregate */
172 a_uint32_t bfs_isretried: 1; /* is retried */
175 #define bf_comp bf_state.bfs_comp
176 #define bf_txq_add bf_state.bfs_txq_add
177 #define bf_pktlen bf_state.bfs_pktlen
178 #define bf_hdrlen bf_state.bfs_hdrlen
179 #define bf_keyix bf_state.bfs_keyix
180 #define bf_atype bf_state.bfs_atype
181 #define bf_seqno bf_state.bfs_seqno
182 #define bf_ndelim bf_state.bfs_ndelim
183 #define bf_nframes bf_state.bfs_nframes
184 #define bf_al bf_state.bfs_al
185 #define bf_tidno bf_state.bfs_tidno
186 #define bf_rcs bf_state.bfs_rcs
187 #define bf_txq bf_state.bfs_txq
188 #define bf_protmode bf_state.bfs_protmode
189 #define bf_keytype bf_state.bfs_keytype
190 #define bf_ismcast bf_state.bfs_ismcast
191 #define bf_shpream bf_state.bfs_shpream
192 #define bf_isaggr bf_state.bfs_isaggr
193 #define bf_isretried bf_state.bfs_isretried
194 #define bf_retries bf_state.bfs_retries
196 #define ATH_GENERIC_BUF \
197 asf_tailq_entry(ath_buf) bf_list; \
198 struct ath_buf *bf_next; \
199 struct ath_desc *bf_desc; \
200 struct ath_desc *bf_descarr; \
201 adf_os_dma_map_t bf_dmamap; \
202 adf_os_dmamap_info_t bf_dmamap_info; \
203 struct ieee80211_node_target *bf_node; \
204 adf_nbuf_queue_t bf_skbhead; \
206 struct ath_desc *bf_lastds;
216 struct ath_buf_state bf_state;
218 HTC_ENDPOINT_ID bf_endpt;
226 a_uint32_t bf_status;
227 struct ath_rx_status bf_rx_status;
230 #define ATH_BUF_GET_DESC_PHY_ADDR(bf) bf->bf_desc
231 #define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx])
232 #define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr)
233 #define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr)
235 typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead;
236 typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead;
238 #define WME_NUM_TID 8
239 #define WME_BA_BMP_SIZE 64
240 #define WME_MAX_BA WME_BA_BMP_SIZE
241 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
242 #define TID_CLEANUP_INPROGRES 0x1
243 #define TID_AGGR_ENABLED 0x2
244 #define TID_REINITIALIZE 0x4
246 #define TAILQ_DEQ(_q, _elm, _field) do { \
247 (_elm) = asf_tailq_first((_q)); \
249 asf_tailq_remove((_q), (_elm), _field); \
253 #define TX_BUF_BITMAP_SIZE 32
254 #define TX_BUF_BITMAP_SET(bitmap, i) bitmap[i>>5] |= ((a_uint32_t)1 << (i&0x1f))
255 #define TX_BUF_BITMAP_CLR(bitmap, i) bitmap[i>>5] &= (~((a_uint32_t)1 << (i&0x1f)))
256 #define TX_BUF_BITMAP_IS_SET(bitmap, i) ((bitmap[i>>5] & ((a_uint32_t)1 << (i&0x1f))) != 0)
258 typedef struct ath_atx_tid {
260 a_uint16_t seq_start;
265 a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE];
266 asf_tailq_entry(ath_atx_tid) tid_qelem;
267 asf_tailq_head(ath_tid_rbq,ath_buf) buf_q;
272 struct ath_node_target *an;
275 struct ath_node_target {
276 struct ieee80211_node_target ni;
277 struct ath_atx_tid tid[WME_NUM_TID];
283 const a_int8_t *dd_name;
284 struct ath_desc *dd_desc;
285 adf_os_dma_map_t dd_desc_dmamap;
286 adf_os_dma_addr_t dd_desc_paddr;
287 adf_os_size_t dd_desc_len;
288 struct ath_buf *dd_bufptr;
293 a_uint32_t *axq_link;
294 asf_tailq_head(,ath_buf) axq_q;
295 a_uint32_t axq_depth;
296 struct ath_buf *axq_linkbuf;
297 asf_tailq_head(,ath_atx_tid) axq_tidq;
300 struct wmi_rc_rate_mask_cmd {
307 struct ath_vap_target {
308 struct ieee80211vap_target av_vap;
309 struct ath_txq av_mcastq;
310 struct ath_buf *av_bcbuf;
311 a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */
312 a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */
316 #define ATH_RXBUF_RESET(bf) \
321 /* Target-side HTC/HIF/WMI related data structure */
322 pool_handle_t pool_handle;
323 hif_handle_t tgt_hif_handle;
324 htc_handle_t tgt_htc_handle;
325 wmi_handle_t tgt_wmi_handle;
327 /* Target HTC Service IDs */
328 HTC_SERVICE htc_beacon_service;
329 HTC_SERVICE htc_cab_service;
330 HTC_SERVICE htc_uapsd_service;
331 HTC_SERVICE htc_mgmt_service;
332 HTC_SERVICE htc_data_VO_service;
333 HTC_SERVICE htc_data_VI_service;
334 HTC_SERVICE htc_data_BE_service;
335 HTC_SERVICE htc_data_BK_service;
338 /* Target HTC Endpoint IDs */
339 HTC_ENDPOINT_ID wmi_command_ep;
340 HTC_ENDPOINT_ID beacon_ep;
341 HTC_ENDPOINT_ID cab_ep;
342 HTC_ENDPOINT_ID uapsd_ep;
343 HTC_ENDPOINT_ID mgmt_ep;
344 HTC_ENDPOINT_ID data_VO_ep;
345 HTC_ENDPOINT_ID data_VI_ep;
346 HTC_ENDPOINT_ID data_BE_ep;
347 HTC_ENDPOINT_ID data_BK_ep;
349 adf_os_handle_t sc_hdl;
350 adf_os_device_t sc_dev;
352 struct ath_ratectrl *sc_rc;
354 a_uint32_t sc_invalid : 1,
355 sc_txstbcsupport : 1,
356 sc_rxstbcsupport : 2,
360 a_int32_t sc_rxbufsize;
361 a_uint16_t sc_cachelsz;
363 struct ath_interrupt_stats sc_int_stats;
364 struct ath_tx_stats sc_tx_stats;
365 struct ath_rx_stats sc_rx_stats;
367 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
368 const HAL_RATE_TABLE *sc_currates;
370 a_uint8_t sc_rixmap[256];
372 enum ieee80211_phymode sc_curmode;
374 a_uint8_t sc_protrix;
378 tq_struct sc_bmisstq;
380 tq_struct sc_fataltq;
382 ath_bufhead sc_rxbuf;
384 ath_deschead sc_rxdesc_idle;
385 ath_deschead sc_rxdesc;
386 struct ath_desc *sc_rxdesc_held;
388 struct ath_buf *sc_txbuf_held;
390 struct ath_descdma sc_rxdma;
391 struct ath_descdma sc_txdma;
392 struct ath_descdma sc_bdma;
394 a_uint32_t *sc_rxlink;
395 ath_bufhead sc_txbuf;
396 a_uint8_t sc_txqsetup;
398 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
399 struct ath_txq *sc_ac2q[WME_NUM_AC];
402 struct ath_hal *sc_ah;
403 struct ath_txq *sc_cabq;
404 struct ath_txq *sc_uapsdq;
405 struct ath_node_target sc_sta[TARGET_NODE_MAX];
406 struct ath_vap_target sc_vap[TARGET_VAP_MAX];
407 struct ieee80211com_target sc_ic;
410 a_uint64_t sc_swba_tsf;
412 WMI_TXSTATUS_EVENT tx_status[2];
415 #define SM(_v, _f) (((_v) << _f##_S) & _f)
416 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
418 #define ATH9K_HTC_TXSTAT_ACK 1<<0
419 #define ATH9K_HTC_TXSTAT_FILT 1<<1
420 #define ATH9K_HTC_TXSTAT_RTC_CTS 1<<2
421 #define ATH9K_HTC_TXSTAT_MCS 1<<3
422 #define ATH9K_HTC_TXSTAT_CW40 1<<4
423 #define ATH9K_HTC_TXSTAT_SGI 1<<5
425 #define ATH9K_HTC_TXSTAT_RATE 0x0f
426 #define ATH9K_HTC_TXSTAT_RATE_S 0
427 #define ATH9K_HTC_TXSTAT_EPID 0xf0
428 #define ATH9K_HTC_TXSTAT_EPID_S 4
430 #define TAILQ_INSERTQ_HEAD(head, tq, field) do { \
431 if ((head)->tqh_first) { \
432 *(tq)->tqh_last = (head)->tqh_first; \
433 (head)->tqh_first->field.tqe_prev = (tq)->tqh_last; \
435 (head)->tqh_last = (tq)->tqh_last; \
437 (head)->tqh_first = (tq)->tqh_first; \
438 (tq)->tqh_first->field.tqe_prev = &(head)->tqh_first; \
441 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
442 asf_tailq_insert_tail( &(_tq)->axq_q, (_elm), _field); \
443 (_tq)->axq_depth++; \
444 (_tq)->axq_linkbuf = (_elm); \
446 #define ATH_TXQ_REMOVE_HEAD(_tq, _elm, _field) do { \
447 asf_tailq_remove(&(_tq)->axq_q, (_elm), _field); \
448 (_tq)->axq_depth--; \
451 struct ieee80211_rate {
452 struct ieee80211_rateset rates;
453 struct ieee80211_rateset htrates;
454 } __attribute__((packed));
456 struct wmi_rc_state_change_cmd {
461 struct ieee80211_rate rs;
462 } __attribute__((packed));
464 struct wmi_rc_rate_update_cmd {
465 a_uint8_t node_index;
469 struct ieee80211_rate rs;
470 } __attribute__((packed));
478 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp);
480 #define ath_hal_getratetable(_ah, _mode) \
481 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
482 #define ath_hal_intrset(_ah, _mask) \
483 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
484 #define ath_hal_intrpend(_ah) \
485 ((*(_ah)->ah_isInterruptPending)((_ah)))
486 #define ath_hal_getisr(_ah, _pmask) \
487 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
488 #define ath_hal_updatetxtriglevel(_ah, _inc) \
489 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
490 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
491 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
492 #define ath_hal_rxprocdescfast(_ah, _ds, _dspa, _dsnext, _rx_stats) \
493 ((*(_ah)->ah_procRxDescFast)((_ah), (_ds), (_dspa), (_dsnext), (_rx_stats)))
494 #define ath_hal_stoptxdma(_ah, _qnum) \
495 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
496 #define ath_hal_aborttxdma(_ah) \
497 ((*(_ah)->ah_abortTxDma)(_ah))
498 #define ath_hal_set11n_txdesc(_ah, _ds, _pktlen, _type, _txpower,\
499 _keyix, _keytype, _flags) \
500 ((*(_ah)->ah_set11nTxDesc)(_ah, _ds, _pktlen, _type, _txpower, _keyix,\
502 #define ath_hal_set11n_ratescenario(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration, \
503 _series, _nseries, _flags) \
504 ((*(_ah)->ah_set11nRateScenario)(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration,\
505 _series, _nseries, _flags))
506 #define ath_hal_clr11n_aggr(_ah, _ds) \
507 ((*(_ah)->ah_clr11nAggr)(_ah, _ds))
508 #define ath_hal_set11n_burstduration(_ah, _ds, _burstduration) \
509 ((*(_ah)->ah_set11nBurstDuration)(_ah, _ds, _burstduration))
510 #define ath_hal_set11n_virtualmorefrag(_ah, _ds, _vmf) \
511 ((*(_ah)->ah_set11nVirtualMoreFrag)(_ah, _ds, _vmf))
512 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
513 _txr0, _txtr0, _keyix, _ant, _flags, \
514 _rtsrate, _rtsdura, \
515 _compicvlen, _compivlen, _comp) \
516 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
517 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
518 (_flags), (_rtsrate), (_rtsdura), \
519 (_compicvlen), (_compivlen), (_comp)))
520 #define ath_hal_fillkeytxdesc(_ah, _ds, _keytype) \
521 ((*(_ah)->ah_fillKeyTxDesc)((_ah), (_ds), (_keytype)))
522 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
523 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
524 #define ath_hal_txprocdesc(_ah, _ds) \
525 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
526 #define ath_hal_putrxbuf(_ah, _bufaddr) \
527 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
528 #define ath_hal_rxena(_ah) \
529 ((*(_ah)->ah_enableReceive)((_ah)))
530 #define ath_hal_stopdmarecv(_ah) \
531 ((*(_ah)->ah_stopDmaReceive)((_ah)))
532 #define ath_hal_stoppcurecv(_ah) \
533 ((*(_ah)->ah_stopPcuReceive)((_ah)))
534 #define ath_hal_htsupported(_ah) \
535 (ath_hal_getcapability(_ah, HAL_CAP_HT, 0, NULL) == HAL_OK)
536 #define ath_hal_rxstbcsupport(_ah, _rxstbc) \
537 (ath_hal_getcapability(_ah, HAL_CAP_RX_STBC, 0, _rxstbc) == HAL_OK)
538 #define ath_hal_txstbcsupport(_ah, _txstbc) \
539 (ath_hal_getcapability(_ah, HAL_CAP_TX_STBC, 0, _txstbc) == HAL_OK)
540 #define ath_hal_getrtsaggrlimit(_ah, _pv) \
541 (ath_hal_getcapability(_ah, HAL_CAP_RTS_AGGR_LIMIT, 0, _pv) == HAL_OK)
542 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
543 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
544 #define ath_hal_txstart(_ah, _q) \
545 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
546 #define ath_hal_setrxfilter(_ah, _filter) \
547 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
548 #define ath_hal_gettsf64(_ah) \
549 ((*(_ah)->ah_getTsf64)((_ah)))
550 #define ath_hal_intrset(_ah, _mask) \
551 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
552 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
553 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
554 #define ath_hal_set11n_aggr_first(_ah, _ds, _aggrlen, _numdelims) \
555 ((*(_ah)->ah_set11nAggrFirst)(_ah, _ds, _aggrlen, _numdelims))
556 #define ath_hal_set11n_aggr_middle(_ah, _ds, _numdelims) \
557 ((*(_ah)->ah_set11nAggrMiddle)(_ah, _ds, _numdelims))
558 #define ath_hal_set11n_aggr_last(_ah, _ds) \
559 ((*(_ah)->ah_set11nAggrLast)(_ah, _ds))
560 #define ath_hal_numtxpending(_ah, _q) \
561 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
563 #endif /* _DEV_ATH_ATHVAR_H */