2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
38 * Copyright (c) 2002-2005 Atheros Communications, Inc.
39 * All rights reserved.
41 * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ah_internal.h#2 $
43 #ifndef _ATH_AH_INTERAL_H_
44 #define _ATH_AH_INTERAL_H_
48 #define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1)
51 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
52 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
55 * Common assertion interface. Note: it is a bad idea to generate
56 * an assertion failure for any recoverable event. Instead catch
57 * the violation and, if possible, fix it up or recover from it; either
58 * with an error return value or a diagnostic messages. System software
59 * does not panic unless the situation is hopeless.
62 #define HALASSERT(_x) do { \
67 #endif /* AH_ASSERT */
70 #define NBBY 8 /* number of bits/byte */
73 #define IEEE80211_ADDR_LEN 6
76 * Internal form of a HAL_CHANNEL. Note that the structure
77 * must be defined such that you can cast references to a
78 * HAL_CHANNEL so don't shuffle the first two members.
81 a_uint16_t channel; /* NB: must be first for casting */
82 a_uint32_t channelFlags;
86 int8_t minTxPower; /* as above... */
87 a_uint8_t regClassId; /* Regulatory class id */
91 HAL_BOOL oneTimeCalsDone;
94 a_int16_t rawNoiseFloor;
95 a_int16_t finalNoiseFloor;
97 a_uint32_t regDmnFlags; /* Flags for channel use in reg */
98 a_uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
99 a_uint16_t mainSpur; /* cached spur value for this cahnnel */
100 u_int64_t ah_tsf_last; /* tsf @ which time accured is computed */
101 u_int64_t ah_channel_time; /* time on the channel */
102 u_int64_t dfsTsf; /* Tsf when channel leaves NOL */
103 } HAL_CHANNEL_INTERNAL;
106 a_uint32_t halChanSpreadSupport : 1,
107 halSleepAfterBeaconBroken : 1,
108 halCompressSupport : 1,
110 halFastFramesSupport : 1,
111 halChapTuningSupport : 1,
112 halTurboGSupport : 1,
113 halTurboPrimeSupport : 1,
115 halMicAesCcmSupport : 1,
116 halMicCkipSupport : 1,
117 halMicTkipSupport : 1,
118 halCipherAesCcmSupport : 1,
119 halCipherCkipSupport : 1,
120 halCipherTkipSupport : 1,
123 halBssIdMaskSupport : 1,
124 halMcastKeySrchSupport : 1,
125 halTsfAddSupport : 1,
127 halChanQuarterRate : 1,
129 halRxStbcSupport : 1,
130 halTxStbcSupport : 1,
132 halFastCCSupport : 1,
133 halExtChanDfsSupport : 1,
134 halUseCombinedRadarRssi : 1,
136 halRifsRxSupport : 1,
137 halRifsTxSupport : 1,
139 halforcePpmSupport : 1,
140 halAutoSleepSupport : 1,
141 hal4kbSplitTransSupport : 1,
142 halEnhancedPmSupport : 1,
143 halMbssidAggrSupport : 1,
144 halTkipWepHtRateSupport : 1,
146 halRfSilentSupport : 1;
147 a_uint32_t halWirelessModes;
148 a_uint16_t halTotalQueues;
149 a_uint16_t halKeyCacheSize;
150 a_uint16_t halLow5GhzChan, halHigh5GhzChan;
151 a_uint16_t halLow2GhzChan, halHigh2GhzChan;
152 a_uint16_t halNumMRRetries;
153 a_uint8_t halTxChainMask;
154 a_uint8_t halRxChainMask;
155 a_uint16_t halRtsAggrLimit;
156 a_uint16_t halJapanRegCap;
157 a_uint8_t halNumGpioPins;
161 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
163 * Stuff that would naturally come from _ieee80211.h
165 #define IEEE80211_ADDR_LEN 6
166 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */
167 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
168 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
169 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
170 #define IEEE80211_CRC_LEN 4
171 #define IEEE80211_MTU 1500
172 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
173 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
175 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
178 IEEE80211_T_DS, /* direct sequence spread spectrum */
179 IEEE80211_T_FH, /* frequency hopping */
180 IEEE80211_T_OFDM, /* frequency division multiplexing */
181 IEEE80211_T_TURBO, /* high rate DS */
182 IEEE80211_T_HT, /* HT - full GI */
185 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
186 #endif /* _NET_IF_IEEE80211_H_ */
188 /* NB: these are defined privately until XR support is announced */
190 ATHEROS_T_XR = IEEE80211_T_MAX, /* extended range */
193 struct ath_hal_private {
196 a_uint32_t ah_macVersion;
197 a_uint16_t ah_macRev;
198 a_uint16_t ah_phyRev;
200 HAL_CAPABILITIES ah_caps; /* device capabilities */
201 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
204 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
206 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
207 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20))
208 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
209 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) || \
210 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20))
211 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
212 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
213 #define IS_CHAN_X(_c) (((_c)->channelFlags & CHANNEL_X) == CHANNEL_X)
214 #define IS_CHAN_PUREG(_c) \
215 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
216 #define IS_CHAN_NA(_c) (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)
217 #define IS_CHAN_NG(_c) (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)
219 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
220 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
221 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
222 #define IS_CHAN_XR(_c) (((_c)->channelFlags & CHANNEL_XR) != 0)
223 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
224 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
225 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
226 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
227 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
228 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
229 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
230 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
232 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
235 * Register manipulation macros that expect bit field defines
236 * to follow the convention that an _S suffix is appended for
237 * a shift count, while the field mask has no suffix.
239 #define SM(_v, _f) (((_v) << _f##_S) & _f)
240 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
241 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
242 OS_REG_WRITE(_a, _r, \
243 (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
244 #define OS_REG_RMW(_a, _r, _set, _clr) \
245 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
246 #define OS_REG_SET_BIT(_a, _r, _f) \
247 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
248 #define OS_REG_CLR_BIT(_a, _r, _f) \
249 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
252 /* wait for the register contents to have the specified value */
253 extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg,
254 a_uint32_t mask, a_uint32_t val);
256 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list);
258 /* allocate and free memory */
259 extern void *ath_hal_malloc(size_t);
260 extern void ath_hal_free(void *);
263 * Generic get/set capability support. Each chip overrides
264 * this routine to support chip-specific capabilities.
266 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
267 HAL_CAPABILITY_TYPE type, a_uint32_t capability,
269 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
270 HAL_CAPABILITY_TYPE type, a_uint32_t capability,
271 a_uint32_t setting, HAL_STATUS *status);
273 #endif /* _ATH_AH_INTERAL_H_ */