2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 #define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) (Owl) */
47 #define HAL_RATE_TABLE_SIZE 33
50 HAL_OK = 0, /* No error */
51 HAL_ENXIO = 1, /* No hardware present */
52 HAL_ENOMEM = 2, /* Memory allocation failed */
53 HAL_EIO = 3, /* Hardware didn't respond as expected */
54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
55 HAL_EEVERSION = 5, /* EEPROM version invalid */
56 HAL_EELOCKED = 6, /* EEPROM unreadable */
57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
58 HAL_EEREAD = 8, /* EEPROM read problem */
59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
60 HAL_EESIZE = 10, /* EEPROM size not supported */
61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
62 HAL_EINVAL = 12, /* Invalid parameter to function */
63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
64 HAL_ESELFTEST = 14, /* Hardware self-test failed */
65 HAL_EINPROGRESS = 15, /* Operation incomplete */
66 HAL_FULL_RESET = 16, /* Full reset done */
76 HAL_CAP_BSSIDMASK = 1,
77 HAL_CAP_TSF_ADJUST = 2,
79 HAL_CAP_RTS_AGGR_LIMIT = 6,
80 } HAL_CAPABILITY_TYPE;
90 HAL_TX_QUEUE_INACTIVE = 0,
91 HAL_TX_QUEUE_DATA = 1,
92 HAL_TX_QUEUE_BEACON = 2,
94 HAL_TX_QUEUE_PSPOLL = 4,
95 HAL_TX_QUEUE_UAPSD = 5,
105 } HAL_TX_QUEUE_SUBTYPE;
107 #define HAL_NUM_TX_QUEUES 10
110 HAL_PKT_TYPE_NORMAL = 0,
111 HAL_PKT_TYPE_ATIM = 1,
112 HAL_PKT_TYPE_PSPOLL = 2,
113 HAL_PKT_TYPE_BEACON = 3,
114 HAL_PKT_TYPE_PROBE_RESP = 4,
115 HAL_PKT_TYPE_CHIRP = 5,
116 HAL_PKT_TYPE_GRP_POLL = 6,
120 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
121 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
125 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
126 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
127 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
128 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
129 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
130 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
131 HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */
132 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
133 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
135 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors*/
136 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PSPOLL frames */
138 ** PHY "Pseudo bits" should be in the upper 16 bits since the lower
139 ** 16 bits actually correspond to register 0x803c bits
142 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/
146 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */
147 #define CHANNEL_HALF 0x4000 /* Half rate channel */
150 HAL_INT_RX = 0x00000001, /* Non-common mapping */
151 HAL_INT_RXDESC = 0x00000002,
152 HAL_INT_RXNOFRM = 0x00000008,
153 HAL_INT_RXEOL = 0x00000010,
154 HAL_INT_RXORN = 0x00000020,
155 HAL_INT_TX = 0x00000040, /* Non-common mapping */
156 HAL_INT_TXDESC = 0x00000080,
157 HAL_INT_TXURN = 0x00000800,
158 HAL_INT_MIB = 0x00001000,
159 HAL_INT_RXPHY = 0x00004000,
160 HAL_INT_RXKCM = 0x00008000,
161 HAL_INT_SWBA = 0x00010000,
162 HAL_INT_BMISS = 0x00040000,
163 HAL_INT_BNR = 0x00100000, /* Non-common mapping */
164 HAL_INT_GPIO = 0x01000000,
165 HAL_INT_CST = 0x02000000, /* Non-common mapping */
166 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
167 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
168 HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */
169 HAL_INT_GENTIMER =0x08000000, /* Non-common mapping */
171 /* Interrupt bits that map directly to ISR/IMR bits */
172 HAL_INT_COMMON = HAL_INT_RXNOFRM
184 HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */
189 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
190 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
191 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
192 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
196 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
197 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
201 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
202 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
206 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
207 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
208 } HAL_HT_EXTPROTSPACING;
211 HAL_HT_MACMODE ht_macmode; /* MAC - 20/40 mode */
212 HAL_HT_PHYMODE ht_phymode; /* PHY - 20/40 mode */
213 a_int8_t ht_extoff; /* ext channel offset */
214 HAL_HT_EXTPROTSPACING ht_extprotspacing; /* ext channel protection spacing */
218 a_uint8_t ht_txchainmask; /* tx chain mask */
219 a_uint8_t ht_rxchainmask; /* rx chain mask */
228 #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */
229 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
230 #define CHANNEL_CCK 0x0020 /* CCK channel */
231 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
232 #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */
233 #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */
234 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
235 #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */
236 #define CHANNEL_XR 0x0800 /* XR channel */
237 #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */
238 #define CHANNEL_HALF 0x4000 /* Half rate channel */
239 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */
240 #define CHANNEL_HT20 0x10000 /* HT20 channel */
241 #define CHANNEL_HT40 0x20000 /* HT40 channel */
242 #define CHANNEL_HT40U 0x40000 /* control channel can be upper channel */
243 #define CHANNEL_HT40L 0x80000 /* control channel can be lower channel */
246 #define CHANNEL_INTERFERENCE 0x01
247 #define CHANNEL_DFS 0x02 /* DFS required on channel */
248 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
249 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
251 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
252 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
253 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
254 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
255 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
256 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
257 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
258 #define CHANNEL_108A CHANNEL_T
259 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
261 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
262 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
263 #define CHANNEL_G_HT40 (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40)
264 #define CHANNEL_A_HT40 (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40)
265 #define CHANNEL_ALL \
273 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
277 a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE];
282 a_int16_t txPower2Chains;
283 a_int16_t txPower3Chains;
286 a_uint8_t shortPreamble;
288 a_uint8_t controlRate;
289 a_uint16_t lpAckDuration;
290 a_uint16_t spAckDuration;
291 } info[HAL_RATE_TABLE_SIZE];
297 a_uint32_t PktDuration;
299 a_uint32_t RateFlags;
300 a_uint32_t RateIndex;
301 a_uint32_t TxPowerCap; /* in 1/2 dBm units */
302 } HAL_11N_RATE_SERIES;
308 a_uint8_t rateCodeToIndex[HAL_RATE_TABLE_SIZE];
314 a_uint8_t shortPreamble;
316 a_uint8_t controlRate;
317 a_uint16_t lpAckDuration;
318 a_uint16_t spAckDuration;
319 } info[HAL_RATE_TABLE_SIZE];
322 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
323 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
324 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
325 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
330 a_uint32_t PktDuration;
332 a_uint32_t RateFlags;
333 } HAL_11N_RATE_SERIES;
338 HAL_MODE_11A = 0x001, /* 11a channels */
339 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
340 HAL_MODE_11B = 0x004, /* 11b channels */
341 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
342 HAL_MODE_11G = 0x008, /* XXX historical */
343 HAL_MODE_108G = 0x020, /* 11a+Turbo channels */
344 HAL_MODE_108A = 0x040, /* 11g+Turbo channels */
345 HAL_MODE_XR = 0x100, /* XR channels */
346 HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
347 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
348 HAL_MODE_11NG = 0x4000, /* 11ng channels */
349 HAL_MODE_11NA = 0x8000, /* 11na channels */
350 HAL_MODE_ALL = 0xffff
362 struct ath_rx_status;
368 adf_os_device_t ah_dev;
370 a_uint32_t ah_macVersion;
371 a_uint16_t ah_macRev;
372 a_uint16_t ah_phyRev;
373 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
375 void __ahdecl(*ah_detach)(struct ath_hal*);
376 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
377 HAL_BOOL incTrigLevel);
380 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
382 HAL_BOOL __ahdecl(*ah_updateCTSForBursting)(struct ath_hal *,
383 struct ath_desc *, struct ath_desc *,
384 struct ath_desc *, struct ath_desc *,
385 a_uint32_t, a_uint32_t);
386 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
389 /* Target Transmit Functions */
391 a_uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, a_uint32_t);
392 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
393 a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
394 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
395 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t);
397 HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *);
399 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *ah,
400 struct ath_tx_desc *ds,
401 a_uint32_t pktLen, HAL_PKT_TYPE type,
402 a_uint32_t txPower, a_uint32_t keyIx,
403 HAL_KEY_TYPE keyType,
405 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *ah,
406 struct ath_tx_desc *ds,
407 a_uint32_t durUpdateEn,
408 a_uint32_t rtsctsRate,
409 a_uint32_t rtsctsDuration,
410 HAL_11N_RATE_SERIES series[],
411 a_uint32_t nseries, a_uint32_t flags);
412 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah,
413 struct ath_tx_desc *ds, a_uint32_t aggrLen,
414 a_uint32_t numDelims);
415 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
416 struct ath_tx_desc *ds, a_uint32_t numDelims);
417 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
418 struct ath_tx_desc *ds);
419 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
420 struct ath_tx_desc *ds);
421 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,
422 struct ath_tx_desc *ds,
423 a_uint32_t burstDuration);
424 void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah,
425 struct ath_tx_desc *ds, a_uint32_t vmf);
427 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_tx_desc *,
428 a_uint32_t pktLen, a_uint32_t hdrLen,
429 HAL_PKT_TYPE type, a_uint32_t txPower,
430 a_uint32_t txRate0, a_uint32_t txTries0,
431 a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
432 a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
433 a_uint32_t compicvLen, a_uint32_t compivLen,
435 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_tx_desc *,
436 a_uint32_t segLen, HAL_BOOL firstSeg,
437 HAL_BOOL lastSeg, const struct ath_tx_desc *);
438 HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_hal *, struct ath_tx_desc *, HAL_KEY_TYPE);
439 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_tx_desc *);
440 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, a_uint32_t *);
441 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
442 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*);
443 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
444 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
445 a_uint32_t filter0, a_uint32_t filter1);
447 a_uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
448 u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
449 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
451 /* Target receive Functions */
452 a_uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
453 void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
454 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_rx_desc *,
455 a_uint32_t size, a_uint32_t flags);
456 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
457 a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
458 HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
459 struct ath_rx_desc *ds, a_uint32_t pa,
460 struct ath_desc *nds,
461 struct ath_rx_status *rx_stats);
462 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
463 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
464 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
465 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
467 /* Interrupt functions */
468 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
469 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
470 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
471 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
475 extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC,
477 a_uint32_t flags, HAL_STATUS* status);
479 extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
480 const HAL_RATE_TABLE *rates,
483 HAL_BOOL shortPreamble);
484 #endif /* _ATH_AH_H_ */