Merge pull request #158 from olerem/gcc-9
[librecmc/open-ath9k-htc-firmware.git] / target_firmware / wlan / ah.h
1 /*
2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted (subject to the limitations in the
7  * disclaimer below) provided that the following conditions are met:
8  *
9  *  * Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  *
12  *  * Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the
15  *    distribution.
16  *
17  *  * Neither the name of Qualcomm Atheros nor the names of its
18  *    contributors may be used to endorse or promote products derived
19  *    from this software without specific prior written permission.
20  *
21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35
36 #ifndef _ATH_AH_H_
37 #define _ATH_AH_H_
38
39 #include <ah_osdep.h>
40 #include <ah_desc.h>
41
42 #ifndef __ahdecl
43 #define __ahdecl
44 #endif
45
46 #define AR5416_DEVID_PCIE   0x0024  /* AR5416 PCI-E (XB) (Owl) */
47 #define HAL_RATE_TABLE_SIZE 33
48
49 typedef enum {
50         HAL_OK           = 0,    /* No error */
51         HAL_ENXIO        = 1,    /* No hardware present */
52         HAL_ENOMEM       = 2,    /* Memory allocation failed */
53         HAL_EIO          = 3,    /* Hardware didn't respond as expected */
54         HAL_EEMAGIC      = 4,    /* EEPROM magic number invalid */
55         HAL_EEVERSION    = 5,    /* EEPROM version invalid */
56         HAL_EELOCKED     = 6,    /* EEPROM unreadable */
57         HAL_EEBADSUM     = 7,    /* EEPROM checksum invalid */
58         HAL_EEREAD       = 8,    /* EEPROM read problem */
59         HAL_EEBADMAC     = 9,    /* EEPROM mac address invalid */
60         HAL_EESIZE       = 10,   /* EEPROM size not supported */
61         HAL_EEWRITE      = 11,   /* Attempt to change write-locked EEPROM */
62         HAL_EINVAL       = 12,   /* Invalid parameter to function */
63         HAL_ENOTSUPP     = 13,   /* Hardware revision not supported */
64         HAL_ESELFTEST    = 14,   /* Hardware self-test failed */
65         HAL_EINPROGRESS  = 15,   /* Operation incomplete */
66         HAL_FULL_RESET   = 16,   /* Full reset done */
67 } HAL_STATUS;
68
69 typedef enum {
70         AH_FALSE = 0,
71         AH_TRUE  = 1,
72 } HAL_BOOL;
73
74 typedef enum {
75         HAL_CAP_VEOL        = 0,
76         HAL_CAP_BSSIDMASK   = 1,
77         HAL_CAP_TSF_ADJUST  = 2,
78         HAL_CAP_HT          = 5,
79         HAL_CAP_RTS_AGGR_LIMIT = 6,
80 } HAL_CAPABILITY_TYPE;
81
82 typedef enum {
83         HAL_TX_QUEUE_INACTIVE   = 0,
84         HAL_TX_QUEUE_DATA   = 1,
85         HAL_TX_QUEUE_BEACON = 2,
86         HAL_TX_QUEUE_CAB    = 3,
87         HAL_TX_QUEUE_PSPOLL = 4,
88         HAL_TX_QUEUE_UAPSD  = 5,
89 } HAL_TX_QUEUE;
90
91 typedef enum {
92         HAL_WME_AC_BK   = 0,
93         HAL_WME_AC_BE   = 1,
94         HAL_WME_AC_VI   = 2,
95         HAL_WME_AC_VO   = 3,
96         HAL_WME_UPSD    = 4,
97         HAL_XR_DATA     = 5,
98 } HAL_TX_QUEUE_SUBTYPE;
99
100 #define HAL_NUM_TX_QUEUES  10
101
102 typedef enum {
103         HAL_PKT_TYPE_NORMAL = 0,
104         HAL_PKT_TYPE_ATIM   = 1,
105         HAL_PKT_TYPE_PSPOLL = 2,
106         HAL_PKT_TYPE_BEACON = 3,
107         HAL_PKT_TYPE_PROBE_RESP = 4,
108         HAL_PKT_TYPE_CHIRP  = 5,
109         HAL_PKT_TYPE_GRP_POLL = 6,
110 } HAL_PKT_TYPE;
111
112 typedef enum {
113         HAL_RX_CLEAR_CTL_LOW    = 0x1,    /* force control channel to appear busy */
114         HAL_RX_CLEAR_EXT_LOW    = 0x2,    /* force extension channel to appear busy */
115 } HAL_HT_RXCLEAR;
116
117 typedef enum {
118         HAL_RX_FILTER_UCAST     = 0x00000001,   /* Allow unicast frames */
119         HAL_RX_FILTER_MCAST     = 0x00000002,   /* Allow multicast frames */
120         HAL_RX_FILTER_BCAST     = 0x00000004,   /* Allow broadcast frames */
121         HAL_RX_FILTER_CONTROL   = 0x00000008,   /* Allow control frames */
122         HAL_RX_FILTER_BEACON    = 0x00000010,   /* Allow beacon frames */
123         HAL_RX_FILTER_PROM      = 0x00000020,   /* Promiscuous mode */
124         HAL_RX_FILTER_XRPOLL    = 0x00000040,   /* Allow XR poll frmae */
125         HAL_RX_FILTER_PROBEREQ  = 0x00000080,   /* Allow probe request frames */
126         HAL_RX_FILTER_PHYERR    = 0x00000100,   /* Allow phy errors */
127 #ifdef MAGPIE_MERLIN
128         HAL_RX_FILTER_PHYRADAR  =  0x00002000, /* Allow phy radar errors*/
129         HAL_RX_FILTER_PSPOLL    = 0x00004000,   /* Allow PSPOLL frames */
130         /*
131         ** PHY "Pseudo bits" should be in the upper 16 bits since the lower
132         ** 16 bits actually correspond to register 0x803c bits
133         */
134 #else
135         HAL_RX_FILTER_PHYRADAR  = 0x00000200,   /* Allow phy radar errors*/
136 #endif
137 } HAL_RX_FILTER;
138
139 #define CHANNEL_QUARTER 0x8000  /* Quarter rate channel */
140 #define CHANNEL_HALF    0x4000  /* Half rate channel */
141
142 typedef enum {
143         HAL_INT_RX      = 0x00000001,   /* Non-common mapping */
144         HAL_INT_RXDESC  = 0x00000002,
145         HAL_INT_RXNOFRM = 0x00000008,
146         HAL_INT_RXEOL   = 0x00000010,
147         HAL_INT_RXORN   = 0x00000020,
148         HAL_INT_TX      = 0x00000040,   /* Non-common mapping */
149         HAL_INT_TXDESC  = 0x00000080,
150         HAL_INT_TXURN   = 0x00000800,
151         HAL_INT_MIB     = 0x00001000,
152         HAL_INT_RXPHY   = 0x00004000,
153         HAL_INT_RXKCM   = 0x00008000,
154         HAL_INT_SWBA    = 0x00010000,
155         HAL_INT_BMISS   = 0x00040000,
156         HAL_INT_BNR     = 0x00100000,   /* Non-common mapping */
157         HAL_INT_GPIO    = 0x01000000,
158         HAL_INT_CST     = 0x02000000,   /* Non-common mapping */
159         HAL_INT_GTT     = 0x20000000,   /* Non-common mapping */
160         HAL_INT_FATAL   = 0x40000000,   /* Non-common mapping */
161         HAL_INT_GLOBAL  = 0x80000000,   /* Set/clear IER */
162         HAL_INT_GENTIMER =0x08000000,   /* Non-common mapping */
163
164         /* Interrupt bits that map directly to ISR/IMR bits */
165         HAL_INT_COMMON  = HAL_INT_RXNOFRM
166         | HAL_INT_RXDESC
167         | HAL_INT_RXEOL
168         | HAL_INT_RXORN
169         | HAL_INT_TXURN
170         | HAL_INT_TXDESC
171         | HAL_INT_MIB
172         | HAL_INT_RXPHY
173         | HAL_INT_RXKCM
174         | HAL_INT_SWBA
175         | HAL_INT_BMISS
176         | HAL_INT_GPIO,
177         HAL_INT_NOCARD  = 0xffffffff    /* To signal the card was removed */
178 } HAL_INT;
179
180 #ifdef MAGPIE_MERLIN
181
182 #define HAL_RATESERIES_RTS_CTS    0x0001  /* use rts/cts w/this series */
183 #define HAL_RATESERIES_2040       0x0002  /* use ext channel for series */
184 #define HAL_RATESERIES_HALFGI     0x0004  /* use half-gi for series */
185 #define HAL_RATESERIES_STBC       0x0008  /* use STBC for series */
186
187 /* 11n */
188 typedef enum {
189         HAL_HT_MACMODE_20   = 0,        /* 20 MHz operation */
190         HAL_HT_MACMODE_2040 = 1,        /* 20/40 MHz operation */
191 } HAL_HT_MACMODE;
192
193 typedef enum {
194         HAL_HT_PHYMODE_20   = 0,        /* 20 MHz operation */
195         HAL_HT_PHYMODE_2040 = 1,        /* 20/40 MHz operation */
196 } HAL_HT_PHYMODE;
197
198 typedef enum {
199         HAL_HT_EXTPROTSPACING_20 = 0,       /* 20 MHz spacing */
200         HAL_HT_EXTPROTSPACING_25 = 1,       /* 25 MHz spacing */
201 } HAL_HT_EXTPROTSPACING;
202
203 typedef struct {
204         HAL_HT_MACMODE          ht_macmode;     /* MAC - 20/40 mode */
205         HAL_HT_PHYMODE          ht_phymode;     /* PHY - 20/40 mode */
206         a_int8_t                ht_extoff;      /* ext channel offset */
207         HAL_HT_EXTPROTSPACING   ht_extprotspacing;  /* ext channel protection spacing */
208 } HAL_HT_CWM;
209
210 typedef struct {
211         a_uint8_t ht_txchainmask; /* tx chain mask    */
212         a_uint8_t ht_rxchainmask; /* rx chain mask    */
213 } HAL_HT_MISC;
214
215 typedef struct {
216         HAL_HT_CWM  cwm;
217         HAL_HT_MISC misc;
218 } HAL_HT;
219
220 /* channelFlags */
221 #define CHANNEL_CW_INT  0x0002  /* CW interference detected on channel */
222 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
223 #define CHANNEL_CCK     0x0020  /* CCK channel */
224 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
225 #define CHANNEL_2GHZ    0x0080  /* 2 GHz spectrum channel. */
226 #define CHANNEL_5GHZ    0x0100  /* 5 GHz spectrum channel */
227 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed in the channel */
228 #define CHANNEL_DYN     0x0400  /* dynamic CCK-OFDM channel */
229 #define CHANNEL_XR      0x0800  /* XR channel */
230 #define CHANNEL_STURBO  0x2000  /* Static turbo, no 11a-only usage */
231 #define CHANNEL_HALF    0x4000  /* Half rate channel */
232 #define CHANNEL_QUARTER 0x8000  /* Quarter rate channel */
233 #define CHANNEL_HT20    0x10000 /* HT20 channel */
234 #define CHANNEL_HT40    0x20000 /* HT40 channel */
235 #define CHANNEL_HT40U   0x40000 /* control channel can be upper channel */
236 #define CHANNEL_HT40L   0x80000 /* control channel can be lower channel */
237
238 /* privFlags */
239 #define CHANNEL_INTERFERENCE    0x01
240 #define CHANNEL_DFS             0x02 /* DFS required on channel */
241 #define CHANNEL_4MS_LIMIT       0x04 /* 4msec packet limit on this channel */
242 #define CHANNEL_DFS_CLEAR       0x08 /* if channel has been checked for DFS */
243
244 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
245 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
246 #define CHANNEL_PUREG   (CHANNEL_2GHZ|CHANNEL_OFDM)
247 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
248 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
249 #define CHANNEL_ST      (CHANNEL_T|CHANNEL_STURBO)
250 #define CHANNEL_108G    (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
251 #define CHANNEL_108A    CHANNEL_T
252 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
253
254 #define CHANNEL_G_HT20  (CHANNEL_2GHZ|CHANNEL_HT20)
255 #define CHANNEL_A_HT20  (CHANNEL_5GHZ|CHANNEL_HT20)
256 #define CHANNEL_G_HT40  (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40)
257 #define CHANNEL_A_HT40  (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40)
258 #define CHANNEL_ALL                             \
259         (CHANNEL_OFDM |                         \
260          CHANNEL_CCK |                          \
261          CHANNEL_2GHZ |                         \
262          CHANNEL_5GHZ |                         \
263          CHANNEL_TURBO |                        \
264          CHANNEL_HT20 |                         \
265          CHANNEL_HT40)
266 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL &~ CHANNEL_TURBO)
267
268 typedef struct {
269         a_int32_t    rateCount;
270         a_uint8_t    rateCodeToIndex[HAL_RATE_TABLE_SIZE];
271         struct {
272                 a_uint8_t    valid;
273                 a_uint8_t    phy;
274                 a_int16_t    txPower;
275                 a_int16_t    txPower2Chains;
276                 a_int16_t    txPower3Chains;
277                 a_uint32_t   rateKbps;
278                 a_uint8_t    rateCode;
279                 a_uint8_t    shortPreamble;
280                 a_uint8_t    dot11Rate;
281                 a_uint8_t    controlRate;
282                 a_uint16_t   lpAckDuration;
283                 a_uint16_t   spAckDuration;
284         } info[HAL_RATE_TABLE_SIZE];
285 } HAL_RATE_TABLE;
286
287 typedef struct {
288         a_uint32_t   Tries;
289         a_uint32_t   Rate;
290         a_uint32_t   PktDuration;
291         a_uint32_t   ChSel;
292         a_uint32_t   RateFlags;
293         a_uint32_t   RateIndex;
294         a_uint32_t   TxPowerCap;     /* in 1/2 dBm units */
295 } HAL_11N_RATE_SERIES;
296
297 #else
298
299 typedef struct {
300         a_int32_t    rateCount;
301         a_uint8_t    rateCodeToIndex[HAL_RATE_TABLE_SIZE];
302         struct {
303                 a_uint8_t    valid;
304                 a_uint8_t    phy;
305                 a_uint32_t   rateKbps;
306                 a_uint8_t    rateCode;
307                 a_uint8_t    shortPreamble;
308                 a_uint8_t    dot11Rate;
309                 a_uint8_t    controlRate;
310                 a_uint16_t   lpAckDuration;
311                 a_uint16_t   spAckDuration;
312         } info[HAL_RATE_TABLE_SIZE];
313 } HAL_RATE_TABLE;
314
315 #define HAL_RATESERIES_RTS_CTS    0x0001  /* use rts/cts w/this series */
316 #define HAL_RATESERIES_2040       0x0002  /* use ext channel for series */
317 #define HAL_RATESERIES_HALFGI     0x0004  /* use half-gi for series */
318 #define HAL_RATESERIES_STBC       0x0008  /* use STBC for series */
319
320 typedef struct {
321         a_uint32_t   Tries;
322         a_uint32_t   Rate;
323         a_uint32_t   PktDuration;
324         a_uint32_t   ChSel;
325         a_uint32_t   RateFlags;
326 } HAL_11N_RATE_SERIES;
327
328 #endif
329
330 enum {
331         HAL_MODE_11A    = 0x001,        /* 11a channels */
332         HAL_MODE_TURBO  = 0x002,        /* 11a turbo-only channels */
333         HAL_MODE_11B    = 0x004,        /* 11b channels */
334         HAL_MODE_PUREG  = 0x008,        /* 11g channels (OFDM only) */
335         HAL_MODE_11G    = 0x008,        /* XXX historical */
336         HAL_MODE_108G   = 0x020,        /* 11a+Turbo channels */
337         HAL_MODE_108A   = 0x040,        /* 11g+Turbo channels */
338         HAL_MODE_XR     = 0x100,        /* XR channels */
339         HAL_MODE_11A_HALF_RATE = 0x200,     /* 11A half rate channels */
340         HAL_MODE_11A_QUARTER_RATE = 0x400,  /* 11A quarter rate channels */
341         HAL_MODE_11NG   = 0x4000,           /* 11ng channels */
342         HAL_MODE_11NA   = 0x8000,           /* 11na channels */
343         HAL_MODE_ALL    = 0xffff
344 };
345
346 typedef enum {
347         HAL_KEY_TYPE_CLEAR,
348         HAL_KEY_TYPE_WEP,
349         HAL_KEY_TYPE_AES,
350         HAL_KEY_TYPE_TKIP,
351         HAL_KEY_TYPE_WAPI,
352 } HAL_KEY_TYPE;
353
354 struct ath_desc;
355 struct ath_rx_status;
356
357 struct ath_hal
358 {
359         a_uint32_t ah_magic;
360         HAL_SOFTC ah_sc;
361         adf_os_device_t ah_dev;
362
363         a_uint32_t ah_macVersion;
364         a_uint16_t ah_macRev;
365         a_uint16_t ah_phyRev;
366         const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
367                                                          a_uint32_t mode);
368         void      __ahdecl(*ah_detach)(struct ath_hal*);
369         HAL_BOOL  __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
370                                                   HAL_BOOL incTrigLevel);
371
372         /* Misc Functions */
373         void      __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
374         void      __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
375
376
377         /* Target Transmit Functions */
378         HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
379         a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
380         HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
381         HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t);
382
383         HAL_BOOL  __ahdecl(*ah_abortTxDma)(struct ath_hal *);
384
385         void      __ahdecl(*ah_set11nTxDesc)(struct ath_tx_desc *ds,
386                                              a_uint32_t pktLen, HAL_PKT_TYPE type,
387                                              a_uint32_t txPower, a_uint32_t keyIx,
388                                              HAL_KEY_TYPE keyType,
389                                              a_uint32_t flags);
390         void      __ahdecl(*ah_set11nRateScenario)(struct ath_tx_desc *ds,
391                                                    a_uint32_t durUpdateEn,
392                                                    a_uint32_t rtsctsRate,
393                                                    HAL_11N_RATE_SERIES series[],
394                                                    a_uint32_t nseries, a_uint32_t flags);
395         void      __ahdecl(*ah_set11nAggrFirst)(struct ath_tx_desc *ds, a_uint32_t aggrLen,
396                                                 a_uint32_t numDelims);
397         void      __ahdecl(*ah_set11nAggrMiddle)(struct ath_tx_desc *ds, a_uint32_t numDelims);
398         void      __ahdecl(*ah_set11nAggrLast)(struct ath_tx_desc *ds);
399         void      __ahdecl(*ah_clr11nAggr)(struct ath_tx_desc *ds);
400         void      __ahdecl(*ah_set11nBurstDuration)(struct ath_tx_desc *ds,
401                                                     a_uint32_t burstDuration);
402         void      __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_tx_desc *ds, a_uint32_t vmf);
403
404         HAL_BOOL  __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *,
405                                             a_uint32_t pktLen, a_uint32_t hdrLen,
406                                             HAL_PKT_TYPE type, a_uint32_t txPower,
407                                             a_uint32_t txRate0, a_uint32_t txTries0,
408                                             a_uint32_t keyIx, a_uint32_t flags,
409                                             a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration);
410         HAL_BOOL  __ahdecl(*ah_fillTxDesc)(struct ath_tx_desc *,
411                                            a_uint32_t segLen, HAL_BOOL firstSeg,
412                                            HAL_BOOL lastSeg, const struct ath_tx_desc *);
413         HAL_BOOL  __ahdecl (*ah_fillKeyTxDesc) (struct ath_tx_desc *, HAL_KEY_TYPE);
414         HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_tx_desc *);
415         HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*);
416         void      __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
417         void      __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
418                                                    a_uint32_t filter0, a_uint32_t filter1);
419
420         u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
421
422         /* Target receive Functions */
423         void       __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
424         HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_rx_desc *,
425                                             a_uint32_t size, a_uint32_t flags);
426         HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
427                                             a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
428         HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
429                                                 struct ath_rx_desc *ds, a_uint32_t pa,
430                                                 struct ath_desc *nds,
431                                                 struct ath_rx_status *rx_stats);
432         HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
433         void      __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
434         void      __ahdecl(*ah_enableReceive)(struct ath_hal*);
435
436         /* Interrupt functions */
437         HAL_BOOL  __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
438         HAL_BOOL  __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
439         HAL_INT   __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
440 };
441
442
443 extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC,
444                                                     adf_os_device_t dev,
445                                                     a_uint32_t flags, HAL_STATUS* status);
446
447 extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
448                                                  const HAL_RATE_TABLE *rates,
449                                                  a_uint32_t frameLen,
450                                                  a_uint16_t rateix,
451                                                  HAL_BOOL shortPreamble);
452 #endif /* _ATH_AH_H_ */