11 #define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) (Owl) */
14 HAL_OK = 0, /* No error */
15 HAL_ENXIO = 1, /* No hardware present */
16 HAL_ENOMEM = 2, /* Memory allocation failed */
17 HAL_EIO = 3, /* Hardware didn't respond as expected */
18 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
19 HAL_EEVERSION = 5, /* EEPROM version invalid */
20 HAL_EELOCKED = 6, /* EEPROM unreadable */
21 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
22 HAL_EEREAD = 8, /* EEPROM read problem */
23 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
24 HAL_EESIZE = 10, /* EEPROM size not supported */
25 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
26 HAL_EINVAL = 12, /* Invalid parameter to function */
27 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
28 HAL_ESELFTEST = 14, /* Hardware self-test failed */
29 HAL_EINPROGRESS = 15, /* Operation incomplete */
30 HAL_FULL_RESET = 16, /* Full reset done */
40 HAL_CAP_BSSIDMASK = 1,
41 HAL_CAP_TSF_ADJUST = 2,
45 HAL_CAP_RTS_AGGR_LIMIT = 6,
46 } HAL_CAPABILITY_TYPE;
56 HAL_TX_QUEUE_INACTIVE = 0,
57 HAL_TX_QUEUE_DATA = 1,
58 HAL_TX_QUEUE_BEACON = 2,
60 HAL_TX_QUEUE_PSPOLL = 4,
61 HAL_TX_QUEUE_UAPSD = 5,
71 } HAL_TX_QUEUE_SUBTYPE;
73 #define HAL_NUM_TX_QUEUES 10
76 HAL_PKT_TYPE_NORMAL = 0,
77 HAL_PKT_TYPE_ATIM = 1,
78 HAL_PKT_TYPE_PSPOLL = 2,
79 HAL_PKT_TYPE_BEACON = 3,
80 HAL_PKT_TYPE_PROBE_RESP = 4,
81 HAL_PKT_TYPE_CHIRP = 5,
82 HAL_PKT_TYPE_GRP_POLL = 6,
86 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
87 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
91 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
92 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
93 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
94 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
95 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
96 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
97 HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */
98 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
99 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
101 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors*/
102 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PSPOLL frames */
104 ** PHY "Pseudo bits" should be in the upper 16 bits since the lower
105 ** 16 bits actually correspond to register 0x803c bits
108 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/
112 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */
113 #define CHANNEL_HALF 0x4000 /* Half rate channel */
116 HAL_INT_RX = 0x00000001, /* Non-common mapping */
117 HAL_INT_RXDESC = 0x00000002,
118 HAL_INT_RXNOFRM = 0x00000008,
119 HAL_INT_RXEOL = 0x00000010,
120 HAL_INT_RXORN = 0x00000020,
121 HAL_INT_TX = 0x00000040, /* Non-common mapping */
122 HAL_INT_TXDESC = 0x00000080,
123 HAL_INT_TXURN = 0x00000800,
124 HAL_INT_MIB = 0x00001000,
125 HAL_INT_RXPHY = 0x00004000,
126 HAL_INT_RXKCM = 0x00008000,
127 HAL_INT_SWBA = 0x00010000,
128 HAL_INT_BMISS = 0x00040000,
129 HAL_INT_BNR = 0x00100000, /* Non-common mapping */
130 HAL_INT_GPIO = 0x01000000,
131 HAL_INT_CST = 0x02000000, /* Non-common mapping */
132 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
133 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
134 HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */
135 HAL_INT_GENTIMER =0x08000000, /* Non-common mapping */
137 /* Interrupt bits that map directly to ISR/IMR bits */
138 HAL_INT_COMMON = HAL_INT_RXNOFRM
150 HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */
155 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
156 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
157 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
158 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
162 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
163 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
167 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
168 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
172 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
173 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
174 } HAL_HT_EXTPROTSPACING;
177 HAL_HT_MACMODE ht_macmode; /* MAC - 20/40 mode */
178 HAL_HT_PHYMODE ht_phymode; /* PHY - 20/40 mode */
179 a_int8_t ht_extoff; /* ext channel offset */
180 HAL_HT_EXTPROTSPACING ht_extprotspacing; /* ext channel protection spacing */
184 a_uint8_t ht_txchainmask; /* tx chain mask */
185 a_uint8_t ht_rxchainmask; /* rx chain mask */
194 #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */
195 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
196 #define CHANNEL_CCK 0x0020 /* CCK channel */
197 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
198 #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */
199 #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */
200 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
201 #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */
202 #define CHANNEL_XR 0x0800 /* XR channel */
203 #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */
204 #define CHANNEL_HALF 0x4000 /* Half rate channel */
205 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */
206 #define CHANNEL_HT20 0x10000 /* HT20 channel */
207 #define CHANNEL_HT40 0x20000 /* HT40 channel */
208 #define CHANNEL_HT40U 0x40000 /* control channel can be upper channel */
209 #define CHANNEL_HT40L 0x80000 /* control channel can be lower channel */
212 #define CHANNEL_INTERFERENCE 0x01
213 #define CHANNEL_DFS 0x02 /* DFS required on channel */
214 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
215 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
217 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
218 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
219 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
220 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
221 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
222 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
223 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
224 #define CHANNEL_108A CHANNEL_T
225 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
227 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
228 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
229 #define CHANNEL_G_HT40 (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40)
230 #define CHANNEL_A_HT40 (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40)
231 #define CHANNEL_ALL \
239 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
243 a_uint8_t rateCodeToIndex[32];
248 a_int16_t txPower2Chains;
249 a_int16_t txPower3Chains;
252 a_uint8_t shortPreamble;
254 a_uint8_t controlRate;
255 a_uint16_t lpAckDuration;
256 a_uint16_t spAckDuration;
263 a_uint32_t PktDuration;
265 a_uint32_t RateFlags;
266 a_uint32_t RateIndex;
267 a_uint32_t TxPowerCap; /* in 1/2 dBm units */
268 } HAL_11N_RATE_SERIES;
274 a_uint8_t rateCodeToIndex[32];
280 a_uint8_t shortPreamble;
282 a_uint8_t controlRate;
283 a_uint16_t lpAckDuration;
284 a_uint16_t spAckDuration;
288 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
289 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
290 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
291 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
296 a_uint32_t PktDuration;
298 a_uint32_t RateFlags;
299 } HAL_11N_RATE_SERIES;
304 HAL_MODE_11A = 0x001, /* 11a channels */
305 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
306 HAL_MODE_11B = 0x004, /* 11b channels */
307 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
308 HAL_MODE_11G = 0x008, /* XXX historical */
309 HAL_MODE_108G = 0x020, /* 11a+Turbo channels */
310 HAL_MODE_108A = 0x040, /* 11g+Turbo channels */
311 HAL_MODE_XR = 0x100, /* XR channels */
312 HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
313 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
314 HAL_MODE_11NG = 0x4000, /* 11ng channels */
315 HAL_MODE_11NA = 0x8000, /* 11na channels */
316 HAL_MODE_ALL = 0xffff
328 struct ath_rx_status;
334 HAL_BUS_HANDLE ah_sh;
335 adf_os_device_t ah_dev;
337 a_uint32_t ah_macVersion;
338 a_uint16_t ah_macRev;
339 a_uint16_t ah_phyRev;
340 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
342 void __ahdecl(*ah_detach)(struct ath_hal*);
343 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
344 HAL_BOOL incTrigLevel);
347 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
348 HAL_CAPABILITY_TYPE, a_uint32_t capability,
350 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
352 HAL_BOOL __ahdecl(*ah_updateCTSForBursting)(struct ath_hal *,
353 struct ath_desc *, struct ath_desc *,
354 struct ath_desc *, struct ath_desc *,
355 a_uint32_t, a_uint32_t);
356 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
359 /* Target Transmit Functions */
361 a_uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, a_uint32_t);
362 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
363 a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
364 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
365 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t);
367 HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *);
369 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *ah,
371 a_uint32_t pktLen, HAL_PKT_TYPE type,
372 a_uint32_t txPower, a_uint32_t keyIx,
373 HAL_KEY_TYPE keyType,
375 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *ah,
377 a_uint32_t durUpdateEn,
378 a_uint32_t rtsctsRate,
379 a_uint32_t rtsctsDuration,
380 HAL_11N_RATE_SERIES series[],
381 a_uint32_t nseries, a_uint32_t flags);
382 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah,
383 struct ath_desc *ds, a_uint32_t aggrLen,
384 a_uint32_t numDelims);
385 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
386 struct ath_desc *ds, a_uint32_t numDelims);
387 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
388 struct ath_desc *ds);
389 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
390 struct ath_desc *ds);
391 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,
393 a_uint32_t burstDuration);
394 void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah,
395 struct ath_desc *ds, a_uint32_t vmf);
397 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
398 a_uint32_t pktLen, a_uint32_t hdrLen,
399 HAL_PKT_TYPE type, a_uint32_t txPower,
400 a_uint32_t txRate0, a_uint32_t txTries0,
401 a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags,
402 a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration,
403 a_uint32_t compicvLen, a_uint32_t compivLen,
405 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
406 a_uint32_t segLen, HAL_BOOL firstSeg,
407 HAL_BOOL lastSeg, const struct ath_desc *);
408 HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_hal *, struct ath_desc *, HAL_KEY_TYPE);
409 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc*);
410 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, a_uint32_t *);
411 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
412 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*);
413 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
414 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
415 a_uint32_t filter0, a_uint32_t filter1);
417 a_uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
418 u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
419 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
421 /* Target receive Functions */
422 a_uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
423 void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
424 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
425 a_uint32_t size, a_uint32_t flags);
426 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
427 a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
428 HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
429 struct ath_desc *ds, a_uint32_t pa,
430 struct ath_desc *nds,
431 struct ath_rx_status *rx_stats);
432 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
433 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
434 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
435 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
437 /* Interrupt functions */
438 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
439 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
440 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
441 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
445 extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC,
446 adf_os_device_t dev, HAL_BUS_HANDLE sh,
447 a_uint32_t flags, HAL_STATUS* status);
449 extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *,
452 extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
453 const HAL_RATE_TABLE *rates,
456 HAL_BOOL shortPreamble);
457 #endif /* _ATH_AH_H_ */