target/linux/xburst/patches-2.6.35/001-core.patch

   1 From 2b3ca15058c974f2c20bd057a58a10c414b83fef Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 17 Jul 2010 11:07:51 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip
   5
   6 Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
   7 It also adds the iomem addresses for the different components found on
   8 a JZ4740 SoC.
   9
  10 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
  11 Cc: linux-mips@linux-mips.org
  12 Cc: linux-kernel@vger.kernel.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/1464/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/include/asm/bootinfo.h                   |    6 ++
  17  arch/mips/include/asm/cpu.h                        |    9 +++-
  18  arch/mips/include/asm/mach-jz4740/base.h           |   26 ++++++++++
  19  .../asm/mach-jz4740/cpu-feature-overrides.h        |   51 ++++++++++++++++++++
  20  arch/mips/include/asm/mach-jz4740/war.h            |   25 ++++++++++
  21  arch/mips/kernel/cpu-probe.c                       |   20 ++++++++
  22  arch/mips/mm/tlbex.c                               |    5 ++
  23  7 files changed, 141 insertions(+), 1 deletions(-)
  24  create mode 100644 arch/mips/include/asm/mach-jz4740/base.h
  25  create mode 100644 arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
  26  create mode 100644 arch/mips/include/asm/mach-jz4740/war.h
  27
  28 --- a/arch/mips/include/asm/bootinfo.h
  29 +++ b/arch/mips/include/asm/bootinfo.h
  30 @@ -71,6 +71,12 @@
  31  #define MACH_LEMOTE_LL2F       7
  32  #define MACH_LOONGSON_END      8
  33
  34 +/*
  35 + * Valid machtype for group INGENIC
  36 + */
  37 +#define  MACH_INGENIC_JZ4730   0       /* JZ4730 SOC           */
  38 +#define  MACH_INGENIC_JZ4740   1       /* JZ4740 SOC           */
  39 +
  40  extern char *system_type;
  41  const char *get_system_type(void);
  42
  43 --- a/arch/mips/include/asm/cpu.h
  44 +++ b/arch/mips/include/asm/cpu.h
  45 @@ -34,7 +34,7 @@
  46  #define PRID_COMP_LSI          0x080000
  47  #define PRID_COMP_LEXRA                0x0b0000
  48  #define PRID_COMP_CAVIUM       0x0d0000
  49 -
  50 +#define PRID_COMP_INGENIC      0xd00000
  51
  52  /*
  53   * Assigned values for the product ID register.  In order to detect a
  54 @@ -133,6 +133,12 @@
  55  #define PRID_IMP_CAVIUM_CN52XX 0x0700
  56
  57  /*
  58 + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
  59 + */
  60 +
  61 +#define PRID_IMP_JZRISC        0x0200
  62 +
  63 +/*
  64   * Definitions for 7:0 on legacy processors
  65   */
  66
  67 @@ -219,6 +225,7 @@ enum cpu_type_enum {
  68         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
  69         CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
  70         CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
  71 +       CPU_JZRISC,
  72
  73         /*
  74          * MIPS64 class processors
  75 --- /dev/null
  76 +++ b/arch/mips/include/asm/mach-jz4740/base.h
  77 @@ -0,0 +1,26 @@
  78 +#ifndef __ASM_MACH_JZ4740_BASE_H__
  79 +#define __ASM_MACH_JZ4740_BASE_H__
  80 +
  81 +#define JZ4740_CPM_BASE_ADDR   0x10000000
  82 +#define JZ4740_INTC_BASE_ADDR  0x10001000
  83 +#define JZ4740_WDT_BASE_ADDR   0x10002000
  84 +#define JZ4740_TCU_BASE_ADDR   0x10002010
  85 +#define JZ4740_RTC_BASE_ADDR   0x10003000
  86 +#define JZ4740_GPIO_BASE_ADDR  0x10010000
  87 +#define JZ4740_AIC_BASE_ADDR   0x10020000
  88 +#define JZ4740_MSC_BASE_ADDR   0x10021000
  89 +#define JZ4740_UART0_BASE_ADDR 0x10030000
  90 +#define JZ4740_UART1_BASE_ADDR 0x10031000
  91 +#define JZ4740_I2C_BASE_ADDR   0x10042000
  92 +#define JZ4740_SSI_BASE_ADDR   0x10043000
  93 +#define JZ4740_SADC_BASE_ADDR  0x10070000
  94 +#define JZ4740_EMC_BASE_ADDR   0x13010000
  95 +#define JZ4740_DMAC_BASE_ADDR  0x13020000
  96 +#define JZ4740_UHC_BASE_ADDR   0x13030000
  97 +#define JZ4740_UDC_BASE_ADDR   0x13040000
  98 +#define JZ4740_LCD_BASE_ADDR   0x13050000
  99 +#define JZ4740_SLCD_BASE_ADDR  0x13050000
 100 +#define JZ4740_CIM_BASE_ADDR   0x13060000
 101 +#define JZ4740_IPU_BASE_ADDR   0x13080000
 102 +
 103 +#endif
 104 --- /dev/null
 105 +++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
 106 @@ -0,0 +1,51 @@
 107 +/*
 108 + * This file is subject to the terms and conditions of the GNU General Public
 109 + * License.  See the file "COPYING" in the main directory of this archive
 110 + * for more details.
 111 + *
 112 + */
 113 +#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
 114 +#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
 115 +
 116 +#define cpu_has_tlb 1
 117 +#define cpu_has_4kex           1
 118 +#define cpu_has_3k_cache       0
 119 +#define cpu_has_4k_cache       1
 120 +#define cpu_has_tx39_cache     0
 121 +#define cpu_has_fpu            0
 122 +#define cpu_has_32fpr  0
 123 +#define cpu_has_counter                0
 124 +#define cpu_has_watch          1
 125 +#define cpu_has_divec          1
 126 +#define cpu_has_vce            0
 127 +#define cpu_has_cache_cdex_p   0
 128 +#define cpu_has_cache_cdex_s   0
 129 +#define cpu_has_prefetch       1
 130 +#define cpu_has_mcheck 1
 131 +#define cpu_has_ejtag 1
 132 +#define cpu_has_llsc           1
 133 +#define cpu_has_mips16 0
 134 +#define cpu_has_mdmx 0
 135 +#define cpu_has_mips3d 0
 136 +#define cpu_has_smartmips 0
 137 +#define kernel_uses_llsc       1
 138 +#define cpu_has_vtag_icache    1
 139 +#define cpu_has_dc_aliases     0
 140 +#define cpu_has_ic_fills_f_dc  0
 141 +#define cpu_has_pindexed_dcache 0
 142 +#define cpu_has_mips32r1       1
 143 +#define cpu_has_mips32r2       0
 144 +#define cpu_has_mips64r1       0
 145 +#define cpu_has_mips64r2       0
 146 +#define cpu_has_dsp            0
 147 +#define cpu_has_mipsmt         0
 148 +#define cpu_has_userlocal      0
 149 +#define cpu_has_nofpuex 0
 150 +#define cpu_has_64bits         0
 151 +#define cpu_has_64bit_zero_reg 0
 152 +#define cpu_has_inclusive_pcaches 0
 153 +
 154 +#define cpu_dcache_line_size() 32
 155 +#define cpu_icache_line_size() 32
 156 +
 157 +#endif
 158 --- /dev/null
 159 +++ b/arch/mips/include/asm/mach-jz4740/war.h
 160 @@ -0,0 +1,25 @@
 161 +/*
 162 + * This file is subject to the terms and conditions of the GNU General Public
 163 + * License.  See the file "COPYING" in the main directory of this archive
 164 + * for more details.
 165 + *
 166 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
 167 + */
 168 +#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
 169 +#define __ASM_MIPS_MACH_JZ4740_WAR_H
 170 +
 171 +#define R4600_V1_INDEX_ICACHEOP_WAR    0
 172 +#define R4600_V1_HIT_CACHEOP_WAR       0
 173 +#define R4600_V2_HIT_CACHEOP_WAR       0
 174 +#define R5432_CP0_INTERRUPT_WAR                0
 175 +#define BCM1250_M3_WAR                 0
 176 +#define SIBYTE_1956_WAR                        0
 177 +#define MIPS4K_ICACHE_REFILL_WAR       0
 178 +#define MIPS_CACHE_SYNC_WAR            0
 179 +#define TX49XX_ICACHE_INDEX_INV_WAR    0
 180 +#define RM9000_CDEX_SMP_WAR            0
 181 +#define ICACHE_REFILLS_WORKAROUND_WAR  0
 182 +#define R10000_LLSC_WAR                        0
 183 +#define MIPS34K_MISSED_ITLB_WAR                0
 184 +
 185 +#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
 186 --- a/arch/mips/kernel/cpu-probe.c
 187 +++ b/arch/mips/kernel/cpu-probe.c
 188 @@ -187,6 +187,7 @@ void __init check_wait(void)
 189         case CPU_BCM6358:
 190         case CPU_CAVIUM_OCTEON:
 191         case CPU_CAVIUM_OCTEON_PLUS:
 192 +       case CPU_JZRISC:
 193                 cpu_wait = r4k_wait;
 194                 break;
 195
 196 @@ -956,6 +957,22 @@ platform:
 197         }
 198  }
 199
 200 +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 201 +{
 202 +       decode_configs(c);
 203 +       /* JZRISC does not implement the CP0 counter. */
 204 +       c->options &= ~MIPS_CPU_COUNTER;
 205 +       switch (c->processor_id & 0xff00) {
 206 +       case PRID_IMP_JZRISC:
 207 +               c->cputype = CPU_JZRISC;
 208 +               __cpu_name[cpu] = "Ingenic JZRISC";
 209 +               break;
 210 +       default:
 211 +               panic("Unknown Ingenic Processor ID!");
 212 +               break;
 213 +       }
 214 +}
 215 +
 216  const char *__cpu_name[NR_CPUS];
 217  const char *__elf_platform;
 218
 219 @@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void)
 220         case PRID_COMP_CAVIUM:
 221                 cpu_probe_cavium(c, cpu);
 222                 break;
 223 +       case PRID_COMP_INGENIC:
 224 +               cpu_probe_ingenic(c, cpu);
 225 +               break;
 226         }
 227
 228         BUG_ON(!__cpu_name[cpu]);
 229 --- a/arch/mips/mm/tlbex.c
 230 +++ b/arch/mips/mm/tlbex.c
 231 @@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_en
 232                 tlbw(p);
 233                 break;
 234
 235 +       case CPU_JZRISC:
 236 +               tlbw(p);
 237 +               uasm_i_nop(p);
 238 +               break;
 239 +
 240         default:
 241                 panic("No TLB refill handler yet (CPU type: %d)",
 242                       current_cpu_data.cputype);