2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO SD/MMC controller driver
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 #include <linux/mmc/host.h>
18 #include <linux/irq.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/delay.h>
23 #include <linux/scatterlist.h>
24 #include <linux/clk.h>
25 #include <linux/mmc/jz4740_mmc.h>
27 #include <linux/gpio.h>
28 #include <asm/mach-jz4740/gpio.h>
29 #include <asm/cacheflush.h>
30 #include <linux/dma-mapping.h>
32 #define JZ_REG_MMC_STRPCL 0x00
33 #define JZ_REG_MMC_STATUS 0x04
34 #define JZ_REG_MMC_CLKRT 0x08
35 #define JZ_REG_MMC_CMDAT 0x0C
36 #define JZ_REG_MMC_RESTO 0x10
37 #define JZ_REG_MMC_RDTO 0x14
38 #define JZ_REG_MMC_BLKLEN 0x18
39 #define JZ_REG_MMC_NOB 0x1C
40 #define JZ_REG_MMC_SNOB 0x20
41 #define JZ_REG_MMC_IMASK 0x24
42 #define JZ_REG_MMC_IREG 0x28
43 #define JZ_REG_MMC_CMD 0x2C
44 #define JZ_REG_MMC_ARG 0x30
45 #define JZ_REG_MMC_RESP_FIFO 0x34
46 #define JZ_REG_MMC_RXFIFO 0x38
47 #define JZ_REG_MMC_TXFIFO 0x3C
49 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
50 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
51 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
52 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
53 #define JZ_MMC_STRPCL_RESET BIT(3)
54 #define JZ_MMC_STRPCL_START_OP BIT(2)
55 #define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
56 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
57 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
60 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
61 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
62 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
63 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
64 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
65 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
66 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
67 #define JZ_MMC_STATUS_CLK_EN BIT(8)
68 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
69 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
70 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
71 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
72 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
73 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
74 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
75 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
77 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
78 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
81 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
82 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
83 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
84 #define JZ_MMC_CMDAT_INIT BIT(7)
85 #define JZ_MMC_CMDAT_BUSY BIT(6)
86 #define JZ_MMC_CMDAT_STREAM BIT(5)
87 #define JZ_MMC_CMDAT_WRITE BIT(4)
88 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
89 #define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
90 #define JZ_MMC_CMDAT_RSP_R1 1
91 #define JZ_MMC_CMDAT_RSP_R2 2
92 #define JZ_MMC_CMDAT_RSP_R3 3
94 #define JZ_MMC_IRQ_SDIO BIT(7)
95 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
96 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
97 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
98 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
99 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
102 #define JZ_MMC_CLK_RATE 24000000
104 struct jz4740_mmc_host {
105 struct mmc_host *mmc;
106 struct platform_device *pdev;
107 struct jz4740_mmc_platform_data *pdata;
113 struct resource *mem;
115 struct mmc_request *req;
116 struct mmc_command *cmd;
124 struct timer_list clock_timer;
125 struct timer_list timeout_timer;
129 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
131 static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
134 spin_lock_irqsave(&host->lock, flags);
136 host->irq_mask &= ~irq;
137 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
139 spin_unlock_irqrestore(&host->lock, flags);
142 static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
145 spin_lock_irqsave(&host->lock, flags);
147 host->irq_mask |= irq;
148 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
150 spin_unlock_irqrestore(&host->lock, flags);
153 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
155 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
158 val |= JZ_MMC_STRPCL_START_OP;
160 writew(val, host->base + JZ_REG_MMC_STRPCL);
163 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
166 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
168 status = readl(host->base + JZ_REG_MMC_STATUS);
169 } while (status & JZ_MMC_STATUS_CLK_EN);
173 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
175 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
177 while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
180 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
182 struct mmc_request *req;
185 spin_lock_irqsave(&host->lock, flags);
189 spin_unlock_irqrestore(&host->lock, flags);
194 /* if (req->cmd->error != 0) {
196 jz4740_mmc_reset(host);
199 mmc_request_done(host->mmc, req);
202 static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
203 struct scatterlist *sg;
204 uint32_t *sg_pointer;
206 unsigned int timeout;
209 for (sg = data->sg; sg; sg = sg_next(sg)) {
210 sg_pointer = sg_virt(sg);
217 status = readw(host->base + JZ_REG_MMC_IREG);
218 } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
222 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
224 writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
225 writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
226 writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
227 writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
228 writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
229 writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
230 writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
231 writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
238 status = readw(host->base + JZ_REG_MMC_IREG);
239 } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
243 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
246 writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
251 data->bytes_xfered += sg->length;
254 status = readl(host->base + JZ_REG_MMC_STATUS);
255 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
258 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
261 status = readl(host->base + JZ_REG_MMC_STATUS);
262 } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
265 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
269 host->req->cmd->error = -ETIMEDOUT;
270 data->error = -ETIMEDOUT;
273 if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
274 host->req->cmd->error = -ETIMEDOUT;
275 data->error = -ETIMEDOUT;
277 host->req->cmd->error = -EILSEQ;
278 data->error = -EILSEQ;
282 static void jz4740_mmc_timeout(unsigned long data)
284 struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
287 spin_lock_irqsave(&host->lock, flags);
288 if (!host->waiting) {
289 spin_unlock_irqrestore(&host->lock, flags);
295 spin_unlock_irqrestore(&host->lock, flags);
297 host->req->cmd->error = -ETIMEDOUT;
298 jz4740_mmc_request_done(host);
301 static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
302 struct scatterlist *sg;
303 uint32_t *sg_pointer;
307 unsigned int timeout;
309 for (sg = data->sg; sg; sg = sg_next(sg)) {
310 sg_pointer = sg_virt(sg);
317 status = readw(host->base + JZ_REG_MMC_IREG);
318 } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ) && --timeout);
320 if (unlikely(timeout == 0))
323 writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
325 sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
326 sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
327 sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
328 sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
329 sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
330 sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
331 sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
332 sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
341 status = readl(host->base + JZ_REG_MMC_STATUS);
342 } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout);
344 if (unlikely(timeout == 0))
347 *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
352 d = readl(host->base + JZ_REG_MMC_RXFIFO);
353 memcpy(sg_pointer, &d, i);
355 data->bytes_xfered += sg->length;
357 flush_dcache_page(sg_page(sg));
360 status = readl(host->base + JZ_REG_MMC_STATUS);
361 if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
364 /* For whatever reason there is sometime one word more in the fifo then
366 while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
367 d = readl(host->base + JZ_REG_MMC_RXFIFO);
368 status = readl(host->base + JZ_REG_MMC_STATUS);
372 host->req->cmd->error = -ETIMEDOUT;
373 data->error = -ETIMEDOUT;
376 if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
377 host->req->cmd->error = -ETIMEDOUT;
378 data->error = -ETIMEDOUT;
380 host->req->cmd->error = -EILSEQ;
381 data->error = -EILSEQ;
385 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
387 struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
389 if (host->cmd->error)
390 jz4740_mmc_request_done(host);
392 jz4740_mmc_cmd_done(host);
397 static irqreturn_t jz_mmc_irq(int irq, void *devid)
399 struct jz4740_mmc_host *host = devid;
400 uint16_t irq_reg, status, tmp;
402 irqreturn_t ret = IRQ_HANDLED;
404 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
407 spin_lock_irqsave(&host->lock, flags);
408 irq_reg &= ~host->irq_mask;
409 spin_unlock_irqrestore(&host->lock, flags);
411 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
412 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
414 if (tmp != irq_reg) {
415 dev_warn(&host->pdev->dev, "Sparse irq: %x\n", tmp & ~irq_reg);
416 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
419 if (irq_reg & JZ_MMC_IRQ_SDIO) {
420 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
421 mmc_signal_sdio_irq(host->mmc);
424 if (!host->req || !host->cmd) {
429 spin_lock_irqsave(&host->lock, flags);
430 if (!host->waiting) {
431 spin_unlock_irqrestore(&host->lock, flags);
436 spin_unlock_irqrestore(&host->lock, flags);
438 del_timer(&host->timeout_timer);
440 status = readl(host->base + JZ_REG_MMC_STATUS);
442 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
443 host->cmd->error = -ETIMEDOUT;
444 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
445 host->cmd->error = -EIO;
446 } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
447 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
448 host->cmd->data->error = -EIO;
449 } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
450 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
451 host->cmd->data->error = -EIO;
454 if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
455 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
456 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
457 ret = IRQ_WAKE_THREAD;
463 writew(0xff, host->base + JZ_REG_MMC_IREG);
467 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
469 int real_rate = host->max_clock;
470 jz4740_mmc_clock_disable(host);
472 while ((real_rate >> 1) >= rate && div < 7) {
476 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
478 writew(div, host->base + JZ_REG_MMC_CLKRT);
483 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
487 if (cmd->flags & MMC_RSP_136) {
488 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
489 for (i = 0; i < 4; ++i) {
490 cmd->resp[i] = tmp << 24;
491 cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
492 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
493 cmd->resp[i] |= tmp >> 8;
496 cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
497 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
498 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
502 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
504 uint32_t cmdat = host->cmdat;
506 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
507 jz4740_mmc_clock_disable(host);
511 if (cmd->flags & MMC_RSP_BUSY)
512 cmdat |= JZ_MMC_CMDAT_BUSY;
514 switch (mmc_resp_type(cmd)) {
517 cmdat |= JZ_MMC_CMDAT_RSP_R1;
520 cmdat |= JZ_MMC_CMDAT_RSP_R2;
523 cmdat |= JZ_MMC_CMDAT_RSP_R3;
530 cmdat |= JZ_MMC_CMDAT_DATA_EN;
531 if (cmd->data->flags & MMC_DATA_WRITE)
532 cmdat |= JZ_MMC_CMDAT_WRITE;
533 if (cmd->data->flags & MMC_DATA_STREAM)
534 cmdat |= JZ_MMC_CMDAT_STREAM;
536 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
537 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
540 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
541 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
542 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
545 jz4740_mmc_clock_enable(host, 1);
546 mod_timer(&host->timeout_timer, 4*HZ);
549 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
552 struct mmc_command *cmd = host->req->cmd;
553 struct mmc_request *req = host->req;
554 unsigned int timeout = 100000;
555 status = readl(host->base + JZ_REG_MMC_STATUS);
557 if (cmd->flags & MMC_RSP_PRESENT)
558 jz4740_mmc_read_response(host, cmd);
561 if (cmd->data->flags & MMC_DATA_READ)
562 jz4740_mmc_read_data(host, cmd->data);
564 jz4740_mmc_write_data(host, cmd->data);
568 jz4740_mmc_send_command(host, req->stop);
570 status = readl(host->base + JZ_REG_MMC_STATUS);
571 } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0 && --timeout);
572 writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
576 req->stop->error = -ETIMEDOUT;
578 jz4740_mmc_request_done(host);
581 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
583 struct jz4740_mmc_host *host = mmc_priv(mmc);
587 writew(0xffff, host->base + JZ_REG_MMC_IREG);
589 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
590 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
591 jz4740_mmc_send_command(host, req->cmd);
595 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
597 struct jz4740_mmc_host *host = mmc_priv(mmc);
599 jz4740_mmc_set_clock_rate(host, ios->clock);
601 switch(ios->power_mode) {
603 jz4740_mmc_reset(host);
604 if (gpio_is_valid(host->pdata->gpio_power))
605 gpio_set_value(host->pdata->gpio_power,
606 !host->pdata->power_active_low);
607 host->cmdat |= JZ_MMC_CMDAT_INIT;
608 clk_enable(host->clk);
613 if (gpio_is_valid(host->pdata->gpio_power))
614 gpio_set_value(host->pdata->gpio_power,
615 host->pdata->power_active_low);
616 clk_disable(host->clk);
620 switch(ios->bus_width) {
621 case MMC_BUS_WIDTH_1:
622 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
624 case MMC_BUS_WIDTH_4:
625 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
628 dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
632 static int jz4740_mmc_get_ro(struct mmc_host *mmc)
634 struct jz4740_mmc_host *host = mmc_priv(mmc);
635 if (!gpio_is_valid(host->pdata->gpio_read_only))
638 return gpio_get_value(host->pdata->gpio_read_only) ^
639 host->pdata->read_only_active_low;
642 static int jz4740_mmc_get_cd(struct mmc_host *mmc)
644 struct jz4740_mmc_host *host = mmc_priv(mmc);
645 if (!gpio_is_valid(host->pdata->gpio_card_detect))
648 return gpio_get_value(host->pdata->gpio_card_detect) ^
649 host->pdata->card_detect_active_low;
652 static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
654 struct jz4740_mmc_host *host = devid;
656 mmc_detect_change(host->mmc, HZ / 3);
661 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
663 struct jz4740_mmc_host *host = mmc_priv(mmc);
665 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
667 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
670 static const struct mmc_host_ops jz4740_mmc_ops = {
671 .request = jz4740_mmc_request,
672 .set_ios = jz4740_mmc_set_ios,
673 .get_ro = jz4740_mmc_get_ro,
674 .get_cd = jz4740_mmc_get_cd,
675 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
678 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
679 JZ_GPIO_BULK_PIN(MSC_CMD),
680 JZ_GPIO_BULK_PIN(MSC_CLK),
681 JZ_GPIO_BULK_PIN(MSC_DATA0),
682 JZ_GPIO_BULK_PIN(MSC_DATA1),
683 JZ_GPIO_BULK_PIN(MSC_DATA2),
684 JZ_GPIO_BULK_PIN(MSC_DATA3),
687 static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
690 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
695 if (gpio_is_valid(pdata->gpio_card_detect)) {
696 ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
698 dev_err(&pdev->dev, "Failed to request detect change gpio\n");
701 gpio_direction_input(pdata->gpio_card_detect);
704 if (gpio_is_valid(pdata->gpio_read_only)) {
705 ret = gpio_request(pdata->gpio_read_only, "MMC read only");
707 dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
708 goto err_free_gpio_card_detect;
710 gpio_direction_input(pdata->gpio_read_only);
713 if (gpio_is_valid(pdata->gpio_power)) {
714 ret = gpio_request(pdata->gpio_power, "MMC power");
716 dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
717 goto err_free_gpio_read_only;
719 gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
724 err_free_gpio_read_only:
725 if (gpio_is_valid(pdata->gpio_read_only))
726 gpio_free(pdata->gpio_read_only);
727 err_free_gpio_card_detect:
728 if (gpio_is_valid(pdata->gpio_card_detect))
729 gpio_free(pdata->gpio_card_detect);
734 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
736 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
741 if (gpio_is_valid(pdata->gpio_power))
742 gpio_free(pdata->gpio_power);
743 if (gpio_is_valid(pdata->gpio_read_only))
744 gpio_free(pdata->gpio_read_only);
745 if (gpio_is_valid(pdata->gpio_card_detect))
746 gpio_free(pdata->gpio_card_detect);
749 static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
752 struct mmc_host *mmc;
753 struct jz4740_mmc_host *host;
754 struct jz4740_mmc_platform_data *pdata;
756 pdata = pdev->dev.platform_data;
758 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
761 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
765 host = mmc_priv(mmc);
767 host->irq = platform_get_irq(pdev, 0);
771 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
775 host->clk = clk_get(&pdev->dev, "mmc");
778 dev_err(&pdev->dev, "Failed to get mmc clock\n");
782 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 dev_err(&pdev->dev, "Failed to get base platform memory\n");
790 host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
795 dev_err(&pdev->dev, "Failed to request base memory region\n");
799 host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
803 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
804 goto err_release_mem_region;
807 if (pdata && pdata->data_1bit)
808 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
810 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
813 dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
817 ret = jz4740_mmc_request_gpios(pdev);
819 goto err_gpio_bulk_free;
821 mmc->ops = &jz4740_mmc_ops;
822 mmc->f_min = JZ_MMC_CLK_RATE / 128;
823 mmc->f_max = JZ_MMC_CLK_RATE;
824 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
825 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
826 mmc->caps |= MMC_CAP_SDIO_IRQ;
827 mmc->max_seg_size = 4096;
828 mmc->max_phys_segs = 128;
830 mmc->max_blk_size = (1 << 10) - 1;
831 mmc->max_blk_count = (1 << 15) - 1;
832 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
837 host->max_clock = JZ_MMC_CLK_RATE;
838 spin_lock_init(&host->lock);
839 host->irq_mask = 0xffff;
841 host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
843 if (host->card_detect_irq < 0) {
844 dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
846 ret = request_irq(host->card_detect_irq,
847 jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
850 dev_err(&pdev->dev, "Failed to request card detect irq");
855 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
857 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
858 goto err_free_card_detect_irq;
861 jz4740_mmc_reset(host);
862 jz4740_mmc_clock_disable(host);
863 setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
865 platform_set_drvdata(pdev, host);
866 ret = mmc_add_host(mmc);
869 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
872 printk("JZ SD/MMC card driver registered\n");
877 free_irq(host->irq, host);
878 err_free_card_detect_irq:
879 if (host->card_detect_irq >= 0)
880 free_irq(host->card_detect_irq, host);
882 jz4740_mmc_free_gpios(pdev);
884 if (pdata && pdata->data_1bit)
885 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
887 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
890 err_release_mem_region:
891 release_mem_region(host->mem->start, resource_size(host->mem));
895 platform_set_drvdata(pdev, NULL);
901 static int jz4740_mmc_remove(struct platform_device *pdev)
903 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
904 struct jz4740_mmc_platform_data *pdata = host->pdata;
906 del_timer_sync(&host->timeout_timer);
907 jz4740_mmc_disable_irq(host, 0xff);
908 jz4740_mmc_reset(host);
910 mmc_remove_host(host->mmc);
912 free_irq(host->irq, host);
913 if (host->card_detect_irq >= 0)
914 free_irq(host->card_detect_irq, host);
916 jz4740_mmc_free_gpios(pdev);
917 if (pdata && pdata->data_1bit)
918 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
920 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
923 release_mem_region(host->mem->start, resource_size(host->mem));
927 platform_set_drvdata(pdev, NULL);
928 mmc_free_host(host->mmc);
934 static int jz4740_mmc_suspend(struct device *dev)
936 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
937 struct jz4740_mmc_platform_data *pdata = host->pdata;
939 mmc_suspend_host(host->mmc, PMSG_SUSPEND);
941 if (pdata && pdata->data_1bit)
942 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
944 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
949 static int jz4740_mmc_resume(struct device *dev)
951 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
952 struct jz4740_mmc_platform_data *pdata = host->pdata;
954 if (pdata && pdata->data_1bit)
955 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
957 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
959 mmc_resume_host(host->mmc);
964 struct dev_pm_ops jz4740_mmc_pm_ops = {
965 .suspend = jz4740_mmc_suspend,
966 .resume = jz4740_mmc_resume,
967 .poweroff = jz4740_mmc_suspend,
968 .restore = jz4740_mmc_resume,
971 #define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
973 #define jz4740_mmc_PM_OPS NULL
976 static struct platform_driver jz4740_mmc_driver = {
977 .probe = jz4740_mmc_probe,
978 .remove = jz4740_mmc_remove,
980 .name = "jz4740-mmc",
981 .owner = THIS_MODULE,
982 .pm = jz4740_mmc_PM_OPS,
986 static int __init jz4740_mmc_init(void) {
987 return platform_driver_register(&jz4740_mmc_driver);
989 module_init(jz4740_mmc_init);
991 static void __exit jz4740_mmc_exit(void) {
992 platform_driver_unregister(&jz4740_mmc_driver);
994 module_exit(jz4740_mmc_exit);
996 MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
997 MODULE_LICENSE("GPL");
998 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");