target/linux/sunxi/patches-4.9/0053-stmmac-form-4-13.patch

   1 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
   2 +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
   3 @@ -145,6 +145,17 @@ config DWMAC_SUNXI
   4           This selects Allwinner SoC glue layer support for the
   5           stmmac device driver. This driver is used for A20/A31
   6           GMAC ethernet controller.
   7 +
   8 +config DWMAC_SUN8I
   9 +       tristate "Allwinner sun8i GMAC support"
  10 +       default ARCH_SUNXI
  11 +       depends on OF && (ARCH_SUNXI || COMPILE_TEST)
  12 +       ---help---
  13 +         Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
  14 +
  15 +         This selects Allwinner SoC glue layer support for the
  16 +         stmmac device driver. This driver is used for H3/A83T/A64
  17 +         EMAC ethernet controller.
  18  endif
  19
  20  config STMMAC_PCI
  21 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
  22 +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
  23 @@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA)   += dwmac-alt
  24  obj-$(CONFIG_DWMAC_STI)                += dwmac-sti.o
  25  obj-$(CONFIG_DWMAC_STM32)      += dwmac-stm32.o
  26  obj-$(CONFIG_DWMAC_SUNXI)      += dwmac-sunxi.o
  27 +obj-$(CONFIG_DWMAC_SUN8I)      += dwmac-sun8i.o
  28  obj-$(CONFIG_DWMAC_DWC_QOS_ETH)        += dwmac-dwc-qos-eth.o
  29  obj-$(CONFIG_DWMAC_GENERIC)    += dwmac-generic.o
  30  stmmac-platform-objs:= stmmac_platform.o
  31 --- a/drivers/net/ethernet/stmicro/stmmac/common.h
  32 +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
  33 @@ -549,9 +549,11 @@ extern const struct stmmac_hwtimestamp s
  34  extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
  35
  36  struct mac_link {
  37 -       int port;
  38 -       int duplex;
  39 -       int speed;
  40 +       u32 speed_mask;
  41 +       u32 speed10;
  42 +       u32 speed100;
  43 +       u32 speed1000;
  44 +       u32 duplex;
  45  };
  46
  47  struct mii_regs {
  48 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
  49 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
  50 @@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(st
  51         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
  52         ctrl |= val << reg_shift;
  53
  54 -       if (dwmac->f2h_ptp_ref_clk) {
  55 +       if (dwmac->f2h_ptp_ref_clk ||
  56 +           phymode == PHY_INTERFACE_MODE_MII ||
  57 +           phymode == PHY_INTERFACE_MODE_GMII ||
  58 +           phymode == PHY_INTERFACE_MODE_SGMII) {
  59                 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
  60                 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
  61                             &module);
  62 --- /dev/null
  63 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
  64 @@ -0,0 +1,1007 @@
  65 +/*
  66 + * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
  67 + *
  68 + * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
  69 + *
  70 + * This program is free software; you can redistribute it and/or modify
  71 + * it under the terms of the GNU General Public License as published by
  72 + * the Free Software Foundation; either version 2 of the License, or
  73 + * (at your option) any later version.
  74 + *
  75 + * This program is distributed in the hope that it will be useful,
  76 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  77 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  78 + * GNU General Public License for more details.
  79 + */
  80 +
  81 +#include <linux/clk.h>
  82 +#include <linux/io.h>
  83 +#include <linux/iopoll.h>
  84 +#include <linux/mfd/syscon.h>
  85 +#include <linux/module.h>
  86 +#include <linux/of_device.h>
  87 +#include <linux/of_mdio.h>
  88 +#include <linux/of_net.h>
  89 +#include <linux/phy.h>
  90 +#include <linux/platform_device.h>
  91 +#include <linux/regulator/consumer.h>
  92 +#include <linux/regmap.h>
  93 +#include <linux/stmmac.h>
  94 +
  95 +#include "stmmac.h"
  96 +#include "stmmac_platform.h"
  97 +
  98 +/* General notes on dwmac-sun8i:
  99 + * Locking: no locking is necessary in this file because all necessary locking
 100 + *             is done in the "stmmac files"
 101 + */
 102 +
 103 +/* struct emac_variant - Descrive dwmac-sun8i hardware variant
 104 + * @default_syscon_value:      The default value of the EMAC register in syscon
 105 + *                             This value is used for disabling properly EMAC
 106 + *                             and used as a good starting value in case of the
 107 + *                             boot process(uboot) leave some stuff.
 108 + * @internal_phy:              Does the MAC embed an internal PHY
 109 + * @support_mii:               Does the MAC handle MII
 110 + * @support_rmii:              Does the MAC handle RMII
 111 + * @support_rgmii:             Does the MAC handle RGMII
 112 + */
 113 +struct emac_variant {
 114 +       u32 default_syscon_value;
 115 +       int internal_phy;
 116 +       bool support_mii;
 117 +       bool support_rmii;
 118 +       bool support_rgmii;
 119 +};
 120 +
 121 +/* struct sunxi_priv_data - hold all sunxi private data
 122 + * @tx_clk:    reference to MAC TX clock
 123 + * @ephy_clk:  reference to the optional EPHY clock for the internal PHY
 124 + * @regulator: reference to the optional regulator
 125 + * @rst_ephy:  reference to the optional EPHY reset for the internal PHY
 126 + * @variant:   reference to the current board variant
 127 + * @regmap:    regmap for using the syscon
 128 + * @use_internal_phy: Does the current PHY choice imply using the internal PHY
 129 + */
 130 +struct sunxi_priv_data {
 131 +       struct clk *tx_clk;
 132 +       struct clk *ephy_clk;
 133 +       struct regulator *regulator;
 134 +       struct reset_control *rst_ephy;
 135 +       const struct emac_variant *variant;
 136 +       struct regmap *regmap;
 137 +       bool use_internal_phy;
 138 +};
 139 +
 140 +static const struct emac_variant emac_variant_h3 = {
 141 +       .default_syscon_value = 0x58000,
 142 +       .internal_phy = PHY_INTERFACE_MODE_MII,
 143 +       .support_mii = true,
 144 +       .support_rmii = true,
 145 +       .support_rgmii = true
 146 +};
 147 +
 148 +static const struct emac_variant emac_variant_v3s = {
 149 +       .default_syscon_value = 0x38000,
 150 +       .internal_phy = PHY_INTERFACE_MODE_MII,
 151 +       .support_mii = true
 152 +};
 153 +
 154 +static const struct emac_variant emac_variant_a83t = {
 155 +       .default_syscon_value = 0,
 156 +       .internal_phy = 0,
 157 +       .support_mii = true,
 158 +       .support_rgmii = true
 159 +};
 160 +
 161 +static const struct emac_variant emac_variant_a64 = {
 162 +       .default_syscon_value = 0,
 163 +       .internal_phy = 0,
 164 +       .support_mii = true,
 165 +       .support_rmii = true,
 166 +       .support_rgmii = true
 167 +};
 168 +
 169 +#define EMAC_BASIC_CTL0 0x00
 170 +#define EMAC_BASIC_CTL1 0x04
 171 +#define EMAC_INT_STA    0x08
 172 +#define EMAC_INT_EN     0x0C
 173 +#define EMAC_TX_CTL0    0x10
 174 +#define EMAC_TX_CTL1    0x14
 175 +#define EMAC_TX_FLOW_CTL        0x1C
 176 +#define EMAC_TX_DESC_LIST 0x20
 177 +#define EMAC_RX_CTL0    0x24
 178 +#define EMAC_RX_CTL1    0x28
 179 +#define EMAC_RX_DESC_LIST 0x34
 180 +#define EMAC_RX_FRM_FLT 0x38
 181 +#define EMAC_MDIO_CMD   0x48
 182 +#define EMAC_MDIO_DATA  0x4C
 183 +#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
 184 +#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
 185 +#define EMAC_TX_DMA_STA 0xB0
 186 +#define EMAC_TX_CUR_DESC        0xB4
 187 +#define EMAC_TX_CUR_BUF 0xB8
 188 +#define EMAC_RX_DMA_STA 0xC0
 189 +#define EMAC_RX_CUR_DESC        0xC4
 190 +#define EMAC_RX_CUR_BUF 0xC8
 191 +
 192 +/* Use in EMAC_BASIC_CTL0 */
 193 +#define EMAC_DUPLEX_FULL       BIT(0)
 194 +#define EMAC_LOOPBACK          BIT(1)
 195 +#define EMAC_SPEED_1000 0
 196 +#define EMAC_SPEED_100 (0x03 << 2)
 197 +#define EMAC_SPEED_10 (0x02 << 2)
 198 +
 199 +/* Use in EMAC_BASIC_CTL1 */
 200 +#define EMAC_BURSTLEN_SHIFT            24
 201 +
 202 +/* Used in EMAC_RX_FRM_FLT */
 203 +#define EMAC_FRM_FLT_RXALL              BIT(0)
 204 +#define EMAC_FRM_FLT_CTL                BIT(13)
 205 +#define EMAC_FRM_FLT_MULTICAST          BIT(16)
 206 +
 207 +/* Used in RX_CTL1*/
 208 +#define EMAC_RX_MD              BIT(1)
 209 +#define EMAC_RX_TH_MASK                GENMASK(4, 5)
 210 +#define EMAC_RX_TH_32          0
 211 +#define EMAC_RX_TH_64          (0x1 << 4)
 212 +#define EMAC_RX_TH_96          (0x2 << 4)
 213 +#define EMAC_RX_TH_128         (0x3 << 4)
 214 +#define EMAC_RX_DMA_EN  BIT(30)
 215 +#define EMAC_RX_DMA_START       BIT(31)
 216 +
 217 +/* Used in TX_CTL1*/
 218 +#define EMAC_TX_MD              BIT(1)
 219 +#define EMAC_TX_NEXT_FRM        BIT(2)
 220 +#define EMAC_TX_TH_MASK                GENMASK(8, 10)
 221 +#define EMAC_TX_TH_64          0
 222 +#define EMAC_TX_TH_128         (0x1 << 8)
 223 +#define EMAC_TX_TH_192         (0x2 << 8)
 224 +#define EMAC_TX_TH_256         (0x3 << 8)
 225 +#define EMAC_TX_DMA_EN  BIT(30)
 226 +#define EMAC_TX_DMA_START       BIT(31)
 227 +
 228 +/* Used in RX_CTL0 */
 229 +#define EMAC_RX_RECEIVER_EN             BIT(31)
 230 +#define EMAC_RX_DO_CRC BIT(27)
 231 +#define EMAC_RX_FLOW_CTL_EN             BIT(16)
 232 +
 233 +/* Used in TX_CTL0 */
 234 +#define EMAC_TX_TRANSMITTER_EN  BIT(31)
 235 +
 236 +/* Used in EMAC_TX_FLOW_CTL */
 237 +#define EMAC_TX_FLOW_CTL_EN             BIT(0)
 238 +
 239 +/* Used in EMAC_INT_STA */
 240 +#define EMAC_TX_INT             BIT(0)
 241 +#define EMAC_TX_DMA_STOP_INT    BIT(1)
 242 +#define EMAC_TX_BUF_UA_INT      BIT(2)
 243 +#define EMAC_TX_TIMEOUT_INT     BIT(3)
 244 +#define EMAC_TX_UNDERFLOW_INT   BIT(4)
 245 +#define EMAC_TX_EARLY_INT       BIT(5)
 246 +#define EMAC_RX_INT             BIT(8)
 247 +#define EMAC_RX_BUF_UA_INT      BIT(9)
 248 +#define EMAC_RX_DMA_STOP_INT    BIT(10)
 249 +#define EMAC_RX_TIMEOUT_INT     BIT(11)
 250 +#define EMAC_RX_OVERFLOW_INT    BIT(12)
 251 +#define EMAC_RX_EARLY_INT       BIT(13)
 252 +#define EMAC_RGMII_STA_INT      BIT(16)
 253 +
 254 +#define MAC_ADDR_TYPE_DST BIT(31)
 255 +
 256 +/* H3 specific bits for EPHY */
 257 +#define H3_EPHY_ADDR_SHIFT     20
 258 +#define H3_EPHY_CLK_SEL                BIT(18) /* 1: 24MHz, 0: 25MHz */
 259 +#define H3_EPHY_LED_POL                BIT(17) /* 1: active low, 0: active high */
 260 +#define H3_EPHY_SHUTDOWN       BIT(16) /* 1: shutdown, 0: power up */
 261 +#define H3_EPHY_SELECT         BIT(15) /* 1: internal PHY, 0: external PHY */
 262 +
 263 +/* H3/A64 specific bits */
 264 +#define SYSCON_RMII_EN         BIT(13) /* 1: enable RMII (overrides EPIT) */
 265 +
 266 +/* Generic system control EMAC_CLK bits */
 267 +#define SYSCON_ETXDC_MASK              GENMASK(2, 0)
 268 +#define SYSCON_ETXDC_SHIFT             10
 269 +#define SYSCON_ERXDC_MASK              GENMASK(4, 0)
 270 +#define SYSCON_ERXDC_SHIFT             5
 271 +/* EMAC PHY Interface Type */
 272 +#define SYSCON_EPIT                    BIT(2) /* 1: RGMII, 0: MII */
 273 +#define SYSCON_ETCS_MASK               GENMASK(1, 0)
 274 +#define SYSCON_ETCS_MII                0x0
 275 +#define SYSCON_ETCS_EXT_GMII   0x1
 276 +#define SYSCON_ETCS_INT_GMII   0x2
 277 +#define SYSCON_EMAC_REG                0x30
 278 +
 279 +/* sun8i_dwmac_dma_reset() - reset the EMAC
 280 + * Called from stmmac via stmmac_dma_ops->reset
 281 + */
 282 +static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
 283 +{
 284 +       writel(0, ioaddr + EMAC_RX_CTL1);
 285 +       writel(0, ioaddr + EMAC_TX_CTL1);
 286 +       writel(0, ioaddr + EMAC_RX_FRM_FLT);
 287 +       writel(0, ioaddr + EMAC_RX_DESC_LIST);
 288 +       writel(0, ioaddr + EMAC_TX_DESC_LIST);
 289 +       writel(0, ioaddr + EMAC_INT_EN);
 290 +       writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 291 +       return 0;
 292 +}
 293 +
 294 +/* sun8i_dwmac_dma_init() - initialize the EMAC
 295 + * Called from stmmac via stmmac_dma_ops->init
 296 + */
 297 +static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
 298 +                                struct stmmac_dma_cfg *dma_cfg,
 299 +                                u32 dma_tx, u32 dma_rx, int atds)
 300 +{
 301 +       /* Write TX and RX descriptors address */
 302 +       writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
 303 +       writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
 304 +
 305 +       writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
 306 +       writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 307 +}
 308 +
 309 +/* sun8i_dwmac_dump_regs() - Dump EMAC address space
 310 + * Called from stmmac_dma_ops->dump_regs
 311 + * Used for ethtool
 312 + */
 313 +static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
 314 +{
 315 +       int i;
 316 +
 317 +       for (i = 0; i < 0xC8; i += 4) {
 318 +               if (i == 0x32 || i == 0x3C)
 319 +                       continue;
 320 +               reg_space[i / 4] = readl(ioaddr + i);
 321 +       }
 322 +}
 323 +
 324 +/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
 325 + * Called from stmmac_ops->dump_regs
 326 + * Used for ethtool
 327 + */
 328 +static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
 329 +                                     u32 *reg_space)
 330 +{
 331 +       int i;
 332 +       void __iomem *ioaddr = hw->pcsr;
 333 +
 334 +       for (i = 0; i < 0xC8; i += 4) {
 335 +               if (i == 0x32 || i == 0x3C)
 336 +                       continue;
 337 +               reg_space[i / 4] = readl(ioaddr + i);
 338 +       }
 339 +}
 340 +
 341 +static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
 342 +{
 343 +       writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
 344 +}
 345 +
 346 +static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
 347 +{
 348 +       writel(0, ioaddr + EMAC_INT_EN);
 349 +}
 350 +
 351 +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
 352 +{
 353 +       u32 v;
 354 +
 355 +       v = readl(ioaddr + EMAC_TX_CTL1);
 356 +       v |= EMAC_TX_DMA_START;
 357 +       v |= EMAC_TX_DMA_EN;
 358 +       writel(v, ioaddr + EMAC_TX_CTL1);
 359 +}
 360 +
 361 +static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
 362 +{
 363 +       u32 v;
 364 +
 365 +       v = readl(ioaddr + EMAC_TX_CTL1);
 366 +       v |= EMAC_TX_DMA_START;
 367 +       v |= EMAC_TX_DMA_EN;
 368 +       writel(v, ioaddr + EMAC_TX_CTL1);
 369 +}
 370 +
 371 +static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
 372 +{
 373 +       u32 v;
 374 +
 375 +       v = readl(ioaddr + EMAC_TX_CTL1);
 376 +       v &= ~EMAC_TX_DMA_EN;
 377 +       writel(v, ioaddr + EMAC_TX_CTL1);
 378 +}
 379 +
 380 +static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
 381 +{
 382 +       u32 v;
 383 +
 384 +       v = readl(ioaddr + EMAC_RX_CTL1);
 385 +       v |= EMAC_RX_DMA_START;
 386 +       v |= EMAC_RX_DMA_EN;
 387 +       writel(v, ioaddr + EMAC_RX_CTL1);
 388 +}
 389 +
 390 +static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
 391 +{
 392 +       u32 v;
 393 +
 394 +       v = readl(ioaddr + EMAC_RX_CTL1);
 395 +       v &= ~EMAC_RX_DMA_EN;
 396 +       writel(v, ioaddr + EMAC_RX_CTL1);
 397 +}
 398 +
 399 +static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
 400 +                                    struct stmmac_extra_stats *x, u32 chan)
 401 +{
 402 +       u32 v;
 403 +       int ret = 0;
 404 +
 405 +       v = readl(ioaddr + EMAC_INT_STA);
 406 +
 407 +       if (v & EMAC_TX_INT) {
 408 +               ret |= handle_tx;
 409 +               x->tx_normal_irq_n++;
 410 +       }
 411 +
 412 +       if (v & EMAC_TX_DMA_STOP_INT)
 413 +               x->tx_process_stopped_irq++;
 414 +
 415 +       if (v & EMAC_TX_BUF_UA_INT)
 416 +               x->tx_process_stopped_irq++;
 417 +
 418 +       if (v & EMAC_TX_TIMEOUT_INT)
 419 +               ret |= tx_hard_error;
 420 +
 421 +       if (v & EMAC_TX_UNDERFLOW_INT) {
 422 +               ret |= tx_hard_error;
 423 +               x->tx_undeflow_irq++;
 424 +       }
 425 +
 426 +       if (v & EMAC_TX_EARLY_INT)
 427 +               x->tx_early_irq++;
 428 +
 429 +       if (v & EMAC_RX_INT) {
 430 +               ret |= handle_rx;
 431 +               x->rx_normal_irq_n++;
 432 +       }
 433 +
 434 +       if (v & EMAC_RX_BUF_UA_INT)
 435 +               x->rx_buf_unav_irq++;
 436 +
 437 +       if (v & EMAC_RX_DMA_STOP_INT)
 438 +               x->rx_process_stopped_irq++;
 439 +
 440 +       if (v & EMAC_RX_TIMEOUT_INT)
 441 +               ret |= tx_hard_error;
 442 +
 443 +       if (v & EMAC_RX_OVERFLOW_INT) {
 444 +               ret |= tx_hard_error;
 445 +               x->rx_overflow_irq++;
 446 +       }
 447 +
 448 +       if (v & EMAC_RX_EARLY_INT)
 449 +               x->rx_early_irq++;
 450 +
 451 +       if (v & EMAC_RGMII_STA_INT)
 452 +               x->irq_rgmii_n++;
 453 +
 454 +       writel(v, ioaddr + EMAC_INT_STA);
 455 +
 456 +       return ret;
 457 +}
 458 +
 459 +static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
 460 +                                          int rxmode, int rxfifosz)
 461 +{
 462 +       u32 v;
 463 +
 464 +       v = readl(ioaddr + EMAC_TX_CTL1);
 465 +       if (txmode == SF_DMA_MODE) {
 466 +               v |= EMAC_TX_MD;
 467 +               /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
 468 +                * comment is
 469 +                * "Operating on second frame increase the performance
 470 +                * especially when transmit store-and-forward is used."
 471 +                */
 472 +               v |= EMAC_TX_NEXT_FRM;
 473 +       } else {
 474 +               v &= ~EMAC_TX_MD;
 475 +               v &= ~EMAC_TX_TH_MASK;
 476 +               if (txmode < 64)
 477 +                       v |= EMAC_TX_TH_64;
 478 +               else if (txmode < 128)
 479 +                       v |= EMAC_TX_TH_128;
 480 +               else if (txmode < 192)
 481 +                       v |= EMAC_TX_TH_192;
 482 +               else if (txmode < 256)
 483 +                       v |= EMAC_TX_TH_256;
 484 +       }
 485 +       writel(v, ioaddr + EMAC_TX_CTL1);
 486 +
 487 +       v = readl(ioaddr + EMAC_RX_CTL1);
 488 +       if (rxmode == SF_DMA_MODE) {
 489 +               v |= EMAC_RX_MD;
 490 +       } else {
 491 +               v &= ~EMAC_RX_MD;
 492 +               v &= ~EMAC_RX_TH_MASK;
 493 +               if (rxmode < 32)
 494 +                       v |= EMAC_RX_TH_32;
 495 +               else if (rxmode < 64)
 496 +                       v |= EMAC_RX_TH_64;
 497 +               else if (rxmode < 96)
 498 +                       v |= EMAC_RX_TH_96;
 499 +               else if (rxmode < 128)
 500 +                       v |= EMAC_RX_TH_128;
 501 +       }
 502 +       writel(v, ioaddr + EMAC_RX_CTL1);
 503 +}
 504 +
 505 +static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
 506 +       .reset = sun8i_dwmac_dma_reset,
 507 +       .init = sun8i_dwmac_dma_init,
 508 +       .dump_regs = sun8i_dwmac_dump_regs,
 509 +       .dma_mode = sun8i_dwmac_dma_operation_mode,
 510 +       .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
 511 +       .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
 512 +       .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
 513 +       .start_tx = sun8i_dwmac_dma_start_tx,
 514 +       .stop_tx = sun8i_dwmac_dma_stop_tx,
 515 +       .start_rx = sun8i_dwmac_dma_start_rx,
 516 +       .stop_rx = sun8i_dwmac_dma_stop_rx,
 517 +       .dma_interrupt = sun8i_dwmac_dma_interrupt,
 518 +};
 519 +
 520 +static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
 521 +{
 522 +       struct sunxi_priv_data *gmac = priv;
 523 +       int ret;
 524 +
 525 +       if (gmac->regulator) {
 526 +               ret = regulator_enable(gmac->regulator);
 527 +               if (ret) {
 528 +                       dev_err(&pdev->dev, "Fail to enable regulator\n");
 529 +                       return ret;
 530 +               }
 531 +       }
 532 +
 533 +       ret = clk_prepare_enable(gmac->tx_clk);
 534 +       if (ret) {
 535 +               if (gmac->regulator)
 536 +                       regulator_disable(gmac->regulator);
 537 +               dev_err(&pdev->dev, "Could not enable AHB clock\n");
 538 +               return ret;
 539 +       }
 540 +
 541 +       return 0;
 542 +}
 543 +
 544 +static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
 545 +{
 546 +       void __iomem *ioaddr = hw->pcsr;
 547 +       u32 v;
 548 +
 549 +       v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
 550 +       writel(v, ioaddr + EMAC_BASIC_CTL1);
 551 +}
 552 +
 553 +static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
 554 +{
 555 +       u32 t, r;
 556 +
 557 +       t = readl(ioaddr + EMAC_TX_CTL0);
 558 +       r = readl(ioaddr + EMAC_RX_CTL0);
 559 +       if (enable) {
 560 +               t |= EMAC_TX_TRANSMITTER_EN;
 561 +               r |= EMAC_RX_RECEIVER_EN;
 562 +       } else {
 563 +               t &= ~EMAC_TX_TRANSMITTER_EN;
 564 +               r &= ~EMAC_RX_RECEIVER_EN;
 565 +       }
 566 +       writel(t, ioaddr + EMAC_TX_CTL0);
 567 +       writel(r, ioaddr + EMAC_RX_CTL0);
 568 +}
 569 +
 570 +/* Set MAC address at slot reg_n
 571 + * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
 572 + * If addr is NULL, clear the slot
 573 + */
 574 +static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
 575 +                                     unsigned char *addr,
 576 +                                     unsigned int reg_n)
 577 +{
 578 +       void __iomem *ioaddr = hw->pcsr;
 579 +       u32 v;
 580 +
 581 +       if (!addr) {
 582 +               writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
 583 +               return;
 584 +       }
 585 +
 586 +       stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 587 +                           EMAC_MACADDR_LO(reg_n));
 588 +       if (reg_n > 0) {
 589 +               v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
 590 +               v |= MAC_ADDR_TYPE_DST;
 591 +               writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
 592 +       }
 593 +}
 594 +
 595 +static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
 596 +                                     unsigned char *addr,
 597 +                                     unsigned int reg_n)
 598 +{
 599 +       void __iomem *ioaddr = hw->pcsr;
 600 +
 601 +       stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 602 +                           EMAC_MACADDR_LO(reg_n));
 603 +}
 604 +
 605 +/* caution this function must return non 0 to work */
 606 +static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
 607 +{
 608 +       void __iomem *ioaddr = hw->pcsr;
 609 +       u32 v;
 610 +
 611 +       v = readl(ioaddr + EMAC_RX_CTL0);
 612 +       v |= EMAC_RX_DO_CRC;
 613 +       writel(v, ioaddr + EMAC_RX_CTL0);
 614 +
 615 +       return 1;
 616 +}
 617 +
 618 +static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
 619 +                                  struct net_device *dev)
 620 +{
 621 +       void __iomem *ioaddr = hw->pcsr;
 622 +       u32 v;
 623 +       int i = 1;
 624 +       struct netdev_hw_addr *ha;
 625 +       int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
 626 +
 627 +       v = EMAC_FRM_FLT_CTL;
 628 +
 629 +       if (dev->flags & IFF_PROMISC) {
 630 +               v = EMAC_FRM_FLT_RXALL;
 631 +       } else if (dev->flags & IFF_ALLMULTI) {
 632 +               v |= EMAC_FRM_FLT_MULTICAST;
 633 +       } else if (macaddrs <= hw->unicast_filter_entries) {
 634 +               if (!netdev_mc_empty(dev)) {
 635 +                       netdev_for_each_mc_addr(ha, dev) {
 636 +                               sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 637 +                               i++;
 638 +                       }
 639 +               }
 640 +               if (!netdev_uc_empty(dev)) {
 641 +                       netdev_for_each_uc_addr(ha, dev) {
 642 +                               sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 643 +                               i++;
 644 +                       }
 645 +               }
 646 +       } else {
 647 +               netdev_info(dev, "Too many address, switching to promiscuous\n");
 648 +               v = EMAC_FRM_FLT_RXALL;
 649 +       }
 650 +
 651 +       /* Disable unused address filter slots */
 652 +       while (i < hw->unicast_filter_entries)
 653 +               sun8i_dwmac_set_umac_addr(hw, NULL, i++);
 654 +
 655 +       writel(v, ioaddr + EMAC_RX_FRM_FLT);
 656 +}
 657 +
 658 +static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
 659 +                                 unsigned int duplex, unsigned int fc,
 660 +                                 unsigned int pause_time, u32 tx_cnt)
 661 +{
 662 +       void __iomem *ioaddr = hw->pcsr;
 663 +       u32 v;
 664 +
 665 +       v = readl(ioaddr + EMAC_RX_CTL0);
 666 +       if (fc == FLOW_AUTO)
 667 +               v |= EMAC_RX_FLOW_CTL_EN;
 668 +       else
 669 +               v &= ~EMAC_RX_FLOW_CTL_EN;
 670 +       writel(v, ioaddr + EMAC_RX_CTL0);
 671 +
 672 +       v = readl(ioaddr + EMAC_TX_FLOW_CTL);
 673 +       if (fc == FLOW_AUTO)
 674 +               v |= EMAC_TX_FLOW_CTL_EN;
 675 +       else
 676 +               v &= ~EMAC_TX_FLOW_CTL_EN;
 677 +       writel(v, ioaddr + EMAC_TX_FLOW_CTL);
 678 +}
 679 +
 680 +static int sun8i_dwmac_reset(struct stmmac_priv *priv)
 681 +{
 682 +       u32 v;
 683 +       int err;
 684 +
 685 +       v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
 686 +       writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
 687 +
 688 +       /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
 689 +        * need more if no cable plugged. 100ms seems OK
 690 +        */
 691 +       err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
 692 +                                !(v & 0x01), 100, 100000);
 693 +
 694 +       if (err) {
 695 +               dev_err(priv->device, "EMAC reset timeout\n");
 696 +               return -EFAULT;
 697 +       }
 698 +       return 0;
 699 +}
 700 +
 701 +static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
 702 +{
 703 +       struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 704 +       struct device_node *node = priv->device->of_node;
 705 +       int ret;
 706 +       u32 reg, val;
 707 +
 708 +       regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
 709 +       reg = gmac->variant->default_syscon_value;
 710 +       if (reg != val)
 711 +               dev_warn(priv->device,
 712 +                        "Current syscon value is not the default %x (expect %x)\n",
 713 +                        val, reg);
 714 +
 715 +       if (gmac->variant->internal_phy) {
 716 +               if (!gmac->use_internal_phy) {
 717 +                       /* switch to external PHY interface */
 718 +                       reg &= ~H3_EPHY_SELECT;
 719 +               } else {
 720 +                       reg |= H3_EPHY_SELECT;
 721 +                       reg &= ~H3_EPHY_SHUTDOWN;
 722 +                       dev_dbg(priv->device, "Select internal_phy %x\n", reg);
 723 +
 724 +                       if (of_property_read_bool(priv->plat->phy_node,
 725 +                                                 "allwinner,leds-active-low"))
 726 +                               reg |= H3_EPHY_LED_POL;
 727 +                       else
 728 +                               reg &= ~H3_EPHY_LED_POL;
 729 +
 730 +                       /* Force EPHY xtal frequency to 24MHz. */
 731 +                       reg |= H3_EPHY_CLK_SEL;
 732 +
 733 +                       ret = of_mdio_parse_addr(priv->device,
 734 +                                                priv->plat->phy_node);
 735 +                       if (ret < 0) {
 736 +                               dev_err(priv->device, "Could not parse MDIO addr\n");
 737 +                               return ret;
 738 +                       }
 739 +                       /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
 740 +                        * address. No need to mask it again.
 741 +                        */
 742 +                       reg |= ret << H3_EPHY_ADDR_SHIFT;
 743 +               }
 744 +       }
 745 +
 746 +       if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
 747 +               if (val % 100) {
 748 +                       dev_err(priv->device, "tx-delay must be a multiple of 100\n");
 749 +                       return -EINVAL;
 750 +               }
 751 +               val /= 100;
 752 +               dev_dbg(priv->device, "set tx-delay to %x\n", val);
 753 +               if (val <= SYSCON_ETXDC_MASK) {
 754 +                       reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
 755 +                       reg |= (val << SYSCON_ETXDC_SHIFT);
 756 +               } else {
 757 +                       dev_err(priv->device, "Invalid TX clock delay: %d\n",
 758 +                               val);
 759 +                       return -EINVAL;
 760 +               }
 761 +       }
 762 +
 763 +       if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
 764 +               if (val % 100) {
 765 +                       dev_err(priv->device, "rx-delay must be a multiple of 100\n");
 766 +                       return -EINVAL;
 767 +               }
 768 +               val /= 100;
 769 +               dev_dbg(priv->device, "set rx-delay to %x\n", val);
 770 +               if (val <= SYSCON_ERXDC_MASK) {
 771 +                       reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
 772 +                       reg |= (val << SYSCON_ERXDC_SHIFT);
 773 +               } else {
 774 +                       dev_err(priv->device, "Invalid RX clock delay: %d\n",
 775 +                               val);
 776 +                       return -EINVAL;
 777 +               }
 778 +       }
 779 +
 780 +       /* Clear interface mode bits */
 781 +       reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
 782 +       if (gmac->variant->support_rmii)
 783 +               reg &= ~SYSCON_RMII_EN;
 784 +
 785 +       switch (priv->plat->interface) {
 786 +       case PHY_INTERFACE_MODE_MII:
 787 +               /* default */
 788 +               break;
 789 +       case PHY_INTERFACE_MODE_RGMII:
 790 +               reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
 791 +               break;
 792 +       case PHY_INTERFACE_MODE_RMII:
 793 +               reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
 794 +               break;
 795 +       default:
 796 +               dev_err(priv->device, "Unsupported interface mode: %s",
 797 +                       phy_modes(priv->plat->interface));
 798 +               return -EINVAL;
 799 +       }
 800 +
 801 +       regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
 802 +
 803 +       return 0;
 804 +}
 805 +
 806 +static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
 807 +{
 808 +       u32 reg = gmac->variant->default_syscon_value;
 809 +
 810 +       regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
 811 +}
 812 +
 813 +static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
 814 +{
 815 +       struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 816 +       int ret;
 817 +
 818 +       if (!gmac->use_internal_phy)
 819 +               return 0;
 820 +
 821 +       ret = clk_prepare_enable(gmac->ephy_clk);
 822 +       if (ret) {
 823 +               dev_err(priv->device, "Cannot enable ephy\n");
 824 +               return ret;
 825 +       }
 826 +
 827 +       /* Make sure the EPHY is properly reseted, as U-Boot may leave
 828 +        * it at deasserted state, and thus it may fail to reset EMAC.
 829 +        */
 830 +       reset_control_assert(gmac->rst_ephy);
 831 +
 832 +       ret = reset_control_deassert(gmac->rst_ephy);
 833 +       if (ret) {
 834 +               dev_err(priv->device, "Cannot deassert ephy\n");
 835 +               clk_disable_unprepare(gmac->ephy_clk);
 836 +               return ret;
 837 +       }
 838 +
 839 +       return 0;
 840 +}
 841 +
 842 +static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
 843 +{
 844 +       if (!gmac->use_internal_phy)
 845 +               return 0;
 846 +
 847 +       clk_disable_unprepare(gmac->ephy_clk);
 848 +       reset_control_assert(gmac->rst_ephy);
 849 +       return 0;
 850 +}
 851 +
 852 +/* sun8i_power_phy() - Activate the PHY:
 853 + * In case of error, no need to call sun8i_unpower_phy(),
 854 + * it will be called anyway by sun8i_dwmac_exit()
 855 + */
 856 +static int sun8i_power_phy(struct stmmac_priv *priv)
 857 +{
 858 +       int ret;
 859 +
 860 +       ret = sun8i_dwmac_power_internal_phy(priv);
 861 +       if (ret)
 862 +               return ret;
 863 +
 864 +       ret = sun8i_dwmac_set_syscon(priv);
 865 +       if (ret)
 866 +               return ret;
 867 +
 868 +       /* After changing syscon value, the MAC need reset or it will use
 869 +        * the last value (and so the last PHY set.
 870 +        */
 871 +       ret = sun8i_dwmac_reset(priv);
 872 +       if (ret)
 873 +               return ret;
 874 +       return 0;
 875 +}
 876 +
 877 +static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
 878 +{
 879 +       sun8i_dwmac_unset_syscon(gmac);
 880 +       sun8i_dwmac_unpower_internal_phy(gmac);
 881 +}
 882 +
 883 +static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
 884 +{
 885 +       struct sunxi_priv_data *gmac = priv;
 886 +
 887 +       sun8i_unpower_phy(gmac);
 888 +
 889 +       clk_disable_unprepare(gmac->tx_clk);
 890 +
 891 +       if (gmac->regulator)
 892 +               regulator_disable(gmac->regulator);
 893 +}
 894 +
 895 +static const struct stmmac_ops sun8i_dwmac_ops = {
 896 +       .core_init = sun8i_dwmac_core_init,
 897 +       .set_mac = sun8i_dwmac_set_mac,
 898 +       .dump_regs = sun8i_dwmac_dump_mac_regs,
 899 +       .rx_ipc = sun8i_dwmac_rx_ipc_enable,
 900 +       .set_filter = sun8i_dwmac_set_filter,
 901 +       .flow_ctrl = sun8i_dwmac_flow_ctrl,
 902 +       .set_umac_addr = sun8i_dwmac_set_umac_addr,
 903 +       .get_umac_addr = sun8i_dwmac_get_umac_addr,
 904 +};
 905 +
 906 +static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
 907 +{
 908 +       struct mac_device_info *mac;
 909 +       struct stmmac_priv *priv = ppriv;
 910 +       int ret;
 911 +
 912 +       mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
 913 +       if (!mac)
 914 +               return NULL;
 915 +
 916 +       ret = sun8i_power_phy(priv);
 917 +       if (ret)
 918 +               return NULL;
 919 +
 920 +       mac->pcsr = priv->ioaddr;
 921 +       mac->mac = &sun8i_dwmac_ops;
 922 +       mac->dma = &sun8i_dwmac_dma_ops;
 923 +
 924 +       /* The loopback bit seems to be re-set when link change
 925 +        * Simply mask it each time
 926 +        * Speed 10/100/1000 are set in BIT(2)/BIT(3)
 927 +        */
 928 +       mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
 929 +       mac->link.speed10 = EMAC_SPEED_10;
 930 +       mac->link.speed100 = EMAC_SPEED_100;
 931 +       mac->link.speed1000 = EMAC_SPEED_1000;
 932 +       mac->link.duplex = EMAC_DUPLEX_FULL;
 933 +       mac->mii.addr = EMAC_MDIO_CMD;
 934 +       mac->mii.data = EMAC_MDIO_DATA;
 935 +       mac->mii.reg_shift = 4;
 936 +       mac->mii.reg_mask = GENMASK(8, 4);
 937 +       mac->mii.addr_shift = 12;
 938 +       mac->mii.addr_mask = GENMASK(16, 12);
 939 +       mac->mii.clk_csr_shift = 20;
 940 +       mac->mii.clk_csr_mask = GENMASK(22, 20);
 941 +       mac->unicast_filter_entries = 8;
 942 +
 943 +       /* Synopsys Id is not available */
 944 +       priv->synopsys_id = 0;
 945 +
 946 +       return mac;
 947 +}
 948 +
 949 +static int sun8i_dwmac_probe(struct platform_device *pdev)
 950 +{
 951 +       struct plat_stmmacenet_data *plat_dat;
 952 +       struct stmmac_resources stmmac_res;
 953 +       struct sunxi_priv_data *gmac;
 954 +       struct device *dev = &pdev->dev;
 955 +       int ret;
 956 +
 957 +       ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 958 +       if (ret)
 959 +               return ret;
 960 +
 961 +       plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 962 +       if (IS_ERR(plat_dat))
 963 +               return PTR_ERR(plat_dat);
 964 +
 965 +       gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
 966 +       if (!gmac)
 967 +               return -ENOMEM;
 968 +
 969 +       gmac->variant = of_device_get_match_data(&pdev->dev);
 970 +       if (!gmac->variant) {
 971 +               dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
 972 +               return -EINVAL;
 973 +       }
 974 +
 975 +       gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
 976 +       if (IS_ERR(gmac->tx_clk)) {
 977 +               dev_err(dev, "Could not get TX clock\n");
 978 +               return PTR_ERR(gmac->tx_clk);
 979 +       }
 980 +
 981 +       /* Optional regulator for PHY */
 982 +       gmac->regulator = devm_regulator_get_optional(dev, "phy");
 983 +       if (IS_ERR(gmac->regulator)) {
 984 +               if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
 985 +                       return -EPROBE_DEFER;
 986 +               dev_info(dev, "No regulator found\n");
 987 +               gmac->regulator = NULL;
 988 +       }
 989 +
 990 +       gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 991 +                                                      "syscon");
 992 +       if (IS_ERR(gmac->regmap)) {
 993 +               ret = PTR_ERR(gmac->regmap);
 994 +               dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
 995 +               return ret;
 996 +       }
 997 +
 998 +       plat_dat->interface = of_get_phy_mode(dev->of_node);
 999 +       if (plat_dat->interface == gmac->variant->internal_phy) {
1000 +               dev_info(&pdev->dev, "Will use internal PHY\n");
1001 +               gmac->use_internal_phy = true;
1002 +               gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
1003 +               if (IS_ERR(gmac->ephy_clk)) {
1004 +                       ret = PTR_ERR(gmac->ephy_clk);
1005 +                       dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
1006 +                       return -EINVAL;
1007 +               }
1008 +
1009 +               gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
1010 +               if (IS_ERR(gmac->rst_ephy)) {
1011 +                       ret = PTR_ERR(gmac->rst_ephy);
1012 +                       if (ret == -EPROBE_DEFER)
1013 +                               return ret;
1014 +                       dev_err(&pdev->dev, "No EPHY reset control found %d\n",
1015 +                               ret);
1016 +                       return -EINVAL;
1017 +               }
1018 +       } else {
1019 +               dev_info(&pdev->dev, "Will use external PHY\n");
1020 +               gmac->use_internal_phy = false;
1021 +       }
1022 +
1023 +       /* platform data specifying hardware features and callbacks.
1024 +        * hardware features were copied from Allwinner drivers.
1025 +        */
1026 +       plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1027 +       plat_dat->tx_coe = 1;
1028 +       plat_dat->has_sun8i = true;
1029 +       plat_dat->bsp_priv = gmac;
1030 +       plat_dat->init = sun8i_dwmac_init;
1031 +       plat_dat->exit = sun8i_dwmac_exit;
1032 +       plat_dat->setup = sun8i_dwmac_setup;
1033 +
1034 +       ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1035 +       if (ret)
1036 +               return ret;
1037 +
1038 +       ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1039 +       if (ret)
1040 +               sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
1041 +
1042 +       return ret;
1043 +}
1044 +
1045 +static const struct of_device_id sun8i_dwmac_match[] = {
1046 +       { .compatible = "allwinner,sun8i-h3-emac",
1047 +               .data = &emac_variant_h3 },
1048 +       { .compatible = "allwinner,sun8i-v3s-emac",
1049 +               .data = &emac_variant_v3s },
1050 +       { .compatible = "allwinner,sun8i-a83t-emac",
1051 +               .data = &emac_variant_a83t },
1052 +       { .compatible = "allwinner,sun50i-a64-emac",
1053 +               .data = &emac_variant_a64 },
1054 +       { }
1055 +};
1056 +MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1057 +
1058 +static struct platform_driver sun8i_dwmac_driver = {
1059 +       .probe  = sun8i_dwmac_probe,
1060 +       .remove = stmmac_pltfr_remove,
1061 +       .driver = {
1062 +               .name           = "dwmac-sun8i",
1063 +               .pm             = &stmmac_pltfr_pm_ops,
1064 +               .of_match_table = sun8i_dwmac_match,
1065 +       },
1066 +};
1067 +module_platform_driver(sun8i_dwmac_driver);
1068 +
1069 +MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1070 +MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1071 +MODULE_LICENSE("GPL");
1072 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
1073 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
1074 @@ -45,15 +45,17 @@ static void dwmac1000_core_init(struct m
1075         if (hw->ps) {
1076                 value |= GMAC_CONTROL_TE;
1077
1078 -               if (hw->ps == SPEED_1000) {
1079 -                       value &= ~GMAC_CONTROL_PS;
1080 -               } else {
1081 -                       value |= GMAC_CONTROL_PS;
1082 -
1083 -                       if (hw->ps == SPEED_10)
1084 -                               value &= ~GMAC_CONTROL_FES;
1085 -                       else
1086 -                               value |= GMAC_CONTROL_FES;
1087 +               value &= ~hw->link.speed_mask;
1088 +               switch (hw->ps) {
1089 +               case SPEED_1000:
1090 +                       value |= hw->link.speed1000;
1091 +                       break;
1092 +               case SPEED_100:
1093 +                       value |= hw->link.speed100;
1094 +                       break;
1095 +               case SPEED_10:
1096 +                       value |= hw->link.speed10;
1097 +                       break;
1098                 }
1099         }
1100
1101 @@ -531,9 +533,11 @@ struct mac_device_info *dwmac1000_setup(
1102         mac->mac = &dwmac1000_ops;
1103         mac->dma = &dwmac1000_dma_ops;
1104
1105 -       mac->link.port = GMAC_CONTROL_PS;
1106         mac->link.duplex = GMAC_CONTROL_DM;
1107 -       mac->link.speed = GMAC_CONTROL_FES;
1108 +       mac->link.speed10 = GMAC_CONTROL_PS;
1109 +       mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
1110 +       mac->link.speed1000 = 0;
1111 +       mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
1112         mac->mii.addr = GMAC_MII_ADDR;
1113         mac->mii.data = GMAC_MII_DATA;
1114         mac->mii.addr_shift = 11;
1115 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
1116 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
1117 @@ -205,8 +205,8 @@ static void dwmac1000_dump_dma_regs(void
1118  {
1119         int i;
1120
1121 -       for (i = 0; i < 22; i++)
1122 -               if ((i < 9) || (i > 17))
1123 +       for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++)
1124 +               if ((i < 12) || (i > 17))
1125                         reg_space[DMA_BUS_MODE / 4 + i] =
1126                                 readl(ioaddr + DMA_BUS_MODE + i * 4);
1127  }
1128 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
1129 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
1130 @@ -175,9 +175,11 @@ struct mac_device_info *dwmac100_setup(v
1131         mac->mac = &dwmac100_ops;
1132         mac->dma = &dwmac100_dma_ops;
1133
1134 -       mac->link.port = MAC_CONTROL_PS;
1135         mac->link.duplex = MAC_CONTROL_F;
1136 -       mac->link.speed = 0;
1137 +       mac->link.speed10 = 0;
1138 +       mac->link.speed100 = 0;
1139 +       mac->link.speed1000 = 0;
1140 +       mac->link.speed_mask = MAC_CONTROL_PS;
1141         mac->mii.addr = MAC_MII_ADDR;
1142         mac->mii.data = MAC_MII_DATA;
1143         mac->mii.addr_shift = 11;
1144 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
1145 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
1146 @@ -70,7 +70,7 @@ static void dwmac100_dump_dma_regs(void
1147  {
1148         int i;
1149
1150 -       for (i = 0; i < 9; i++)
1151 +       for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++)
1152                 reg_space[DMA_BUS_MODE / 4 + i] =
1153                         readl(ioaddr + DMA_BUS_MODE + i * 4);
1154
1155 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
1156 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
1157 @@ -35,15 +35,17 @@ static void dwmac4_core_init(struct mac_
1158         if (hw->ps) {
1159                 value |= GMAC_CONFIG_TE;
1160
1161 -               if (hw->ps == SPEED_1000) {
1162 -                       value &= ~GMAC_CONFIG_PS;
1163 -               } else {
1164 -                       value |= GMAC_CONFIG_PS;
1165 -
1166 -                       if (hw->ps == SPEED_10)
1167 -                               value &= ~GMAC_CONFIG_FES;
1168 -                       else
1169 -                               value |= GMAC_CONFIG_FES;
1170 +               value &= hw->link.speed_mask;
1171 +               switch (hw->ps) {
1172 +               case SPEED_1000:
1173 +                       value |= hw->link.speed1000;
1174 +                       break;
1175 +               case SPEED_100:
1176 +                       value |= hw->link.speed100;
1177 +                       break;
1178 +               case SPEED_10:
1179 +                       value |= hw->link.speed10;
1180 +                       break;
1181                 }
1182         }
1183
1184 @@ -115,7 +117,7 @@ static void dwmac4_tx_queue_routing(stru
1185         void __iomem *ioaddr = hw->pcsr;
1186         u32 value;
1187
1188 -       const struct stmmac_rx_routing route_possibilities[] = {
1189 +       static const struct stmmac_rx_routing route_possibilities[] = {
1190                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
1191                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
1192                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
1193 @@ -747,9 +749,11 @@ struct mac_device_info *dwmac4_setup(voi
1194         if (mac->multicast_filter_bins)
1195                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1196
1197 -       mac->link.port = GMAC_CONFIG_PS;
1198         mac->link.duplex = GMAC_CONFIG_DM;
1199 -       mac->link.speed = GMAC_CONFIG_FES;
1200 +       mac->link.speed10 = GMAC_CONFIG_PS;
1201 +       mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1202 +       mac->link.speed1000 = 0;
1203 +       mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1204         mac->mii.addr = GMAC_MDIO_ADDR;
1205         mac->mii.data = GMAC_MDIO_DATA;
1206         mac->mii.addr_shift = 21;
1207 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
1208 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
1209 @@ -71,9 +71,9 @@ static void dwmac4_dma_axi(void __iomem
1210         writel(value, ioaddr + DMA_SYS_BUS_MODE);
1211  }
1212
1213 -void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
1214 -                            struct stmmac_dma_cfg *dma_cfg,
1215 -                            u32 dma_rx_phy, u32 chan)
1216 +static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
1217 +                                   struct stmmac_dma_cfg *dma_cfg,
1218 +                                   u32 dma_rx_phy, u32 chan)
1219  {
1220         u32 value;
1221         u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
1222 @@ -85,9 +85,9 @@ void dwmac4_dma_init_rx_chan(void __iome
1223         writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
1224  }
1225
1226 -void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
1227 -                            struct stmmac_dma_cfg *dma_cfg,
1228 -                            u32 dma_tx_phy, u32 chan)
1229 +static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
1230 +                                   struct stmmac_dma_cfg *dma_cfg,
1231 +                                   u32 dma_tx_phy, u32 chan)
1232  {
1233         u32 value;
1234         u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
1235 @@ -99,8 +99,8 @@ void dwmac4_dma_init_tx_chan(void __iome
1236         writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
1237  }
1238
1239 -void dwmac4_dma_init_channel(void __iomem *ioaddr,
1240 -                            struct stmmac_dma_cfg *dma_cfg, u32 chan)
1241 +static void dwmac4_dma_init_channel(void __iomem *ioaddr,
1242 +                                   struct stmmac_dma_cfg *dma_cfg, u32 chan)
1243  {
1244         u32 value;
1245
1246 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
1247 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
1248 @@ -136,6 +136,9 @@
1249  #define DMA_STATUS_TI  0x00000001      /* Transmit Interrupt */
1250  #define DMA_CONTROL_FTF                0x00100000      /* Flush transmit FIFO */
1251
1252 +#define NUM_DWMAC100_DMA_REGS  9
1253 +#define NUM_DWMAC1000_DMA_REGS 23
1254 +
1255  void dwmac_enable_dma_transmission(void __iomem *ioaddr);
1256  void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan);
1257  void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan);
1258 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
1259 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
1260 @@ -248,6 +248,7 @@ void stmmac_set_mac_addr(void __iomem *i
1261         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1262         writel(data, ioaddr + low);
1263  }
1264 +EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
1265
1266  /* Enable disable MAC RX/TX */
1267  void stmmac_set_mac(void __iomem *ioaddr, bool enable)
1268 @@ -279,4 +280,4 @@ void stmmac_get_mac_addr(void __iomem *i
1269         addr[4] = hi_addr & 0xff;
1270         addr[5] = (hi_addr >> 8) & 0xff;
1271  }
1272 -
1273 +EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);
1274 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
1275 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
1276 @@ -104,7 +104,7 @@ struct stmmac_priv {
1277         /* TX Queue */
1278         struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
1279
1280 -       int oldlink;
1281 +       bool oldlink;
1282         int speed;
1283         int oldduplex;
1284         unsigned int flow_ctrl;
1285 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
1286 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
1287 @@ -29,10 +29,12 @@
1288  #include "stmmac.h"
1289  #include "dwmac_dma.h"
1290
1291 -#define REG_SPACE_SIZE 0x1054
1292 +#define REG_SPACE_SIZE 0x1060
1293  #define MAC100_ETHTOOL_NAME    "st_mac100"
1294  #define GMAC_ETHTOOL_NAME      "st_gmac"
1295
1296 +#define ETHTOOL_DMA_OFFSET     55
1297 +
1298  struct stmmac_stats {
1299         char stat_string[ETH_GSTRING_LEN];
1300         int sizeof_stat;
1301 @@ -273,7 +275,6 @@ static int stmmac_ethtool_get_link_ksett
1302  {
1303         struct stmmac_priv *priv = netdev_priv(dev);
1304         struct phy_device *phy = dev->phydev;
1305 -       int rc;
1306
1307         if (priv->hw->pcs & STMMAC_PCS_RGMII ||
1308             priv->hw->pcs & STMMAC_PCS_SGMII) {
1309 @@ -364,8 +365,8 @@ static int stmmac_ethtool_get_link_ksett
1310                 "link speed / duplex setting\n", dev->name);
1311                 return -EBUSY;
1312         }
1313 -       rc = phy_ethtool_ksettings_get(phy, cmd);
1314 -       return rc;
1315 +       phy_ethtool_ksettings_get(phy, cmd);
1316 +       return 0;
1317  }
1318
1319  static int
1320 @@ -443,6 +444,9 @@ static void stmmac_ethtool_gregs(struct
1321
1322         priv->hw->mac->dump_regs(priv->hw, reg_space);
1323         priv->hw->dma->dump_regs(priv->ioaddr, reg_space);
1324 +       /* Copy DMA registers to where ethtool expects them */
1325 +       memcpy(&reg_space[ETHTOOL_DMA_OFFSET], &reg_space[DMA_BUS_MODE / 4],
1326 +              NUM_DWMAC1000_DMA_REGS * 4);
1327  }
1328
1329  static void
1330 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
1331 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
1332 @@ -235,6 +235,17 @@ static void stmmac_clk_csr_set(struct st
1333                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
1334                         priv->clk_csr = STMMAC_CSR_250_300M;
1335         }
1336 +
1337 +       if (priv->plat->has_sun8i) {
1338 +               if (clk_rate > 160000000)
1339 +                       priv->clk_csr = 0x03;
1340 +               else if (clk_rate > 80000000)
1341 +                       priv->clk_csr = 0x02;
1342 +               else if (clk_rate > 40000000)
1343 +                       priv->clk_csr = 0x01;
1344 +               else
1345 +                       priv->clk_csr = 0;
1346 +       }
1347  }
1348
1349  static void print_pkt(unsigned char *buf, int len)
1350 @@ -789,7 +800,7 @@ static void stmmac_adjust_link(struct ne
1351         struct stmmac_priv *priv = netdev_priv(dev);
1352         struct phy_device *phydev = dev->phydev;
1353         unsigned long flags;
1354 -       int new_state = 0;
1355 +       bool new_state = false;
1356
1357         if (!phydev)
1358                 return;
1359 @@ -802,8 +813,8 @@ static void stmmac_adjust_link(struct ne
1360                 /* Now we make sure that we can be in full duplex mode.
1361                  * If not, we operate in half-duplex mode. */
1362                 if (phydev->duplex != priv->oldduplex) {
1363 -                       new_state = 1;
1364 -                       if (!(phydev->duplex))
1365 +                       new_state = true;
1366 +                       if (!phydev->duplex)
1367                                 ctrl &= ~priv->hw->link.duplex;
1368                         else
1369                                 ctrl |= priv->hw->link.duplex;
1370 @@ -814,30 +825,17 @@ static void stmmac_adjust_link(struct ne
1371                         stmmac_mac_flow_ctrl(priv, phydev->duplex);
1372
1373                 if (phydev->speed != priv->speed) {
1374 -                       new_state = 1;
1375 +                       new_state = true;
1376 +                       ctrl &= ~priv->hw->link.speed_mask;
1377                         switch (phydev->speed) {
1378 -                       case 1000:
1379 -                               if (priv->plat->has_gmac ||
1380 -                                   priv->plat->has_gmac4)
1381 -                                       ctrl &= ~priv->hw->link.port;
1382 +                       case SPEED_1000:
1383 +                               ctrl |= priv->hw->link.speed1000;
1384                                 break;
1385 -                       case 100:
1386 -                               if (priv->plat->has_gmac ||
1387 -                                   priv->plat->has_gmac4) {
1388 -                                       ctrl |= priv->hw->link.port;
1389 -                                       ctrl |= priv->hw->link.speed;
1390 -                               } else {
1391 -                                       ctrl &= ~priv->hw->link.port;
1392 -                               }
1393 +                       case SPEED_100:
1394 +                               ctrl |= priv->hw->link.speed100;
1395                                 break;
1396 -                       case 10:
1397 -                               if (priv->plat->has_gmac ||
1398 -                                   priv->plat->has_gmac4) {
1399 -                                       ctrl |= priv->hw->link.port;
1400 -                                       ctrl &= ~(priv->hw->link.speed);
1401 -                               } else {
1402 -                                       ctrl &= ~priv->hw->link.port;
1403 -                               }
1404 +                       case SPEED_10:
1405 +                               ctrl |= priv->hw->link.speed10;
1406                                 break;
1407                         default:
1408                                 netif_warn(priv, link, priv->dev,
1409 @@ -853,12 +851,12 @@ static void stmmac_adjust_link(struct ne
1410                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1411
1412                 if (!priv->oldlink) {
1413 -                       new_state = 1;
1414 -                       priv->oldlink = 1;
1415 +                       new_state = true;
1416 +                       priv->oldlink = true;
1417                 }
1418         } else if (priv->oldlink) {
1419 -               new_state = 1;
1420 -               priv->oldlink = 0;
1421 +               new_state = true;
1422 +               priv->oldlink = false;
1423                 priv->speed = SPEED_UNKNOWN;
1424                 priv->oldduplex = DUPLEX_UNKNOWN;
1425         }
1426 @@ -921,7 +919,7 @@ static int stmmac_init_phy(struct net_de
1427         char bus_id[MII_BUS_ID_SIZE];
1428         int interface = priv->plat->interface;
1429         int max_speed = priv->plat->max_speed;
1430 -       priv->oldlink = 0;
1431 +       priv->oldlink = false;
1432         priv->speed = SPEED_UNKNOWN;
1433         priv->oldduplex = DUPLEX_UNKNOWN;
1434
1435 @@ -1456,7 +1454,7 @@ static void free_dma_rx_desc_resources(s
1436  static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1437  {
1438         u32 tx_count = priv->plat->tx_queues_to_use;
1439 -       u32 queue = 0;
1440 +       u32 queue;
1441
1442         /* Free TX queue resources */
1443         for (queue = 0; queue < tx_count; queue++) {
1444 @@ -1505,7 +1503,7 @@ static int alloc_dma_rx_desc_resources(s
1445                                                     sizeof(dma_addr_t),
1446                                                     GFP_KERNEL);
1447                 if (!rx_q->rx_skbuff_dma)
1448 -                       return -ENOMEM;
1449 +                       goto err_dma;
1450
1451                 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1452                                                 sizeof(struct sk_buff *),
1453 @@ -1568,13 +1566,13 @@ static int alloc_dma_tx_desc_resources(s
1454                                                     sizeof(*tx_q->tx_skbuff_dma),
1455                                                     GFP_KERNEL);
1456                 if (!tx_q->tx_skbuff_dma)
1457 -                       return -ENOMEM;
1458 +                       goto err_dma;
1459
1460                 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1461                                                 sizeof(struct sk_buff *),
1462                                                 GFP_KERNEL);
1463                 if (!tx_q->tx_skbuff)
1464 -                       goto err_dma_buffers;
1465 +                       goto err_dma;
1466
1467                 if (priv->extend_desc) {
1468                         tx_q->dma_etx = dma_zalloc_coherent(priv->device,
1469 @@ -1584,7 +1582,7 @@ static int alloc_dma_tx_desc_resources(s
1470                                                             &tx_q->dma_tx_phy,
1471                                                             GFP_KERNEL);
1472                         if (!tx_q->dma_etx)
1473 -                               goto err_dma_buffers;
1474 +                               goto err_dma;
1475                 } else {
1476                         tx_q->dma_tx = dma_zalloc_coherent(priv->device,
1477                                                            DMA_TX_SIZE *
1478 @@ -1593,13 +1591,13 @@ static int alloc_dma_tx_desc_resources(s
1479                                                            &tx_q->dma_tx_phy,
1480                                                            GFP_KERNEL);
1481                         if (!tx_q->dma_tx)
1482 -                               goto err_dma_buffers;
1483 +                               goto err_dma;
1484                 }
1485         }
1486
1487         return 0;
1488
1489 -err_dma_buffers:
1490 +err_dma:
1491         free_dma_tx_desc_resources(priv);
1492
1493         return ret;
1494 @@ -2907,8 +2905,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
1495                 priv->xstats.tx_set_ic_bit++;
1496         }
1497
1498 -       if (!priv->hwts_tx_en)
1499 -               skb_tx_timestamp(skb);
1500 +       skb_tx_timestamp(skb);
1501
1502         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1503                      priv->hwts_tx_en)) {
1504 @@ -2993,7 +2990,7 @@ static netdev_tx_t stmmac_xmit(struct sk
1505
1506         /* Manage oversized TCP frames for GMAC4 device */
1507         if (skb_is_gso(skb) && priv->tso) {
1508 -               if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1509 +               if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
1510                         return stmmac_tso_xmit(skb, dev);
1511         }
1512
1513 @@ -3124,8 +3121,7 @@ static netdev_tx_t stmmac_xmit(struct sk
1514                 priv->xstats.tx_set_ic_bit++;
1515         }
1516
1517 -       if (!priv->hwts_tx_en)
1518 -               skb_tx_timestamp(skb);
1519 +       skb_tx_timestamp(skb);
1520
1521         /* Ready to fill the first descriptor and set the OWN bit w/o any
1522          * problems because all the descriptors are actually ready to be
1523 @@ -4002,7 +3998,9 @@ static int stmmac_hw_init(struct stmmac_
1524         struct mac_device_info *mac;
1525
1526         /* Identify the MAC HW device */
1527 -       if (priv->plat->has_gmac) {
1528 +       if (priv->plat->setup) {
1529 +               mac = priv->plat->setup(priv);
1530 +       } else if (priv->plat->has_gmac) {
1531                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1532                 mac = dwmac1000_setup(priv->ioaddr,
1533                                       priv->plat->multicast_filter_bins,
1534 @@ -4022,6 +4020,10 @@ static int stmmac_hw_init(struct stmmac_
1535
1536         priv->hw = mac;
1537
1538 +       /* dwmac-sun8i only work in chain mode */
1539 +       if (priv->plat->has_sun8i)
1540 +               chain_mode = 1;
1541 +
1542         /* To use the chained or ring mode */
1543         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1544                 priv->hw->mode = &dwmac4_ring_mode_ops;
1545 @@ -4150,8 +4152,15 @@ int stmmac_dvr_probe(struct device *devi
1546         if ((phyaddr >= 0) && (phyaddr <= 31))
1547                 priv->plat->phy_addr = phyaddr;
1548
1549 -       if (priv->plat->stmmac_rst)
1550 +       if (priv->plat->stmmac_rst) {
1551 +               ret = reset_control_assert(priv->plat->stmmac_rst);
1552                 reset_control_deassert(priv->plat->stmmac_rst);
1553 +               /* Some reset controllers have only reset callback instead of
1554 +                * assert + deassert callbacks pair.
1555 +                */
1556 +               if (ret == -ENOTSUPP)
1557 +                       reset_control_reset(priv->plat->stmmac_rst);
1558 +       }
1559
1560         /* Init MAC and get the capabilities */
1561         ret = stmmac_hw_init(priv);
1562 @@ -4168,7 +4177,7 @@ int stmmac_dvr_probe(struct device *devi
1563                             NETIF_F_RXCSUM;
1564
1565         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
1566 -               ndev->hw_features |= NETIF_F_TSO;
1567 +               ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
1568                 priv->tso = true;
1569                 dev_info(priv->device, "TSO feature enabled\n");
1570         }
1571 @@ -4330,7 +4339,7 @@ int stmmac_suspend(struct device *dev)
1572         }
1573         spin_unlock_irqrestore(&priv->lock, flags);
1574
1575 -       priv->oldlink = 0;
1576 +       priv->oldlink = false;
1577         priv->speed = SPEED_UNKNOWN;
1578         priv->oldduplex = DUPLEX_UNKNOWN;
1579         return 0;
1580 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
1581 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
1582 @@ -204,6 +204,7 @@ int stmmac_mdio_register(struct net_devi
1583         struct stmmac_priv *priv = netdev_priv(ndev);
1584         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1585         struct device_node *mdio_node = priv->plat->mdio_node;
1586 +       struct device *dev = ndev->dev.parent;
1587         int addr, found;
1588
1589         if (!mdio_bus_data)
1590 @@ -237,7 +238,7 @@ int stmmac_mdio_register(struct net_devi
1591         else
1592                 err = mdiobus_register(new_bus);
1593         if (err != 0) {
1594 -               netdev_err(ndev, "Cannot register the MDIO bus\n");
1595 +               dev_err(dev, "Cannot register the MDIO bus\n");
1596                 goto bus_register_fail;
1597         }
1598
1599 @@ -292,7 +293,7 @@ int stmmac_mdio_register(struct net_devi
1600         }
1601
1602         if (!found && !mdio_node) {
1603 -               netdev_warn(ndev, "No PHY found\n");
1604 +               dev_warn(dev, "No PHY found\n");
1605                 mdiobus_unregister(new_bus);
1606                 mdiobus_free(new_bus);
1607                 return -ENODEV;
1608 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
1609 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
1610 @@ -30,42 +30,39 @@
1611   * negative value of the address means that MAC controller is not connected
1612   * with PHY.
1613   */
1614 -struct stmmac_pci_dmi_data {
1615 -       const char *name;
1616 -       const char *asset_tag;
1617 +struct stmmac_pci_func_data {
1618         unsigned int func;
1619         int phy_addr;
1620  };
1621
1622 -struct stmmac_pci_info {
1623 -       struct pci_dev *pdev;
1624 -       int (*setup)(struct plat_stmmacenet_data *plat,
1625 -                    struct stmmac_pci_info *info);
1626 -       struct stmmac_pci_dmi_data *dmi;
1627 +struct stmmac_pci_dmi_data {
1628 +       const struct stmmac_pci_func_data *func;
1629 +       size_t nfuncs;
1630  };
1631
1632 -static int stmmac_pci_find_phy_addr(struct stmmac_pci_info *info)
1633 -{
1634 -       const char *name = dmi_get_system_info(DMI_BOARD_NAME);
1635 -       const char *asset_tag = dmi_get_system_info(DMI_BOARD_ASSET_TAG);
1636 -       unsigned int func = PCI_FUNC(info->pdev->devfn);
1637 -       struct stmmac_pci_dmi_data *dmi;
1638 -
1639 -       /*
1640 -        * Galileo boards with old firmware don't support DMI. We always return
1641 -        * 1 here, so at least first found MAC controller would be probed.
1642 -        */
1643 -       if (!name)
1644 -               return 1;
1645 +struct stmmac_pci_info {
1646 +       int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
1647 +};
1648
1649 -       for (dmi = info->dmi; dmi->name && *dmi->name; dmi++) {
1650 -               if (!strcmp(dmi->name, name) && dmi->func == func) {
1651 -                       /* If asset tag is provided, match on it as well. */
1652 -                       if (dmi->asset_tag && strcmp(dmi->asset_tag, asset_tag))
1653 -                               continue;
1654 -                       return dmi->phy_addr;
1655 -               }
1656 -       }
1657 +static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
1658 +                                   const struct dmi_system_id *dmi_list)
1659 +{
1660 +       const struct stmmac_pci_func_data *func_data;
1661 +       const struct stmmac_pci_dmi_data *dmi_data;
1662 +       const struct dmi_system_id *dmi_id;
1663 +       int func = PCI_FUNC(pdev->devfn);
1664 +       size_t n;
1665 +
1666 +       dmi_id = dmi_first_match(dmi_list);
1667 +       if (!dmi_id)
1668 +               return -ENODEV;
1669 +
1670 +       dmi_data = dmi_id->driver_data;
1671 +       func_data = dmi_data->func;
1672 +
1673 +       for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
1674 +               if (func_data->func == func)
1675 +                       return func_data->phy_addr;
1676
1677         return -ENODEV;
1678  }
1679 @@ -100,7 +97,8 @@ static void common_default_data(struct p
1680         plat->rx_queues_cfg[0].pkt_route = 0x0;
1681  }
1682
1683 -static void stmmac_default_data(struct plat_stmmacenet_data *plat)
1684 +static int stmmac_default_data(struct pci_dev *pdev,
1685 +                              struct plat_stmmacenet_data *plat)
1686  {
1687         /* Set common default data first */
1688         common_default_data(plat);
1689 @@ -112,12 +110,77 @@ static void stmmac_default_data(struct p
1690         plat->dma_cfg->pbl = 32;
1691         plat->dma_cfg->pblx8 = true;
1692         /* TODO: AXI */
1693 +
1694 +       return 0;
1695  }
1696
1697 -static int quark_default_data(struct plat_stmmacenet_data *plat,
1698 -                             struct stmmac_pci_info *info)
1699 +static const struct stmmac_pci_info stmmac_pci_info = {
1700 +       .setup = stmmac_default_data,
1701 +};
1702 +
1703 +static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
1704 +       {
1705 +               .func = 6,
1706 +               .phy_addr = 1,
1707 +       },
1708 +};
1709 +
1710 +static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
1711 +       .func = galileo_stmmac_func_data,
1712 +       .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
1713 +};
1714 +
1715 +static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
1716 +       {
1717 +               .func = 6,
1718 +               .phy_addr = 1,
1719 +       },
1720 +       {
1721 +               .func = 7,
1722 +               .phy_addr = 1,
1723 +       },
1724 +};
1725 +
1726 +static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
1727 +       .func = iot2040_stmmac_func_data,
1728 +       .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
1729 +};
1730 +
1731 +static const struct dmi_system_id quark_pci_dmi[] = {
1732 +       {
1733 +               .matches = {
1734 +                       DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
1735 +               },
1736 +               .driver_data = (void *)&galileo_stmmac_dmi_data,
1737 +       },
1738 +       {
1739 +               .matches = {
1740 +                       DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
1741 +               },
1742 +               .driver_data = (void *)&galileo_stmmac_dmi_data,
1743 +       },
1744 +       {
1745 +               .matches = {
1746 +                       DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1747 +                       DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
1748 +                                       "6ES7647-0AA00-0YA2"),
1749 +               },
1750 +               .driver_data = (void *)&galileo_stmmac_dmi_data,
1751 +       },
1752 +       {
1753 +               .matches = {
1754 +                       DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1755 +                       DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
1756 +                                       "6ES7647-0AA00-1YA2"),
1757 +               },
1758 +               .driver_data = (void *)&iot2040_stmmac_dmi_data,
1759 +       },
1760 +       {}
1761 +};
1762 +
1763 +static int quark_default_data(struct pci_dev *pdev,
1764 +                             struct plat_stmmacenet_data *plat)
1765  {
1766 -       struct pci_dev *pdev = info->pdev;
1767         int ret;
1768
1769         /* Set common default data first */
1770 @@ -127,9 +190,19 @@ static int quark_default_data(struct pla
1771          * Refuse to load the driver and register net device if MAC controller
1772          * does not connect to any PHY interface.
1773          */
1774 -       ret = stmmac_pci_find_phy_addr(info);
1775 -       if (ret < 0)
1776 -               return ret;
1777 +       ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
1778 +       if (ret < 0) {
1779 +               /* Return error to the caller on DMI enabled boards. */
1780 +               if (dmi_get_system_info(DMI_BOARD_NAME))
1781 +                       return ret;
1782 +
1783 +               /*
1784 +                * Galileo boards with old firmware don't support DMI. We always
1785 +                * use 1 here as PHY address, so at least the first found MAC
1786 +                * controller would be probed.
1787 +                */
1788 +               ret = 1;
1789 +       }
1790
1791         plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn);
1792         plat->phy_addr = ret;
1793 @@ -143,41 +216,8 @@ static int quark_default_data(struct pla
1794         return 0;
1795  }
1796
1797 -static struct stmmac_pci_dmi_data quark_pci_dmi_data[] = {
1798 -       {
1799 -               .name = "Galileo",
1800 -               .func = 6,
1801 -               .phy_addr = 1,
1802 -       },
1803 -       {
1804 -               .name = "GalileoGen2",
1805 -               .func = 6,
1806 -               .phy_addr = 1,
1807 -       },
1808 -       {
1809 -               .name = "SIMATIC IOT2000",
1810 -               .asset_tag = "6ES7647-0AA00-0YA2",
1811 -               .func = 6,
1812 -               .phy_addr = 1,
1813 -       },
1814 -       {
1815 -               .name = "SIMATIC IOT2000",
1816 -               .asset_tag = "6ES7647-0AA00-1YA2",
1817 -               .func = 6,
1818 -               .phy_addr = 1,
1819 -       },
1820 -       {
1821 -               .name = "SIMATIC IOT2000",
1822 -               .asset_tag = "6ES7647-0AA00-1YA2",
1823 -               .func = 7,
1824 -               .phy_addr = 1,
1825 -       },
1826 -       {}
1827 -};
1828 -
1829 -static struct stmmac_pci_info quark_pci_info = {
1830 +static const struct stmmac_pci_info quark_pci_info = {
1831         .setup = quark_default_data,
1832 -       .dmi = quark_pci_dmi_data,
1833  };
1834
1835  /**
1836 @@ -236,15 +276,9 @@ static int stmmac_pci_probe(struct pci_d
1837
1838         pci_set_master(pdev);
1839
1840 -       if (info) {
1841 -               info->pdev = pdev;
1842 -               if (info->setup) {
1843 -                       ret = info->setup(plat, info);
1844 -                       if (ret)
1845 -                               return ret;
1846 -               }
1847 -       } else
1848 -               stmmac_default_data(plat);
1849 +       ret = info->setup(pdev, plat);
1850 +       if (ret)
1851 +               return ret;
1852
1853         pci_enable_msi(pdev);
1854
1855 @@ -270,14 +304,21 @@ static void stmmac_pci_remove(struct pci
1856
1857  static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_suspend, stmmac_resume);
1858
1859 -#define STMMAC_VENDOR_ID 0x700
1860 +/* synthetic ID, no official vendor */
1861 +#define PCI_VENDOR_ID_STMMAC 0x700
1862 +
1863  #define STMMAC_QUARK_ID  0x0937
1864  #define STMMAC_DEVICE_ID 0x1108
1865
1866 +#define STMMAC_DEVICE(vendor_id, dev_id, info) {       \
1867 +       PCI_VDEVICE(vendor_id, dev_id),                 \
1868 +       .driver_data = (kernel_ulong_t)&info            \
1869 +       }
1870 +
1871  static const struct pci_device_id stmmac_id_table[] = {
1872 -       {PCI_DEVICE(STMMAC_VENDOR_ID, STMMAC_DEVICE_ID)},
1873 -       {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_MAC)},
1874 -       {PCI_VDEVICE(INTEL, STMMAC_QUARK_ID), (kernel_ulong_t)&quark_pci_info},
1875 +       STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info),
1876 +       STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info),
1877 +       STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info),
1878         {}
1879  };
1880
1881 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
1882 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
1883 @@ -309,6 +309,13 @@ static int stmmac_dt_phy(struct plat_stm
1884                          struct device_node *np, struct device *dev)
1885  {
1886         bool mdio = true;
1887 +       static const struct of_device_id need_mdio_ids[] = {
1888 +               { .compatible = "snps,dwc-qos-ethernet-4.10" },
1889 +               { .compatible = "allwinner,sun8i-a83t-emac" },
1890 +               { .compatible = "allwinner,sun8i-h3-emac" },
1891 +               { .compatible = "allwinner,sun8i-v3s-emac" },
1892 +               { .compatible = "allwinner,sun50i-a64-emac" },
1893 +       };
1894
1895         /* If phy-handle property is passed from DT, use it as the PHY */
1896         plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
1897 @@ -325,8 +332,7 @@ static int stmmac_dt_phy(struct plat_stm
1898                 mdio = false;
1899         }
1900
1901 -       /* exception for dwmac-dwc-qos-eth glue logic */
1902 -       if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) {
1903 +       if (of_match_node(need_mdio_ids, np)) {
1904                 plat->mdio_node = of_get_child_by_name(np, "mdio");
1905         } else {
1906                 /**
1907 --- a/include/linux/stmmac.h
1908 +++ b/include/linux/stmmac.h
1909 @@ -177,6 +177,7 @@ struct plat_stmmacenet_data {
1910         void (*fix_mac_speed)(void *priv, unsigned int speed);
1911         int (*init)(struct platform_device *pdev, void *priv);
1912         void (*exit)(struct platform_device *pdev, void *priv);
1913 +       struct mac_device_info *(*setup)(void *priv);
1914         void *bsp_priv;
1915         struct clk *stmmac_clk;
1916         struct clk *pclk;
1917 @@ -185,6 +186,7 @@ struct plat_stmmacenet_data {
1918         struct reset_control *stmmac_rst;
1919         struct stmmac_axi *axi;
1920         int has_gmac4;
1921 +       bool has_sun8i;
1922         bool tso_en;
1923         int mac_port_sel_speed;
1924         bool en_tx_lpi_clockgating;