target/linux/sunxi/patches-4.9/0051-stmmac-form-4-11.patch

   1 --- a/Documentation/devicetree/bindings/net/stmmac.txt
   2 +++ b/Documentation/devicetree/bindings/net/stmmac.txt
   3 @@ -49,6 +49,8 @@ Optional properties:
   4  - snps,force_sf_dma_mode       Force DMA to use the Store and Forward
   5                                 mode for both tx and rx. This flag is
   6                                 ignored if force_thresh_dma_mode is set.
   7 +- snps,en-tx-lpi-clockgating   Enable gating of the MAC TX clock during
   8 +                               TX low-power mode
   9  - snps,multicast-filter-bins:  Number of multicast filter hash bins
  10                                 supported by this device instance
  11  - snps,perfect-filter-entries: Number of perfect filter entries supported
  12 @@ -65,7 +67,6 @@ Optional properties:
  13         - snps,wr_osr_lmt: max write outstanding req. limit
  14         - snps,rd_osr_lmt: max read outstanding req. limit
  15         - snps,kbbe: do not cross 1KiB boundary.
  16 -       - snps,axi_all: align address
  17         - snps,blen: this is a vector of supported burst length.
  18         - snps,fb: fixed-burst
  19         - snps,mb: mixed-burst
  20 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
  21 +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
  22 @@ -1,5 +1,5 @@
  23  config STMMAC_ETH
  24 -       tristate "STMicroelectronics 10/100/1000 Ethernet driver"
  25 +       tristate "STMicroelectronics 10/100/1000/EQOS Ethernet driver"
  26         depends on HAS_IOMEM && HAS_DMA
  27         select MII
  28         select PHYLIB
  29 @@ -7,9 +7,8 @@ config STMMAC_ETH
  30         select PTP_1588_CLOCK
  31         select RESET_CONTROLLER
  32         ---help---
  33 -         This is the driver for the Ethernet IPs are built around a
  34 -         Synopsys IP Core and only tested on the STMicroelectronics
  35 -         platforms.
  36 +         This is the driver for the Ethernet IPs built around a
  37 +         Synopsys IP Core.
  38
  39  if STMMAC_ETH
  40
  41 @@ -29,6 +28,15 @@ config STMMAC_PLATFORM
  42
  43  if STMMAC_PLATFORM
  44
  45 +config DWMAC_DWC_QOS_ETH
  46 +       tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
  47 +       select PHYLIB
  48 +       select CRC32
  49 +       select MII
  50 +       depends on OF && HAS_DMA
  51 +       help
  52 +         Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
  53 +
  54  config DWMAC_GENERIC
  55         tristate "Generic driver for DWMAC"
  56         default STMMAC_PLATFORM
  57 @@ -143,11 +151,11 @@ config STMMAC_PCI
  58         tristate "STMMAC PCI bus support"
  59         depends on STMMAC_ETH && PCI
  60         ---help---
  61 -         This is to select the Synopsys DWMAC available on PCI devices,
  62 -         if you have a controller with this interface, say Y or M here.
  63 +         This selects the platform specific bus support for the stmmac driver.
  64 +         This driver was tested on XLINX XC2V3000 FF1152AMT0221
  65 +         D1215994A VIRTEX FPGA board and SNPS QoS IPK Prototyping Kit.
  66
  67 -         This PCI support is tested on XLINX XC2V3000 FF1152AMT0221
  68 -         D1215994A VIRTEX FPGA board.
  69 +         If you have a controller with this interface, say Y or M here.
  70
  71           If unsure, say N.
  72  endif
  73 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
  74 +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
  75 @@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA)   += dwmac-alt
  76  obj-$(CONFIG_DWMAC_STI)                += dwmac-sti.o
  77  obj-$(CONFIG_DWMAC_STM32)      += dwmac-stm32.o
  78  obj-$(CONFIG_DWMAC_SUNXI)      += dwmac-sunxi.o
  79 +obj-$(CONFIG_DWMAC_DWC_QOS_ETH)        += dwmac-dwc-qos-eth.o
  80  obj-$(CONFIG_DWMAC_GENERIC)    += dwmac-generic.o
  81  stmmac-platform-objs:= stmmac_platform.o
  82  dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o
  83 --- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
  84 +++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
  85 @@ -16,10 +16,6 @@
  86    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  87    more details.
  88
  89 -  You should have received a copy of the GNU General Public License along with
  90 -  this program; if not, write to the Free Software Foundation, Inc.,
  91 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  92 -
  93    The full GNU General Public License is included in this distribution in
  94    the file called "COPYING".
  95
  96 --- a/drivers/net/ethernet/stmicro/stmmac/common.h
  97 +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
  98 @@ -12,10 +12,6 @@
  99    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 100    more details.
 101
 102 -  You should have received a copy of the GNU General Public License along with
 103 -  this program; if not, write to the Free Software Foundation, Inc.,
 104 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 105 -
 106    The full GNU General Public License is included in this distribution in
 107    the file called "COPYING".
 108
 109 @@ -71,7 +67,7 @@ struct stmmac_extra_stats {
 110         unsigned long overflow_error;
 111         unsigned long ipc_csum_error;
 112         unsigned long rx_collision;
 113 -       unsigned long rx_crc;
 114 +       unsigned long rx_crc_errors;
 115         unsigned long dribbling_bit;
 116         unsigned long rx_length;
 117         unsigned long rx_mii;
 118 @@ -323,6 +319,9 @@ struct dma_features {
 119         /* TX and RX number of channels */
 120         unsigned int number_rx_channel;
 121         unsigned int number_tx_channel;
 122 +       /* TX and RX number of queues */
 123 +       unsigned int number_rx_queues;
 124 +       unsigned int number_tx_queues;
 125         /* Alternate (enhanced) DESC mode */
 126         unsigned int enh_desc;
 127  };
 128 @@ -340,7 +339,7 @@ struct dma_features {
 129  /* Common MAC defines */
 130  #define MAC_CTRL_REG           0x00000000      /* MAC Control */
 131  #define MAC_ENABLE_TX          0x00000008      /* Transmitter Enable */
 132 -#define MAC_RNABLE_RX          0x00000004      /* Receiver Enable */
 133 +#define MAC_ENABLE_RX          0x00000004      /* Receiver Enable */
 134
 135  /* Default LPI timers */
 136  #define STMMAC_DEFAULT_LIT_LS  0x3E8
 137 @@ -417,7 +416,7 @@ struct stmmac_dma_ops {
 138         /* Configure the AXI Bus Mode Register */
 139         void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
 140         /* Dump DMA registers */
 141 -       void (*dump_regs) (void __iomem *ioaddr);
 142 +       void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
 143         /* Set tx/rx threshold in the csr6 register
 144          * An invalid value enables the store-and-forward mode */
 145         void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
 146 @@ -454,8 +453,10 @@ struct stmmac_ops {
 147         void (*core_init)(struct mac_device_info *hw, int mtu);
 148         /* Enable and verify that the IPC module is supported */
 149         int (*rx_ipc)(struct mac_device_info *hw);
 150 +       /* Enable RX Queues */
 151 +       void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
 152         /* Dump MAC registers */
 153 -       void (*dump_regs)(struct mac_device_info *hw);
 154 +       void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
 155         /* Handle extra events on specific interrupts hw dependent */
 156         int (*host_irq_status)(struct mac_device_info *hw,
 157                                struct stmmac_extra_stats *x);
 158 @@ -471,7 +472,8 @@ struct stmmac_ops {
 159                               unsigned int reg_n);
 160         void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
 161                               unsigned int reg_n);
 162 -       void (*set_eee_mode)(struct mac_device_info *hw);
 163 +       void (*set_eee_mode)(struct mac_device_info *hw,
 164 +                            bool en_tx_lpi_clockgating);
 165         void (*reset_eee_mode)(struct mac_device_info *hw);
 166         void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
 167         void (*set_eee_pls)(struct mac_device_info *hw, int link);
 168 --- a/drivers/net/ethernet/stmicro/stmmac/descs.h
 169 +++ b/drivers/net/ethernet/stmicro/stmmac/descs.h
 170 @@ -11,10 +11,6 @@
 171    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 172    more details.
 173
 174 -  You should have received a copy of the GNU General Public License along with
 175 -  this program; if not, write to the Free Software Foundation, Inc.,
 176 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 177 -
 178    The full GNU General Public License is included in this distribution in
 179    the file called "COPYING".
 180
 181 --- a/drivers/net/ethernet/stmicro/stmmac/descs_com.h
 182 +++ b/drivers/net/ethernet/stmicro/stmmac/descs_com.h
 183 @@ -17,10 +17,6 @@
 184    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 185    more details.
 186
 187 -  You should have received a copy of the GNU General Public License along with
 188 -  this program; if not, write to the Free Software Foundation, Inc.,
 189 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 190 -
 191    The full GNU General Public License is included in this distribution in
 192    the file called "COPYING".
 193
 194 --- /dev/null
 195 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
 196 @@ -0,0 +1,202 @@
 197 +/*
 198 + * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
 199 + *
 200 + * Copyright (C) 2016 Joao Pinto <jpinto@synopsys.com>
 201 + *
 202 + * This program is free software; you can redistribute it and/or modify
 203 + * it under the terms of the GNU General Public License version 2 as
 204 + * published by the Free Software Foundation.
 205 + *
 206 + * You should have received a copy of the GNU General Public License
 207 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
 208 + */
 209 +
 210 +#include <linux/clk.h>
 211 +#include <linux/clk-provider.h>
 212 +#include <linux/device.h>
 213 +#include <linux/ethtool.h>
 214 +#include <linux/io.h>
 215 +#include <linux/ioport.h>
 216 +#include <linux/module.h>
 217 +#include <linux/of_net.h>
 218 +#include <linux/mfd/syscon.h>
 219 +#include <linux/platform_device.h>
 220 +#include <linux/stmmac.h>
 221 +
 222 +#include "stmmac_platform.h"
 223 +
 224 +static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
 225 +                                  struct plat_stmmacenet_data *plat_dat)
 226 +{
 227 +       struct device_node *np = pdev->dev.of_node;
 228 +       u32 burst_map = 0;
 229 +       u32 bit_index = 0;
 230 +       u32 a_index = 0;
 231 +
 232 +       if (!plat_dat->axi) {
 233 +               plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL);
 234 +
 235 +               if (!plat_dat->axi)
 236 +                       return -ENOMEM;
 237 +       }
 238 +
 239 +       plat_dat->axi->axi_lpi_en = of_property_read_bool(np, "snps,en-lpi");
 240 +       if (of_property_read_u32(np, "snps,write-requests",
 241 +                                &plat_dat->axi->axi_wr_osr_lmt)) {
 242 +               /**
 243 +                * Since the register has a reset value of 1, if property
 244 +                * is missing, default to 1.
 245 +                */
 246 +               plat_dat->axi->axi_wr_osr_lmt = 1;
 247 +       } else {
 248 +               /**
 249 +                * If property exists, to keep the behavior from dwc_eth_qos,
 250 +                * subtract one after parsing.
 251 +                */
 252 +               plat_dat->axi->axi_wr_osr_lmt--;
 253 +       }
 254 +
 255 +       if (of_property_read_u32(np, "read,read-requests",
 256 +                                &plat_dat->axi->axi_rd_osr_lmt)) {
 257 +               /**
 258 +                * Since the register has a reset value of 1, if property
 259 +                * is missing, default to 1.
 260 +                */
 261 +               plat_dat->axi->axi_rd_osr_lmt = 1;
 262 +       } else {
 263 +               /**
 264 +                * If property exists, to keep the behavior from dwc_eth_qos,
 265 +                * subtract one after parsing.
 266 +                */
 267 +               plat_dat->axi->axi_rd_osr_lmt--;
 268 +       }
 269 +       of_property_read_u32(np, "snps,burst-map", &burst_map);
 270 +
 271 +       /* converts burst-map bitmask to burst array */
 272 +       for (bit_index = 0; bit_index < 7; bit_index++) {
 273 +               if (burst_map & (1 << bit_index)) {
 274 +                       switch (bit_index) {
 275 +                       case 0:
 276 +                       plat_dat->axi->axi_blen[a_index] = 4; break;
 277 +                       case 1:
 278 +                       plat_dat->axi->axi_blen[a_index] = 8; break;
 279 +                       case 2:
 280 +                       plat_dat->axi->axi_blen[a_index] = 16; break;
 281 +                       case 3:
 282 +                       plat_dat->axi->axi_blen[a_index] = 32; break;
 283 +                       case 4:
 284 +                       plat_dat->axi->axi_blen[a_index] = 64; break;
 285 +                       case 5:
 286 +                       plat_dat->axi->axi_blen[a_index] = 128; break;
 287 +                       case 6:
 288 +                       plat_dat->axi->axi_blen[a_index] = 256; break;
 289 +                       default:
 290 +                       break;
 291 +                       }
 292 +                       a_index++;
 293 +               }
 294 +       }
 295 +
 296 +       /* dwc-qos needs GMAC4, AAL, TSO and PMT */
 297 +       plat_dat->has_gmac4 = 1;
 298 +       plat_dat->dma_cfg->aal = 1;
 299 +       plat_dat->tso_en = 1;
 300 +       plat_dat->pmt = 1;
 301 +
 302 +       return 0;
 303 +}
 304 +
 305 +static int dwc_eth_dwmac_probe(struct platform_device *pdev)
 306 +{
 307 +       struct plat_stmmacenet_data *plat_dat;
 308 +       struct stmmac_resources stmmac_res;
 309 +       struct resource *res;
 310 +       int ret;
 311 +
 312 +       memset(&stmmac_res, 0, sizeof(struct stmmac_resources));
 313 +
 314 +       /**
 315 +        * Since stmmac_platform supports name IRQ only, basic platform
 316 +        * resource initialization is done in the glue logic.
 317 +        */
 318 +       stmmac_res.irq = platform_get_irq(pdev, 0);
 319 +       if (stmmac_res.irq < 0) {
 320 +               if (stmmac_res.irq != -EPROBE_DEFER)
 321 +                       dev_err(&pdev->dev,
 322 +                               "IRQ configuration information not found\n");
 323 +
 324 +               return stmmac_res.irq;
 325 +       }
 326 +       stmmac_res.wol_irq = stmmac_res.irq;
 327 +
 328 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 329 +       stmmac_res.addr = devm_ioremap_resource(&pdev->dev, res);
 330 +       if (IS_ERR(stmmac_res.addr))
 331 +               return PTR_ERR(stmmac_res.addr);
 332 +
 333 +       plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 334 +       if (IS_ERR(plat_dat))
 335 +               return PTR_ERR(plat_dat);
 336 +
 337 +       plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk");
 338 +       if (IS_ERR(plat_dat->stmmac_clk)) {
 339 +               dev_err(&pdev->dev, "apb_pclk clock not found.\n");
 340 +               ret = PTR_ERR(plat_dat->stmmac_clk);
 341 +               plat_dat->stmmac_clk = NULL;
 342 +               goto err_remove_config_dt;
 343 +       }
 344 +       clk_prepare_enable(plat_dat->stmmac_clk);
 345 +
 346 +       plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk");
 347 +       if (IS_ERR(plat_dat->pclk)) {
 348 +               dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
 349 +               ret = PTR_ERR(plat_dat->pclk);
 350 +               plat_dat->pclk = NULL;
 351 +               goto err_out_clk_dis_phy;
 352 +       }
 353 +       clk_prepare_enable(plat_dat->pclk);
 354 +
 355 +       ret = dwc_eth_dwmac_config_dt(pdev, plat_dat);
 356 +       if (ret)
 357 +               goto err_out_clk_dis_aper;
 358 +
 359 +       ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 360 +       if (ret)
 361 +               goto err_out_clk_dis_aper;
 362 +
 363 +       return 0;
 364 +
 365 +err_out_clk_dis_aper:
 366 +       clk_disable_unprepare(plat_dat->pclk);
 367 +err_out_clk_dis_phy:
 368 +       clk_disable_unprepare(plat_dat->stmmac_clk);
 369 +err_remove_config_dt:
 370 +       stmmac_remove_config_dt(pdev, plat_dat);
 371 +
 372 +       return ret;
 373 +}
 374 +
 375 +static int dwc_eth_dwmac_remove(struct platform_device *pdev)
 376 +{
 377 +       return stmmac_pltfr_remove(pdev);
 378 +}
 379 +
 380 +static const struct of_device_id dwc_eth_dwmac_match[] = {
 381 +       { .compatible = "snps,dwc-qos-ethernet-4.10", },
 382 +       { }
 383 +};
 384 +MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
 385 +
 386 +static struct platform_driver dwc_eth_dwmac_driver = {
 387 +       .probe  = dwc_eth_dwmac_probe,
 388 +       .remove = dwc_eth_dwmac_remove,
 389 +       .driver = {
 390 +               .name           = "dwc-eth-dwmac",
 391 +               .of_match_table = dwc_eth_dwmac_match,
 392 +       },
 393 +};
 394 +module_platform_driver(dwc_eth_dwmac_driver);
 395 +
 396 +MODULE_AUTHOR("Joao Pinto <jpinto@synopsys.com>");
 397 +MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver");
 398 +MODULE_LICENSE("GPL v2");
 399 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
 400 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
 401 @@ -35,10 +35,6 @@
 402
 403  #define PRG_ETH0_TXDLY_SHIFT           5
 404  #define PRG_ETH0_TXDLY_MASK            GENMASK(6, 5)
 405 -#define PRG_ETH0_TXDLY_OFF             (0x0 << PRG_ETH0_TXDLY_SHIFT)
 406 -#define PRG_ETH0_TXDLY_QUARTER         (0x1 << PRG_ETH0_TXDLY_SHIFT)
 407 -#define PRG_ETH0_TXDLY_HALF            (0x2 << PRG_ETH0_TXDLY_SHIFT)
 408 -#define PRG_ETH0_TXDLY_THREE_QUARTERS  (0x3 << PRG_ETH0_TXDLY_SHIFT)
 409
 410  /* divider for the result of m250_sel */
 411  #define PRG_ETH0_CLK_M250_DIV_SHIFT    7
 412 @@ -69,6 +65,8 @@ struct meson8b_dwmac {
 413
 414         struct clk_divider      m25_div;
 415         struct clk              *m25_div_clk;
 416 +
 417 +       u32                     tx_delay_ns;
 418  };
 419
 420  static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
 421 @@ -179,11 +177,19 @@ static int meson8b_init_prg_eth(struct m
 422  {
 423         int ret;
 424         unsigned long clk_rate;
 425 +       u8 tx_dly_val = 0;
 426
 427         switch (dwmac->phy_mode) {
 428         case PHY_INTERFACE_MODE_RGMII:
 429 -       case PHY_INTERFACE_MODE_RGMII_ID:
 430         case PHY_INTERFACE_MODE_RGMII_RXID:
 431 +               /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where
 432 +                * 8ns are exactly one cycle of the 125MHz RGMII TX clock):
 433 +                * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
 434 +                */
 435 +               tx_dly_val = dwmac->tx_delay_ns >> 1;
 436 +               /* fall through */
 437 +
 438 +       case PHY_INTERFACE_MODE_RGMII_ID:
 439         case PHY_INTERFACE_MODE_RGMII_TXID:
 440                 /* Generate a 25MHz clock for the PHY */
 441                 clk_rate = 25 * 1000 * 1000;
 442 @@ -196,9 +202,8 @@ static int meson8b_init_prg_eth(struct m
 443                 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
 444                                         PRG_ETH0_INVERTED_RMII_CLK, 0);
 445
 446 -               /* TX clock delay - all known boards use a 1/4 cycle delay */
 447                 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
 448 -                                       PRG_ETH0_TXDLY_QUARTER);
 449 +                                       tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
 450                 break;
 451
 452         case PHY_INTERFACE_MODE_RMII:
 453 @@ -284,6 +289,11 @@ static int meson8b_dwmac_probe(struct pl
 454                 goto err_remove_config_dt;
 455         }
 456
 457 +       /* use 2ns as fallback since this value was previously hardcoded */
 458 +       if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
 459 +                                &dwmac->tx_delay_ns))
 460 +               dwmac->tx_delay_ns = 2;
 461 +
 462         ret = meson8b_init_clk(dwmac);
 463         if (ret)
 464                 goto err_remove_config_dt;
 465 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
 466 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
 467 @@ -302,6 +302,122 @@ static const struct rk_gmac_ops rk3288_o
 468         .set_rmii_speed = rk3288_set_rmii_speed,
 469  };
 470
 471 +#define RK3328_GRF_MAC_CON0    0x0900
 472 +#define RK3328_GRF_MAC_CON1    0x0904
 473 +
 474 +/* RK3328_GRF_MAC_CON0 */
 475 +#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
 476 +#define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
 477 +
 478 +/* RK3328_GRF_MAC_CON1 */
 479 +#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
 480 +               (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 481 +#define RK3328_GMAC_PHY_INTF_SEL_RMII  \
 482 +               (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 483 +#define RK3328_GMAC_FLOW_CTRL          GRF_BIT(3)
 484 +#define RK3328_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(3)
 485 +#define RK3328_GMAC_SPEED_10M          GRF_CLR_BIT(2)
 486 +#define RK3328_GMAC_SPEED_100M         GRF_BIT(2)
 487 +#define RK3328_GMAC_RMII_CLK_25M       GRF_BIT(7)
 488 +#define RK3328_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(7)
 489 +#define RK3328_GMAC_CLK_125M           (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 490 +#define RK3328_GMAC_CLK_25M            (GRF_BIT(11) | GRF_BIT(12))
 491 +#define RK3328_GMAC_CLK_2_5M           (GRF_CLR_BIT(11) | GRF_BIT(12))
 492 +#define RK3328_GMAC_RMII_MODE          GRF_BIT(9)
 493 +#define RK3328_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(9)
 494 +#define RK3328_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(0)
 495 +#define RK3328_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(0)
 496 +#define RK3328_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(1)
 497 +#define RK3328_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(0)
 498 +
 499 +static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 500 +                               int tx_delay, int rx_delay)
 501 +{
 502 +       struct device *dev = &bsp_priv->pdev->dev;
 503 +
 504 +       if (IS_ERR(bsp_priv->grf)) {
 505 +               dev_err(dev, "Missing rockchip,grf property\n");
 506 +               return;
 507 +       }
 508 +
 509 +       regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 510 +                    RK3328_GMAC_PHY_INTF_SEL_RGMII |
 511 +                    RK3328_GMAC_RMII_MODE_CLR |
 512 +                    RK3328_GMAC_RXCLK_DLY_ENABLE |
 513 +                    RK3328_GMAC_TXCLK_DLY_ENABLE);
 514 +
 515 +       regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 516 +                    RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 517 +                    RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 518 +}
 519 +
 520 +static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 521 +{
 522 +       struct device *dev = &bsp_priv->pdev->dev;
 523 +
 524 +       if (IS_ERR(bsp_priv->grf)) {
 525 +               dev_err(dev, "Missing rockchip,grf property\n");
 526 +               return;
 527 +       }
 528 +
 529 +       regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 530 +                    RK3328_GMAC_PHY_INTF_SEL_RMII |
 531 +                    RK3328_GMAC_RMII_MODE);
 532 +
 533 +       /* set MAC to RMII mode */
 534 +       regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
 535 +}
 536 +
 537 +static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 538 +{
 539 +       struct device *dev = &bsp_priv->pdev->dev;
 540 +
 541 +       if (IS_ERR(bsp_priv->grf)) {
 542 +               dev_err(dev, "Missing rockchip,grf property\n");
 543 +               return;
 544 +       }
 545 +
 546 +       if (speed == 10)
 547 +               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 548 +                            RK3328_GMAC_CLK_2_5M);
 549 +       else if (speed == 100)
 550 +               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 551 +                            RK3328_GMAC_CLK_25M);
 552 +       else if (speed == 1000)
 553 +               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 554 +                            RK3328_GMAC_CLK_125M);
 555 +       else
 556 +               dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 557 +}
 558 +
 559 +static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 560 +{
 561 +       struct device *dev = &bsp_priv->pdev->dev;
 562 +
 563 +       if (IS_ERR(bsp_priv->grf)) {
 564 +               dev_err(dev, "Missing rockchip,grf property\n");
 565 +               return;
 566 +       }
 567 +
 568 +       if (speed == 10)
 569 +               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 570 +                            RK3328_GMAC_RMII_CLK_2_5M |
 571 +                            RK3328_GMAC_SPEED_10M);
 572 +       else if (speed == 100)
 573 +               regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 574 +                            RK3328_GMAC_RMII_CLK_25M |
 575 +                            RK3328_GMAC_SPEED_100M);
 576 +       else
 577 +               dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 578 +}
 579 +
 580 +static const struct rk_gmac_ops rk3328_ops = {
 581 +       .set_to_rgmii = rk3328_set_to_rgmii,
 582 +       .set_to_rmii = rk3328_set_to_rmii,
 583 +       .set_rgmii_speed = rk3328_set_rgmii_speed,
 584 +       .set_rmii_speed = rk3328_set_rmii_speed,
 585 +};
 586 +
 587  #define RK3366_GRF_SOC_CON6    0x0418
 588  #define RK3366_GRF_SOC_CON7    0x041c
 589
 590 @@ -1006,6 +1122,7 @@ static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops,
 591  static const struct of_device_id rk_gmac_dwmac_match[] = {
 592         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
 593         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
 594 +       { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
 595         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
 596         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
 597         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
 598 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
 599 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
 600 @@ -341,7 +341,7 @@ static int socfpga_dwmac_probe(struct pl
 601          * mode. Create a copy of the core reset handle so it can be used by
 602          * the driver later.
 603          */
 604 -       dwmac->stmmac_rst = stpriv->stmmac_rst;
 605 +       dwmac->stmmac_rst = stpriv->plat->stmmac_rst;
 606
 607         ret = socfpga_dwmac_set_phy_mode(dwmac);
 608         if (ret)
 609 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100.h
 610 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100.h
 611 @@ -12,10 +12,6 @@
 612    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 613    more details.
 614
 615 -  You should have received a copy of the GNU General Public License along with
 616 -  this program; if not, write to the Free Software Foundation, Inc.,
 617 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 618 -
 619    The full GNU General Public License is included in this distribution in
 620    the file called "COPYING".
 621
 622 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
 623 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
 624 @@ -10,10 +10,6 @@
 625    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 626    more details.
 627
 628 -  You should have received a copy of the GNU General Public License along with
 629 -  this program; if not, write to the Free Software Foundation, Inc.,
 630 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 631 -
 632    The full GNU General Public License is included in this distribution in
 633    the file called "COPYING".
 634
 635 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
 636 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
 637 @@ -16,10 +16,6 @@
 638    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 639    more details.
 640
 641 -  You should have received a copy of the GNU General Public License along with
 642 -  this program; if not, write to the Free Software Foundation, Inc.,
 643 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 644 -
 645    The full GNU General Public License is included in this distribution in
 646    the file called "COPYING".
 647
 648 @@ -96,17 +92,13 @@ static int dwmac1000_rx_ipc_enable(struc
 649         return !!(value & GMAC_CONTROL_IPC);
 650  }
 651
 652 -static void dwmac1000_dump_regs(struct mac_device_info *hw)
 653 +static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 654  {
 655         void __iomem *ioaddr = hw->pcsr;
 656         int i;
 657 -       pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
 658
 659 -       for (i = 0; i < 55; i++) {
 660 -               int offset = i * 4;
 661 -               pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
 662 -                       offset, readl(ioaddr + offset));
 663 -       }
 664 +       for (i = 0; i < 55; i++)
 665 +               reg_space[i] = readl(ioaddr + i * 4);
 666  }
 667
 668  static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 669 @@ -347,11 +339,14 @@ static int dwmac1000_irq_status(struct m
 670         return ret;
 671  }
 672
 673 -static void dwmac1000_set_eee_mode(struct mac_device_info *hw)
 674 +static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
 675 +                                  bool en_tx_lpi_clockgating)
 676  {
 677         void __iomem *ioaddr = hw->pcsr;
 678         u32 value;
 679
 680 +       /*TODO - en_tx_lpi_clockgating treatment */
 681 +
 682         /* Enable the link status receive on RGMII, SGMII ore SMII
 683          * receive path and instruct the transmit to enter in LPI
 684          * state.
 685 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
 686 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
 687 @@ -16,10 +16,6 @@
 688    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 689    more details.
 690
 691 -  You should have received a copy of the GNU General Public License along with
 692 -  this program; if not, write to the Free Software Foundation, Inc.,
 693 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 694 -
 695    The full GNU General Public License is included in this distribution in
 696    the file called "COPYING".
 697
 698 @@ -205,18 +201,14 @@ static void dwmac1000_dma_operation_mode
 699         writel(csr6, ioaddr + DMA_CONTROL);
 700  }
 701
 702 -static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
 703 +static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
 704  {
 705         int i;
 706 -       pr_info(" DMA registers\n");
 707 -       for (i = 0; i < 22; i++) {
 708 -               if ((i < 9) || (i > 17)) {
 709 -                       int offset = i * 4;
 710 -                       pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
 711 -                              (DMA_BUS_MODE + offset),
 712 -                              readl(ioaddr + DMA_BUS_MODE + offset));
 713 -               }
 714 -       }
 715 +
 716 +       for (i = 0; i < 22; i++)
 717 +               if ((i < 9) || (i > 17))
 718 +                       reg_space[DMA_BUS_MODE / 4 + i] =
 719 +                               readl(ioaddr + DMA_BUS_MODE + i * 4);
 720  }
 721
 722  static void dwmac1000_get_hw_feature(void __iomem *ioaddr,
 723 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
 724 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
 725 @@ -18,10 +18,6 @@
 726    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 727    more details.
 728
 729 -  You should have received a copy of the GNU General Public License along with
 730 -  this program; if not, write to the Free Software Foundation, Inc.,
 731 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 732 -
 733    The full GNU General Public License is included in this distribution in
 734    the file called "COPYING".
 735
 736 @@ -44,28 +40,18 @@ static void dwmac100_core_init(struct ma
 737  #endif
 738  }
 739
 740 -static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
 741 +static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
 742  {
 743         void __iomem *ioaddr = hw->pcsr;
 744 -       pr_info("\t----------------------------------------------\n"
 745 -               "\t  DWMAC 100 CSR (base addr = 0x%p)\n"
 746 -               "\t----------------------------------------------\n", ioaddr);
 747 -       pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
 748 -               readl(ioaddr + MAC_CONTROL));
 749 -       pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
 750 -               readl(ioaddr + MAC_ADDR_HIGH));
 751 -       pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
 752 -               readl(ioaddr + MAC_ADDR_LOW));
 753 -       pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
 754 -               MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
 755 -       pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
 756 -               MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
 757 -       pr_info("\tflow control (offset 0x%x): 0x%08x\n",
 758 -               MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
 759 -       pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
 760 -               readl(ioaddr + MAC_VLAN1));
 761 -       pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
 762 -               readl(ioaddr + MAC_VLAN2));
 763 +
 764 +       reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
 765 +       reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
 766 +       reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
 767 +       reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
 768 +       reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
 769 +       reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
 770 +       reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
 771 +       reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
 772  }
 773
 774  static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
 775 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
 776 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
 777 @@ -18,10 +18,6 @@
 778    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 779    more details.
 780
 781 -  You should have received a copy of the GNU General Public License along with
 782 -  this program; if not, write to the Free Software Foundation, Inc.,
 783 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 784 -
 785    The full GNU General Public License is included in this distribution in
 786    the file called "COPYING".
 787
 788 @@ -70,19 +66,18 @@ static void dwmac100_dma_operation_mode(
 789         writel(csr6, ioaddr + DMA_CONTROL);
 790  }
 791
 792 -static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
 793 +static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
 794  {
 795         int i;
 796
 797 -       pr_debug("DWMAC 100 DMA CSR\n");
 798         for (i = 0; i < 9; i++)
 799 -               pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
 800 -                        (DMA_BUS_MODE + i * 4),
 801 -                        readl(ioaddr + DMA_BUS_MODE + i * 4));
 802 -
 803 -       pr_debug("\tCSR20 (0x%x): 0x%08x, CSR21 (0x%x): 0x%08x\n",
 804 -                DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR),
 805 -                DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
 806 +               reg_space[DMA_BUS_MODE / 4 + i] =
 807 +                       readl(ioaddr + DMA_BUS_MODE + i * 4);
 808 +
 809 +       reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
 810 +               readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
 811 +       reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
 812 +               readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
 813  }
 814
 815  /* DMA controller has two counters to track the number of the missed frames. */
 816 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
 817 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
 818 @@ -22,6 +22,7 @@
 819  #define GMAC_HASH_TAB_32_63            0x00000014
 820  #define GMAC_RX_FLOW_CTRL              0x00000090
 821  #define GMAC_QX_TX_FLOW_CTRL(x)                (0x70 + x * 4)
 822 +#define GMAC_RXQ_CTRL0                 0x000000a0
 823  #define GMAC_INT_STATUS                        0x000000b0
 824  #define GMAC_INT_EN                    0x000000b4
 825  #define GMAC_PCS_BASE                  0x000000e0
 826 @@ -44,6 +45,11 @@
 827
 828  #define GMAC_MAX_PERFECT_ADDRESSES     128
 829
 830 +/* MAC RX Queue Enable */
 831 +#define GMAC_RX_QUEUE_CLEAR(queue)     ~(GENMASK(1, 0) << ((queue) * 2))
 832 +#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
 833 +#define GMAC_RX_DCB_QUEUE_ENABLE(queue)        BIT(((queue) * 2) + 1)
 834 +
 835  /* MAC Flow Control RX */
 836  #define GMAC_RX_FLOW_CTRL_RFE          BIT(0)
 837
 838 @@ -84,6 +90,19 @@ enum power_event {
 839         power_down = 0x00000001,
 840  };
 841
 842 +/* Energy Efficient Ethernet (EEE) for GMAC4
 843 + *
 844 + * LPI status, timer and control register offset
 845 + */
 846 +#define GMAC4_LPI_CTRL_STATUS  0xd0
 847 +#define GMAC4_LPI_TIMER_CTRL   0xd4
 848 +
 849 +/* LPI control and status defines */
 850 +#define GMAC4_LPI_CTRL_STATUS_LPITCSE  BIT(21) /* LPI Tx Clock Stop Enable */
 851 +#define GMAC4_LPI_CTRL_STATUS_LPITXA   BIT(19) /* Enable LPI TX Automate */
 852 +#define GMAC4_LPI_CTRL_STATUS_PLS      BIT(17) /* PHY Link Status */
 853 +#define GMAC4_LPI_CTRL_STATUS_LPIEN    BIT(16) /* LPI Enable */
 854 +
 855  /* MAC Debug bitmap */
 856  #define GMAC_DEBUG_TFCSTS_MASK         GENMASK(18, 17)
 857  #define GMAC_DEBUG_TFCSTS_SHIFT                17
 858 @@ -133,6 +152,8 @@ enum power_event {
 859  /* MAC HW features2 bitmap */
 860  #define GMAC_HW_FEAT_TXCHCNT           GENMASK(21, 18)
 861  #define GMAC_HW_FEAT_RXCHCNT           GENMASK(15, 12)
 862 +#define GMAC_HW_FEAT_TXQCNT            GENMASK(9, 6)
 863 +#define GMAC_HW_FEAT_RXQCNT            GENMASK(3, 0)
 864
 865  /* MAC HW ADDR regs */
 866  #define GMAC_HI_DCS                    GENMASK(18, 16)
 867 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
 868 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
 869 @@ -59,19 +59,24 @@ static void dwmac4_core_init(struct mac_
 870         writel(value, ioaddr + GMAC_INT_EN);
 871  }
 872
 873 -static void dwmac4_dump_regs(struct mac_device_info *hw)
 874 +static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
 875  {
 876         void __iomem *ioaddr = hw->pcsr;
 877 -       int i;
 878 +       u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
 879
 880 -       pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr);
 881 +       value &= GMAC_RX_QUEUE_CLEAR(queue);
 882 +       value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
 883
 884 -       for (i = 0; i < GMAC_REG_NUM; i++) {
 885 -               int offset = i * 4;
 886 +       writel(value, ioaddr + GMAC_RXQ_CTRL0);
 887 +}
 888
 889 -               pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
 890 -                        offset, readl(ioaddr + offset));
 891 -       }
 892 +static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 893 +{
 894 +       void __iomem *ioaddr = hw->pcsr;
 895 +       int i;
 896 +
 897 +       for (i = 0; i < GMAC_REG_NUM; i++)
 898 +               reg_space[i] = readl(ioaddr + i * 4);
 899  }
 900
 901  static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 902 @@ -126,6 +131,65 @@ static void dwmac4_get_umac_addr(struct
 903                                    GMAC_ADDR_LOW(reg_n));
 904  }
 905
 906 +static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 907 +                               bool en_tx_lpi_clockgating)
 908 +{
 909 +       void __iomem *ioaddr = hw->pcsr;
 910 +       u32 value;
 911 +
 912 +       /* Enable the link status receive on RGMII, SGMII ore SMII
 913 +        * receive path and instruct the transmit to enter in LPI
 914 +        * state.
 915 +        */
 916 +       value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 917 +       value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 918 +
 919 +       if (en_tx_lpi_clockgating)
 920 +               value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 921 +
 922 +       writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 923 +}
 924 +
 925 +static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 926 +{
 927 +       void __iomem *ioaddr = hw->pcsr;
 928 +       u32 value;
 929 +
 930 +       value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 931 +       value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 932 +       writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 933 +}
 934 +
 935 +static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 936 +{
 937 +       void __iomem *ioaddr = hw->pcsr;
 938 +       u32 value;
 939 +
 940 +       value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 941 +
 942 +       if (link)
 943 +               value |= GMAC4_LPI_CTRL_STATUS_PLS;
 944 +       else
 945 +               value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 946 +
 947 +       writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 948 +}
 949 +
 950 +static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 951 +{
 952 +       void __iomem *ioaddr = hw->pcsr;
 953 +       int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 954 +
 955 +       /* Program the timers in the LPI timer control register:
 956 +        * LS: minimum time (ms) for which the link
 957 +        *  status from PHY should be ok before transmitting
 958 +        *  the LPI pattern.
 959 +        * TW: minimum time (us) for which the core waits
 960 +        *  after it has stopped transmitting the LPI pattern.
 961 +        */
 962 +       writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 963 +}
 964 +
 965  static void dwmac4_set_filter(struct mac_device_info *hw,
 966                               struct net_device *dev)
 967  {
 968 @@ -392,12 +456,17 @@ static void dwmac4_debug(void __iomem *i
 969  static const struct stmmac_ops dwmac4_ops = {
 970         .core_init = dwmac4_core_init,
 971         .rx_ipc = dwmac4_rx_ipc_enable,
 972 +       .rx_queue_enable = dwmac4_rx_queue_enable,
 973         .dump_regs = dwmac4_dump_regs,
 974         .host_irq_status = dwmac4_irq_status,
 975         .flow_ctrl = dwmac4_flow_ctrl,
 976         .pmt = dwmac4_pmt,
 977         .set_umac_addr = dwmac4_set_umac_addr,
 978         .get_umac_addr = dwmac4_get_umac_addr,
 979 +       .set_eee_mode = dwmac4_set_eee_mode,
 980 +       .reset_eee_mode = dwmac4_reset_eee_mode,
 981 +       .set_eee_timer = dwmac4_set_eee_timer,
 982 +       .set_eee_pls = dwmac4_set_eee_pls,
 983         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 984         .pcs_rane = dwmac4_rane,
 985         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 986 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
 987 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
 988 @@ -103,7 +103,7 @@ static int dwmac4_wrback_get_rx_status(v
 989                         x->rx_mii++;
 990
 991                 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
 992 -                       x->rx_crc++;
 993 +                       x->rx_crc_errors++;
 994                         stats->rx_crc_errors++;
 995                 }
 996
 997 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
 998 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
 999 @@ -127,53 +127,51 @@ static void dwmac4_dma_init(void __iomem
1000                 dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i);
1001  }
1002
1003 -static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
1004 +static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
1005 +                                 u32 *reg_space)
1006  {
1007 -       pr_debug(" Channel %d\n", channel);
1008 -       pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
1009 -                readl(ioaddr + DMA_CHAN_CONTROL(channel)));
1010 -       pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
1011 -                readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
1012 -       pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
1013 -                readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
1014 -       pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
1015 -                readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
1016 -       pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
1017 -                readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
1018 -       pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
1019 -                readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
1020 -       pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
1021 -                readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
1022 -       pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
1023 -                readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
1024 -       pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
1025 -                readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
1026 -       pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
1027 -                readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
1028 -       pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
1029 -                readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
1030 -       pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
1031 -                readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
1032 -       pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
1033 -                readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
1034 -       pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
1035 -                readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
1036 -       pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
1037 -                readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
1038 -       pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
1039 -                readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
1040 -       pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
1041 -                readl(ioaddr + DMA_CHAN_STATUS(channel)));
1042 +       reg_space[DMA_CHAN_CONTROL(channel) / 4] =
1043 +               readl(ioaddr + DMA_CHAN_CONTROL(channel));
1044 +       reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
1045 +               readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
1046 +       reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
1047 +               readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
1048 +       reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
1049 +               readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
1050 +       reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
1051 +               readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
1052 +       reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
1053 +               readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
1054 +       reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
1055 +               readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
1056 +       reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
1057 +               readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
1058 +       reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
1059 +               readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
1060 +       reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
1061 +               readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
1062 +       reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
1063 +               readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
1064 +       reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
1065 +               readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
1066 +       reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
1067 +               readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
1068 +       reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
1069 +               readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
1070 +       reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
1071 +               readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
1072 +       reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
1073 +               readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
1074 +       reg_space[DMA_CHAN_STATUS(channel) / 4] =
1075 +               readl(ioaddr + DMA_CHAN_STATUS(channel));
1076  }
1077
1078 -static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
1079 +static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
1080  {
1081         int i;
1082
1083 -       pr_debug(" GMAC4 DMA registers\n");
1084 -
1085         for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
1086 -               _dwmac4_dump_dma_regs(ioaddr, i);
1087 +               _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
1088  }
1089
1090  static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)
1091 @@ -303,6 +301,11 @@ static void dwmac4_get_hw_feature(void _
1092                 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
1093         dma_cap->number_tx_channel =
1094                 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
1095 +       /* TX and RX number of queues */
1096 +       dma_cap->number_rx_queues =
1097 +               ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
1098 +       dma_cap->number_tx_queues =
1099 +               ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
1100
1101         /* IEEE 1588-2002 */
1102         dma_cap->time_stamp = 0;
1103 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
1104 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
1105 @@ -12,10 +12,6 @@
1106    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1107    more details.
1108
1109 -  You should have received a copy of the GNU General Public License along with
1110 -  this program; if not, write to the Free Software Foundation, Inc.,
1111 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1112 -
1113    The full GNU General Public License is included in this distribution in
1114    the file called "COPYING".
1115
1116 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
1117 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
1118 @@ -10,10 +10,6 @@
1119    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1120    more details.
1121
1122 -  You should have received a copy of the GNU General Public License along with
1123 -  this program; if not, write to the Free Software Foundation, Inc.,
1124 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1125 -
1126    The full GNU General Public License is included in this distribution in
1127    the file called "COPYING".
1128
1129 @@ -21,6 +17,7 @@
1130  *******************************************************************************/
1131
1132  #include <linux/io.h>
1133 +#include <linux/iopoll.h>
1134  #include "common.h"
1135  #include "dwmac_dma.h"
1136
1137 @@ -29,19 +26,16 @@
1138  int dwmac_dma_reset(void __iomem *ioaddr)
1139  {
1140         u32 value = readl(ioaddr + DMA_BUS_MODE);
1141 -       int limit;
1142 +       int err;
1143
1144         /* DMA SW reset */
1145         value |= DMA_BUS_MODE_SFT_RESET;
1146         writel(value, ioaddr + DMA_BUS_MODE);
1147 -       limit = 10;
1148 -       while (limit--) {
1149 -               if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
1150 -                       break;
1151 -               mdelay(10);
1152 -       }
1153
1154 -       if (limit < 0)
1155 +       err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
1156 +                                !(value & DMA_BUS_MODE_SFT_RESET),
1157 +                                100000, 10000);
1158 +       if (err)
1159                 return -EBUSY;
1160
1161         return 0;
1162 @@ -102,7 +96,7 @@ static void show_tx_process_state(unsign
1163                 pr_debug("- TX (Stopped): Reset or Stop command\n");
1164                 break;
1165         case 1:
1166 -               pr_debug("- TX (Running):Fetching the Tx desc\n");
1167 +               pr_debug("- TX (Running): Fetching the Tx desc\n");
1168                 break;
1169         case 2:
1170                 pr_debug("- TX (Running): Waiting for end of tx\n");
1171 @@ -136,7 +130,7 @@ static void show_rx_process_state(unsign
1172                 pr_debug("- RX (Running): Fetching the Rx desc\n");
1173                 break;
1174         case 2:
1175 -               pr_debug("- RX (Running):Checking for end of pkt\n");
1176 +               pr_debug("- RX (Running): Checking for end of pkt\n");
1177                 break;
1178         case 3:
1179                 pr_debug("- RX (Running): Waiting for Rx pkt\n");
1180 @@ -246,7 +240,7 @@ void stmmac_set_mac_addr(void __iomem *i
1181         unsigned long data;
1182
1183         data = (addr[5] << 8) | addr[4];
1184 -       /* For MAC Addr registers se have to set the Address Enable (AE)
1185 +       /* For MAC Addr registers we have to set the Address Enable (AE)
1186          * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1187          * is RO.
1188          */
1189 @@ -261,9 +255,9 @@ void stmmac_set_mac(void __iomem *ioaddr
1190         u32 value = readl(ioaddr + MAC_CTRL_REG);
1191
1192         if (enable)
1193 -               value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
1194 +               value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
1195         else
1196 -               value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
1197 +               value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
1198
1199         writel(value, ioaddr + MAC_CTRL_REG);
1200  }
1201 --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
1202 +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
1203 @@ -12,10 +12,6 @@
1204    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1205    more details.
1206
1207 -  You should have received a copy of the GNU General Public License along with
1208 -  this program; if not, write to the Free Software Foundation, Inc.,
1209 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1210 -
1211    The full GNU General Public License is included in this distribution in
1212    the file called "COPYING".
1213
1214 @@ -225,7 +221,7 @@ static int enh_desc_get_rx_status(void *
1215                         x->rx_mii++;
1216
1217                 if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
1218 -                       x->rx_crc++;
1219 +                       x->rx_crc_errors++;
1220                         stats->rx_crc_errors++;
1221                 }
1222                 ret = discard_frame;
1223 --- a/drivers/net/ethernet/stmicro/stmmac/mmc.h
1224 +++ b/drivers/net/ethernet/stmicro/stmmac/mmc.h
1225 @@ -12,10 +12,6 @@
1226    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1227    more details.
1228
1229 -  You should have received a copy of the GNU General Public License along with
1230 -  this program; if not, write to the Free Software Foundation, Inc.,
1231 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1232 -
1233    The full GNU General Public License is included in this distribution in
1234    the file called "COPYING".
1235
1236 --- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
1237 +++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
1238 @@ -12,10 +12,6 @@
1239    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1240    more details.
1241
1242 -  You should have received a copy of the GNU General Public License along with
1243 -  this program; if not, write to the Free Software Foundation, Inc.,
1244 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1245 -
1246    The full GNU General Public License is included in this distribution in
1247    the file called "COPYING".
1248
1249 --- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
1250 +++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
1251 @@ -12,10 +12,6 @@
1252    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1253    more details.
1254
1255 -  You should have received a copy of the GNU General Public License along with
1256 -  this program; if not, write to the Free Software Foundation, Inc.,
1257 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1258 -
1259    The full GNU General Public License is included in this distribution in
1260    the file called "COPYING".
1261
1262 @@ -115,7 +111,7 @@ static int ndesc_get_rx_status(void *dat
1263                         stats->collisions++;
1264                 }
1265                 if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
1266 -                       x->rx_crc++;
1267 +                       x->rx_crc_errors++;
1268                         stats->rx_crc_errors++;
1269                 }
1270                 ret = discard_frame;
1271 --- a/drivers/net/ethernet/stmicro/stmmac/ring_mode.c
1272 +++ b/drivers/net/ethernet/stmicro/stmmac/ring_mode.c
1273 @@ -16,10 +16,6 @@
1274    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1275    more details.
1276
1277 -  You should have received a copy of the GNU General Public License along with
1278 -  this program; if not, write to the Free Software Foundation, Inc.,
1279 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1280 -
1281    The full GNU General Public License is included in this distribution in
1282    the file called "COPYING".
1283
1284 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
1285 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
1286 @@ -10,10 +10,6 @@
1287    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1288    more details.
1289
1290 -  You should have received a copy of the GNU General Public License along with
1291 -  this program; if not, write to the Free Software Foundation, Inc.,
1292 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1293 -
1294    The full GNU General Public License is included in this distribution in
1295    the file called "COPYING".
1296
1297 @@ -106,9 +102,6 @@ struct stmmac_priv {
1298         u32 msg_enable;
1299         int wolopts;
1300         int wol_irq;
1301 -       struct clk *stmmac_clk;
1302 -       struct clk *pclk;
1303 -       struct reset_control *stmmac_rst;
1304         int clk_csr;
1305         struct timer_list eee_ctrl_timer;
1306         int lpi_irq;
1307 @@ -120,8 +113,6 @@ struct stmmac_priv {
1308         struct ptp_clock *ptp_clock;
1309         struct ptp_clock_info ptp_clock_ops;
1310         unsigned int default_addend;
1311 -       struct clk *clk_ptp_ref;
1312 -       unsigned int clk_ptp_rate;
1313         u32 adv_ts;
1314         int use_riwt;
1315         int irq_wake;
1316 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
1317 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
1318 @@ -12,10 +12,6 @@
1319    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1320    more details.
1321
1322 -  You should have received a copy of the GNU General Public License along with
1323 -  this program; if not, write to the Free Software Foundation, Inc.,
1324 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1325 -
1326    The full GNU General Public License is included in this distribution in
1327    the file called "COPYING".
1328
1329 @@ -65,7 +61,7 @@ static const struct stmmac_stats stmmac_
1330         STMMAC_STAT(overflow_error),
1331         STMMAC_STAT(ipc_csum_error),
1332         STMMAC_STAT(rx_collision),
1333 -       STMMAC_STAT(rx_crc),
1334 +       STMMAC_STAT(rx_crc_errors),
1335         STMMAC_STAT(dribbling_bit),
1336         STMMAC_STAT(rx_length),
1337         STMMAC_STAT(rx_mii),
1338 @@ -439,32 +435,14 @@ static int stmmac_ethtool_get_regs_len(s
1339  static void stmmac_ethtool_gregs(struct net_device *dev,
1340                           struct ethtool_regs *regs, void *space)
1341  {
1342 -       int i;
1343         u32 *reg_space = (u32 *) space;
1344
1345         struct stmmac_priv *priv = netdev_priv(dev);
1346
1347         memset(reg_space, 0x0, REG_SPACE_SIZE);
1348
1349 -       if (!(priv->plat->has_gmac || priv->plat->has_gmac4)) {
1350 -               /* MAC registers */
1351 -               for (i = 0; i < 12; i++)
1352 -                       reg_space[i] = readl(priv->ioaddr + (i * 4));
1353 -               /* DMA registers */
1354 -               for (i = 0; i < 9; i++)
1355 -                       reg_space[i + 12] =
1356 -                           readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
1357 -               reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
1358 -               reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
1359 -       } else {
1360 -               /* MAC registers */
1361 -               for (i = 0; i < 55; i++)
1362 -                       reg_space[i] = readl(priv->ioaddr + (i * 4));
1363 -               /* DMA registers */
1364 -               for (i = 0; i < 22; i++)
1365 -                       reg_space[i + 55] =
1366 -                           readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
1367 -       }
1368 +       priv->hw->mac->dump_regs(priv->hw, reg_space);
1369 +       priv->hw->dma->dump_regs(priv->ioaddr, reg_space);
1370  }
1371
1372  static void
1373 @@ -712,7 +690,7 @@ static int stmmac_ethtool_op_set_eee(str
1374
1375  static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
1376  {
1377 -       unsigned long clk = clk_get_rate(priv->stmmac_clk);
1378 +       unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
1379
1380         if (!clk)
1381                 return 0;
1382 @@ -722,7 +700,7 @@ static u32 stmmac_usec2riwt(u32 usec, st
1383
1384  static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
1385  {
1386 -       unsigned long clk = clk_get_rate(priv->stmmac_clk);
1387 +       unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
1388
1389         if (!clk)
1390                 return 0;
1391 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
1392 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
1393 @@ -12,10 +12,6 @@
1394    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1395    more details.
1396
1397 -  You should have received a copy of the GNU General Public License along with
1398 -  this program; if not, write to the Free Software Foundation, Inc.,
1399 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1400 -
1401    The full GNU General Public License is included in this distribution in
1402    the file called "COPYING".
1403
1404 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
1405 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
1406 @@ -13,10 +13,6 @@
1407    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1408    more details.
1409
1410 -  You should have received a copy of the GNU General Public License along with
1411 -  this program; if not, write to the Free Software Foundation, Inc.,
1412 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1413 -
1414    The full GNU General Public License is included in this distribution in
1415    the file called "COPYING".
1416
1417 @@ -158,7 +154,7 @@ static void stmmac_clk_csr_set(struct st
1418  {
1419         u32 clk_rate;
1420
1421 -       clk_rate = clk_get_rate(priv->stmmac_clk);
1422 +       clk_rate = clk_get_rate(priv->plat->stmmac_clk);
1423
1424         /* Platform provided default clk_csr would be assumed valid
1425          * for all other cases except for the below mentioned ones.
1426 @@ -191,7 +187,7 @@ static void print_pkt(unsigned char *buf
1427
1428  static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
1429  {
1430 -       unsigned avail;
1431 +       u32 avail;
1432
1433         if (priv->dirty_tx > priv->cur_tx)
1434                 avail = priv->dirty_tx - priv->cur_tx - 1;
1435 @@ -203,7 +199,7 @@ static inline u32 stmmac_tx_avail(struct
1436
1437  static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
1438  {
1439 -       unsigned dirty;
1440 +       u32 dirty;
1441
1442         if (priv->dirty_rx <= priv->cur_rx)
1443                 dirty = priv->cur_rx - priv->dirty_rx;
1444 @@ -216,7 +212,7 @@ static inline u32 stmmac_rx_dirty(struct
1445  /**
1446   * stmmac_hw_fix_mac_speed - callback for speed selection
1447   * @priv: driver private structure
1448 - * Description: on some platforms (e.g. ST), some HW system configuraton
1449 + * Description: on some platforms (e.g. ST), some HW system configuration
1450   * registers have to be set according to the link speed negotiated.
1451   */
1452  static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
1453 @@ -239,7 +235,8 @@ static void stmmac_enable_eee_mode(struc
1454         /* Check and enter in LPI mode */
1455         if ((priv->dirty_tx == priv->cur_tx) &&
1456             (priv->tx_path_in_lpi_mode == false))
1457 -               priv->hw->mac->set_eee_mode(priv->hw);
1458 +               priv->hw->mac->set_eee_mode(priv->hw,
1459 +                                           priv->plat->en_tx_lpi_clockgating);
1460  }
1461
1462  /**
1463 @@ -415,7 +412,7 @@ static void stmmac_get_rx_hwtstamp(struc
1464  /**
1465   *  stmmac_hwtstamp_ioctl - control hardware timestamping.
1466   *  @dev: device pointer.
1467 - *  @ifr: An IOCTL specefic structure, that can contain a pointer to
1468 + *  @ifr: An IOCTL specific structure, that can contain a pointer to
1469   *  a proprietary structure used to pass information to the driver.
1470   *  Description:
1471   *  This function configures the MAC to enable/disable both outgoing(TX)
1472 @@ -606,7 +603,7 @@ static int stmmac_hwtstamp_ioctl(struct
1473
1474                 /* program Sub Second Increment reg */
1475                 sec_inc = priv->hw->ptp->config_sub_second_increment(
1476 -                       priv->ptpaddr, priv->clk_ptp_rate,
1477 +                       priv->ptpaddr, priv->plat->clk_ptp_rate,
1478                         priv->plat->has_gmac4);
1479                 temp = div_u64(1000000000ULL, sec_inc);
1480
1481 @@ -616,7 +613,7 @@ static int stmmac_hwtstamp_ioctl(struct
1482                  * where, freq_div_ratio = 1e9ns/sec_inc
1483                  */
1484                 temp = (u64)(temp << 32);
1485 -               priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
1486 +               priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
1487                 priv->hw->ptp->config_addend(priv->ptpaddr,
1488                                              priv->default_addend);
1489
1490 @@ -644,18 +641,6 @@ static int stmmac_init_ptp(struct stmmac
1491         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
1492                 return -EOPNOTSUPP;
1493
1494 -       /* Fall-back to main clock in case of no PTP ref is passed */
1495 -       priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
1496 -       if (IS_ERR(priv->clk_ptp_ref)) {
1497 -               priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
1498 -               priv->clk_ptp_ref = NULL;
1499 -               netdev_dbg(priv->dev, "PTP uses main clock\n");
1500 -       } else {
1501 -               clk_prepare_enable(priv->clk_ptp_ref);
1502 -               priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
1503 -               netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
1504 -       }
1505 -
1506         priv->adv_ts = 0;
1507         /* Check if adv_ts can be enabled for dwmac 4.x core */
1508         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
1509 @@ -682,8 +667,8 @@ static int stmmac_init_ptp(struct stmmac
1510
1511  static void stmmac_release_ptp(struct stmmac_priv *priv)
1512  {
1513 -       if (priv->clk_ptp_ref)
1514 -               clk_disable_unprepare(priv->clk_ptp_ref);
1515 +       if (priv->plat->clk_ptp_ref)
1516 +               clk_disable_unprepare(priv->plat->clk_ptp_ref);
1517         stmmac_ptp_unregister(priv);
1518  }
1519
1520 @@ -704,7 +689,7 @@ static void stmmac_adjust_link(struct ne
1521         int new_state = 0;
1522         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
1523
1524 -       if (phydev == NULL)
1525 +       if (!phydev)
1526                 return;
1527
1528         spin_lock_irqsave(&priv->lock, flags);
1529 @@ -731,33 +716,36 @@ static void stmmac_adjust_link(struct ne
1530                         new_state = 1;
1531                         switch (phydev->speed) {
1532                         case 1000:
1533 -                               if (likely((priv->plat->has_gmac) ||
1534 -                                          (priv->plat->has_gmac4)))
1535 +                               if (priv->plat->has_gmac ||
1536 +                                   priv->plat->has_gmac4)
1537                                         ctrl &= ~priv->hw->link.port;
1538 -                               stmmac_hw_fix_mac_speed(priv);
1539                                 break;
1540                         case 100:
1541 +                               if (priv->plat->has_gmac ||
1542 +                                   priv->plat->has_gmac4) {
1543 +                                       ctrl |= priv->hw->link.port;
1544 +                                       ctrl |= priv->hw->link.speed;
1545 +                               } else {
1546 +                                       ctrl &= ~priv->hw->link.port;
1547 +                               }
1548 +                               break;
1549                         case 10:
1550 -                               if (likely((priv->plat->has_gmac) ||
1551 -                                          (priv->plat->has_gmac4))) {
1552 +                               if (priv->plat->has_gmac ||
1553 +                                   priv->plat->has_gmac4) {
1554                                         ctrl |= priv->hw->link.port;
1555 -                                       if (phydev->speed == SPEED_100) {
1556 -                                               ctrl |= priv->hw->link.speed;
1557 -                                       } else {
1558 -                                               ctrl &= ~(priv->hw->link.speed);
1559 -                                       }
1560 +                                       ctrl &= ~(priv->hw->link.speed);
1561                                 } else {
1562                                         ctrl &= ~priv->hw->link.port;
1563                                 }
1564 -                               stmmac_hw_fix_mac_speed(priv);
1565                                 break;
1566                         default:
1567                                 netif_warn(priv, link, priv->dev,
1568 -                                          "Speed (%d) not 10/100\n",
1569 -                                          phydev->speed);
1570 +                                          "broken speed: %d\n", phydev->speed);
1571 +                               phydev->speed = SPEED_UNKNOWN;
1572                                 break;
1573                         }
1574 -
1575 +                       if (phydev->speed != SPEED_UNKNOWN)
1576 +                               stmmac_hw_fix_mac_speed(priv);
1577                         priv->speed = phydev->speed;
1578                 }
1579
1580 @@ -770,8 +758,8 @@ static void stmmac_adjust_link(struct ne
1581         } else if (priv->oldlink) {
1582                 new_state = 1;
1583                 priv->oldlink = 0;
1584 -               priv->speed = 0;
1585 -               priv->oldduplex = -1;
1586 +               priv->speed = SPEED_UNKNOWN;
1587 +               priv->oldduplex = DUPLEX_UNKNOWN;
1588         }
1589
1590         if (new_state && netif_msg_link(priv))
1591 @@ -833,8 +821,8 @@ static int stmmac_init_phy(struct net_de
1592         int interface = priv->plat->interface;
1593         int max_speed = priv->plat->max_speed;
1594         priv->oldlink = 0;
1595 -       priv->speed = 0;
1596 -       priv->oldduplex = -1;
1597 +       priv->speed = SPEED_UNKNOWN;
1598 +       priv->oldduplex = DUPLEX_UNKNOWN;
1599
1600         if (priv->plat->phy_node) {
1601                 phydev = of_phy_connect(dev, priv->plat->phy_node,
1602 @@ -886,9 +874,7 @@ static int stmmac_init_phy(struct net_de
1603         if (phydev->is_pseudo_fixed_link)
1604                 phydev->irq = PHY_POLL;
1605
1606 -       netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
1607 -                  __func__, phydev->phy_id, phydev->link);
1608 -
1609 +       phy_attached_info(phydev);
1610         return 0;
1611  }
1612
1613 @@ -1014,7 +1000,7 @@ static void stmmac_free_rx_buffers(struc
1614   * @dev: net device structure
1615   * @flags: gfp flag.
1616   * Description: this function initializes the DMA RX/TX descriptors
1617 - * and allocates the socket buffers. It suppors the chained and ring
1618 + * and allocates the socket buffers. It supports the chained and ring
1619   * modes.
1620   */
1621  static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1622 @@ -1127,13 +1113,6 @@ static void dma_free_tx_skbufs(struct st
1623         int i;
1624
1625         for (i = 0; i < DMA_TX_SIZE; i++) {
1626 -               struct dma_desc *p;
1627 -
1628 -               if (priv->extend_desc)
1629 -                       p = &((priv->dma_etx + i)->basic);
1630 -               else
1631 -                       p = priv->dma_tx + i;
1632 -
1633                 if (priv->tx_skbuff_dma[i].buf) {
1634                         if (priv->tx_skbuff_dma[i].map_as_page)
1635                                 dma_unmap_page(priv->device,
1636 @@ -1147,7 +1126,7 @@ static void dma_free_tx_skbufs(struct st
1637                                                  DMA_TO_DEVICE);
1638                 }
1639
1640 -               if (priv->tx_skbuff[i] != NULL) {
1641 +               if (priv->tx_skbuff[i]) {
1642                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1643                         priv->tx_skbuff[i] = NULL;
1644                         priv->tx_skbuff_dma[i].buf = 0;
1645 @@ -1271,6 +1250,28 @@ static void free_dma_desc_resources(stru
1646  }
1647
1648  /**
1649 + *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1650 + *  @priv: driver private structure
1651 + *  Description: It is used for enabling the rx queues in the MAC
1652 + */
1653 +static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1654 +{
1655 +       int rx_count = priv->dma_cap.number_rx_queues;
1656 +       int queue = 0;
1657 +
1658 +       /* If GMAC does not have multiple queues, then this is not necessary*/
1659 +       if (rx_count == 1)
1660 +               return;
1661 +
1662 +       /**
1663 +        *  If the core is synthesized with multiple rx queues / multiple
1664 +        *  dma channels, then rx queues will be disabled by default.
1665 +        *  For now only rx queue 0 is enabled.
1666 +        */
1667 +       priv->hw->mac->rx_queue_enable(priv->hw, queue);
1668 +}
1669 +
1670 +/**
1671   *  stmmac_dma_operation_mode - HW DMA operation mode
1672   *  @priv: driver private structure
1673   *  Description: it is used for configuring the DMA operation mode register in
1674 @@ -1671,10 +1672,6 @@ static int stmmac_hw_setup(struct net_de
1675         /* Copy the MAC addr into the HW  */
1676         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1677
1678 -       /* If required, perform hw setup of the bus. */
1679 -       if (priv->plat->bus_setup)
1680 -               priv->plat->bus_setup(priv->ioaddr);
1681 -
1682         /* PS and related bits will be programmed according to the speed */
1683         if (priv->hw->pcs) {
1684                 int speed = priv->plat->mac_port_sel_speed;
1685 @@ -1691,6 +1688,10 @@ static int stmmac_hw_setup(struct net_de
1686         /* Initialize the MAC Core */
1687         priv->hw->mac->core_init(priv->hw, dev->mtu);
1688
1689 +       /* Initialize MAC RX Queues */
1690 +       if (priv->hw->mac->rx_queue_enable)
1691 +               stmmac_mac_enable_rx_queues(priv);
1692 +
1693         ret = priv->hw->mac->rx_ipc(priv->hw);
1694         if (!ret) {
1695                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
1696 @@ -1711,8 +1712,10 @@ static int stmmac_hw_setup(struct net_de
1697
1698         if (init_ptp) {
1699                 ret = stmmac_init_ptp(priv);
1700 -               if (ret)
1701 -                       netdev_warn(priv->dev, "fail to init PTP.\n");
1702 +               if (ret == -EOPNOTSUPP)
1703 +                       netdev_warn(priv->dev, "PTP not supported by HW\n");
1704 +               else if (ret)
1705 +                       netdev_warn(priv->dev, "PTP init failed\n");
1706         }
1707
1708  #ifdef CONFIG_DEBUG_FS
1709 @@ -1726,11 +1729,6 @@ static int stmmac_hw_setup(struct net_de
1710         priv->hw->dma->start_tx(priv->ioaddr);
1711         priv->hw->dma->start_rx(priv->ioaddr);
1712
1713 -       /* Dump DMA/MAC registers */
1714 -       if (netif_msg_hw(priv)) {
1715 -               priv->hw->mac->dump_regs(priv->hw);
1716 -               priv->hw->dma->dump_regs(priv->ioaddr);
1717 -       }
1718         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1719
1720         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1721 @@ -2520,7 +2518,7 @@ static int stmmac_rx(struct stmmac_priv
1722                 if (unlikely(status == discard_frame)) {
1723                         priv->dev->stats.rx_errors++;
1724                         if (priv->hwts_rx_en && !priv->extend_desc) {
1725 -                               /* DESC2 & DESC3 will be overwitten by device
1726 +                               /* DESC2 & DESC3 will be overwritten by device
1727                                  * with timestamp value, hence reinitialize
1728                                  * them in stmmac_rx_refill() function so that
1729                                  * device can reuse it.
1730 @@ -2543,7 +2541,7 @@ static int stmmac_rx(struct stmmac_priv
1731
1732                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
1733
1734 -                       /*  If frame length is greather than skb buffer size
1735 +                       /*  If frame length is greater than skb buffer size
1736                          *  (preallocated during init) then the packet is
1737                          *  ignored
1738                          */
1739 @@ -2763,7 +2761,7 @@ static netdev_features_t stmmac_fix_feat
1740         /* Some GMAC devices have a bugged Jumbo frame support that
1741          * needs to have the Tx COE disabled for oversized frames
1742          * (due to limited buffer sizes). In this case we disable
1743 -        * the TX csum insertionin the TDES and not use SF.
1744 +        * the TX csum insertion in the TDES and not use SF.
1745          */
1746         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1747                 features &= ~NETIF_F_CSUM_MASK;
1748 @@ -2909,9 +2907,7 @@ static void sysfs_display_ring(void *hea
1749         struct dma_desc *p = (struct dma_desc *)head;
1750
1751         for (i = 0; i < size; i++) {
1752 -               u64 x;
1753                 if (extend_desc) {
1754 -                       x = *(u64 *) ep;
1755                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1756                                    i, (unsigned int)virt_to_phys(ep),
1757                                    le32_to_cpu(ep->basic.des0),
1758 @@ -2920,7 +2916,6 @@ static void sysfs_display_ring(void *hea
1759                                    le32_to_cpu(ep->basic.des3));
1760                         ep++;
1761                 } else {
1762 -                       x = *(u64 *) p;
1763                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1764                                    i, (unsigned int)virt_to_phys(ep),
1765                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
1766 @@ -2990,7 +2985,7 @@ static int stmmac_sysfs_dma_cap_read(str
1767                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1768         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1769                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1770 -       seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1771 +       seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
1772                    (priv->dma_cap.pcs) ? "Y" : "N");
1773         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1774                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1775 @@ -3266,44 +3261,8 @@ int stmmac_dvr_probe(struct device *devi
1776         if ((phyaddr >= 0) && (phyaddr <= 31))
1777                 priv->plat->phy_addr = phyaddr;
1778
1779 -       priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
1780 -       if (IS_ERR(priv->stmmac_clk)) {
1781 -               netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n",
1782 -                           __func__);
1783 -               /* If failed to obtain stmmac_clk and specific clk_csr value
1784 -                * is NOT passed from the platform, probe fail.
1785 -                */
1786 -               if (!priv->plat->clk_csr) {
1787 -                       ret = PTR_ERR(priv->stmmac_clk);
1788 -                       goto error_clk_get;
1789 -               } else {
1790 -                       priv->stmmac_clk = NULL;
1791 -               }
1792 -       }
1793 -       clk_prepare_enable(priv->stmmac_clk);
1794 -
1795 -       priv->pclk = devm_clk_get(priv->device, "pclk");
1796 -       if (IS_ERR(priv->pclk)) {
1797 -               if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
1798 -                       ret = -EPROBE_DEFER;
1799 -                       goto error_pclk_get;
1800 -               }
1801 -               priv->pclk = NULL;
1802 -       }
1803 -       clk_prepare_enable(priv->pclk);
1804 -
1805 -       priv->stmmac_rst = devm_reset_control_get(priv->device,
1806 -                                                 STMMAC_RESOURCE_NAME);
1807 -       if (IS_ERR(priv->stmmac_rst)) {
1808 -               if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
1809 -                       ret = -EPROBE_DEFER;
1810 -                       goto error_hw_init;
1811 -               }
1812 -               dev_info(priv->device, "no reset control found\n");
1813 -               priv->stmmac_rst = NULL;
1814 -       }
1815 -       if (priv->stmmac_rst)
1816 -               reset_control_deassert(priv->stmmac_rst);
1817 +       if (priv->plat->stmmac_rst)
1818 +               reset_control_deassert(priv->plat->stmmac_rst);
1819
1820         /* Init MAC and get the capabilities */
1821         ret = stmmac_hw_init(priv);
1822 @@ -3389,10 +3348,6 @@ error_netdev_register:
1823  error_mdio_register:
1824         netif_napi_del(&priv->napi);
1825  error_hw_init:
1826 -       clk_disable_unprepare(priv->pclk);
1827 -error_pclk_get:
1828 -       clk_disable_unprepare(priv->stmmac_clk);
1829 -error_clk_get:
1830         free_netdev(ndev);
1831
1832         return ret;
1833 @@ -3418,10 +3373,10 @@ int stmmac_dvr_remove(struct device *dev
1834         stmmac_set_mac(priv->ioaddr, false);
1835         netif_carrier_off(ndev);
1836         unregister_netdev(ndev);
1837 -       if (priv->stmmac_rst)
1838 -               reset_control_assert(priv->stmmac_rst);
1839 -       clk_disable_unprepare(priv->pclk);
1840 -       clk_disable_unprepare(priv->stmmac_clk);
1841 +       if (priv->plat->stmmac_rst)
1842 +               reset_control_assert(priv->plat->stmmac_rst);
1843 +       clk_disable_unprepare(priv->plat->pclk);
1844 +       clk_disable_unprepare(priv->plat->stmmac_clk);
1845         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1846             priv->hw->pcs != STMMAC_PCS_TBI &&
1847             priv->hw->pcs != STMMAC_PCS_RTBI)
1848 @@ -3470,14 +3425,14 @@ int stmmac_suspend(struct device *dev)
1849                 stmmac_set_mac(priv->ioaddr, false);
1850                 pinctrl_pm_select_sleep_state(priv->device);
1851                 /* Disable clock in case of PWM is off */
1852 -               clk_disable(priv->pclk);
1853 -               clk_disable(priv->stmmac_clk);
1854 +               clk_disable(priv->plat->pclk);
1855 +               clk_disable(priv->plat->stmmac_clk);
1856         }
1857         spin_unlock_irqrestore(&priv->lock, flags);
1858
1859         priv->oldlink = 0;
1860 -       priv->speed = 0;
1861 -       priv->oldduplex = -1;
1862 +       priv->speed = SPEED_UNKNOWN;
1863 +       priv->oldduplex = DUPLEX_UNKNOWN;
1864         return 0;
1865  }
1866  EXPORT_SYMBOL_GPL(stmmac_suspend);
1867 @@ -3510,9 +3465,9 @@ int stmmac_resume(struct device *dev)
1868                 priv->irq_wake = 0;
1869         } else {
1870                 pinctrl_pm_select_default_state(priv->device);
1871 -               /* enable the clk prevously disabled */
1872 -               clk_enable(priv->stmmac_clk);
1873 -               clk_enable(priv->pclk);
1874 +               /* enable the clk previously disabled */
1875 +               clk_enable(priv->plat->stmmac_clk);
1876 +               clk_enable(priv->plat->pclk);
1877                 /* reset the phy so that it's ready */
1878                 if (priv->mii)
1879                         stmmac_mdio_reset(priv->mii);
1880 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
1881 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
1882 @@ -13,10 +13,6 @@
1883    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1884    more details.
1885
1886 -  You should have received a copy of the GNU General Public License along with
1887 -  this program; if not, write to the Free Software Foundation, Inc.,
1888 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1889 -
1890    The full GNU General Public License is included in this distribution in
1891    the file called "COPYING".
1892
1893 @@ -24,13 +20,14 @@
1894    Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
1895  *******************************************************************************/
1896
1897 +#include <linux/io.h>
1898 +#include <linux/iopoll.h>
1899  #include <linux/mii.h>
1900 -#include <linux/phy.h>
1901 -#include <linux/slab.h>
1902  #include <linux/of.h>
1903  #include <linux/of_gpio.h>
1904  #include <linux/of_mdio.h>
1905 -#include <asm/io.h>
1906 +#include <linux/phy.h>
1907 +#include <linux/slab.h>
1908
1909  #include "stmmac.h"
1910
1911 @@ -42,22 +39,6 @@
1912  #define MII_GMAC4_WRITE                        (1 << MII_GMAC4_GOC_SHIFT)
1913  #define MII_GMAC4_READ                 (3 << MII_GMAC4_GOC_SHIFT)
1914
1915 -static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
1916 -{
1917 -       unsigned long curr;
1918 -       unsigned long finish = jiffies + 3 * HZ;
1919 -
1920 -       do {
1921 -               curr = jiffies;
1922 -               if (readl(ioaddr + mii_addr) & MII_BUSY)
1923 -                       cpu_relax();
1924 -               else
1925 -                       return 0;
1926 -       } while (!time_after_eq(curr, finish));
1927 -
1928 -       return -EBUSY;
1929 -}
1930 -
1931  /**
1932   * stmmac_mdio_read
1933   * @bus: points to the mii_bus structure
1934 @@ -74,7 +55,7 @@ static int stmmac_mdio_read(struct mii_b
1935         struct stmmac_priv *priv = netdev_priv(ndev);
1936         unsigned int mii_address = priv->hw->mii.addr;
1937         unsigned int mii_data = priv->hw->mii.data;
1938 -
1939 +       u32 v;
1940         int data;
1941         u32 value = MII_BUSY;
1942
1943 @@ -86,12 +67,14 @@ static int stmmac_mdio_read(struct mii_b
1944         if (priv->plat->has_gmac4)
1945                 value |= MII_GMAC4_READ;
1946
1947 -       if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
1948 +       if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
1949 +                              100, 10000))
1950                 return -EBUSY;
1951
1952         writel(value, priv->ioaddr + mii_address);
1953
1954 -       if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
1955 +       if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
1956 +                              100, 10000))
1957                 return -EBUSY;
1958
1959         /* Read the data from the MII data register */
1960 @@ -115,7 +98,7 @@ static int stmmac_mdio_write(struct mii_
1961         struct stmmac_priv *priv = netdev_priv(ndev);
1962         unsigned int mii_address = priv->hw->mii.addr;
1963         unsigned int mii_data = priv->hw->mii.data;
1964 -
1965 +       u32 v;
1966         u32 value = MII_BUSY;
1967
1968         value |= (phyaddr << priv->hw->mii.addr_shift)
1969 @@ -130,7 +113,8 @@ static int stmmac_mdio_write(struct mii_
1970                 value |= MII_WRITE;
1971
1972         /* Wait until any existing MII operation is complete */
1973 -       if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
1974 +       if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
1975 +                              100, 10000))
1976                 return -EBUSY;
1977
1978         /* Set the MII address register to write */
1979 @@ -138,7 +122,8 @@ static int stmmac_mdio_write(struct mii_
1980         writel(value, priv->ioaddr + mii_address);
1981
1982         /* Wait until any existing MII operation is complete */
1983 -       return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
1984 +       return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
1985 +                                 100, 10000);
1986  }
1987
1988  /**
1989 @@ -156,9 +141,9 @@ int stmmac_mdio_reset(struct mii_bus *bu
1990
1991  #ifdef CONFIG_OF
1992         if (priv->device->of_node) {
1993 -
1994                 if (data->reset_gpio < 0) {
1995                         struct device_node *np = priv->device->of_node;
1996 +
1997                         if (!np)
1998                                 return 0;
1999
2000 @@ -198,7 +183,7 @@ int stmmac_mdio_reset(struct mii_bus *bu
2001
2002         /* This is a workaround for problems with the STE101P PHY.
2003          * It doesn't complete its reset until at least one clock cycle
2004 -        * on MDC, so perform a dummy mdio read. To be upadted for GMAC4
2005 +        * on MDC, so perform a dummy mdio read. To be updated for GMAC4
2006          * if needed.
2007          */
2008         if (!priv->plat->has_gmac4)
2009 @@ -225,7 +210,7 @@ int stmmac_mdio_register(struct net_devi
2010                 return 0;
2011
2012         new_bus = mdiobus_alloc();
2013 -       if (new_bus == NULL)
2014 +       if (!new_bus)
2015                 return -ENOMEM;
2016
2017         if (mdio_bus_data->irqs)
2018 @@ -262,49 +247,48 @@ int stmmac_mdio_register(struct net_devi
2019         found = 0;
2020         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
2021                 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
2022 -               if (phydev) {
2023 -                       int act = 0;
2024 -                       char irq_num[4];
2025 -                       char *irq_str;
2026 -
2027 -                       /*
2028 -                        * If an IRQ was provided to be assigned after
2029 -                        * the bus probe, do it here.
2030 -                        */
2031 -                       if ((mdio_bus_data->irqs == NULL) &&
2032 -                           (mdio_bus_data->probed_phy_irq > 0)) {
2033 -                               new_bus->irq[addr] =
2034 -                                       mdio_bus_data->probed_phy_irq;
2035 -                               phydev->irq = mdio_bus_data->probed_phy_irq;
2036 -                       }
2037 -
2038 -                       /*
2039 -                        * If we're going to bind the MAC to this PHY bus,
2040 -                        * and no PHY number was provided to the MAC,
2041 -                        * use the one probed here.
2042 -                        */
2043 -                       if (priv->plat->phy_addr == -1)
2044 -                               priv->plat->phy_addr = addr;
2045 -
2046 -                       act = (priv->plat->phy_addr == addr);
2047 -                       switch (phydev->irq) {
2048 -                       case PHY_POLL:
2049 -                               irq_str = "POLL";
2050 -                               break;
2051 -                       case PHY_IGNORE_INTERRUPT:
2052 -                               irq_str = "IGNORE";
2053 -                               break;
2054 -                       default:
2055 -                               sprintf(irq_num, "%d", phydev->irq);
2056 -                               irq_str = irq_num;
2057 -                               break;
2058 -                       }
2059 -                       netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
2060 -                                   phydev->phy_id, addr,
2061 -                                   irq_str, phydev_name(phydev),
2062 -                                   act ? " active" : "");
2063 -                       found = 1;
2064 +               int act = 0;
2065 +               char irq_num[4];
2066 +               char *irq_str;
2067 +
2068 +               if (!phydev)
2069 +                       continue;
2070 +
2071 +               /*
2072 +                * If an IRQ was provided to be assigned after
2073 +                * the bus probe, do it here.
2074 +                */
2075 +               if (!mdio_bus_data->irqs &&
2076 +                   (mdio_bus_data->probed_phy_irq > 0)) {
2077 +                       new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
2078 +                       phydev->irq = mdio_bus_data->probed_phy_irq;
2079 +               }
2080 +
2081 +               /*
2082 +                * If we're going to bind the MAC to this PHY bus,
2083 +                * and no PHY number was provided to the MAC,
2084 +                * use the one probed here.
2085 +                */
2086 +               if (priv->plat->phy_addr == -1)
2087 +                       priv->plat->phy_addr = addr;
2088 +
2089 +               act = (priv->plat->phy_addr == addr);
2090 +               switch (phydev->irq) {
2091 +               case PHY_POLL:
2092 +                       irq_str = "POLL";
2093 +                       break;
2094 +               case PHY_IGNORE_INTERRUPT:
2095 +                       irq_str = "IGNORE";
2096 +                       break;
2097 +               default:
2098 +                       sprintf(irq_num, "%d", phydev->irq);
2099 +                       irq_str = irq_num;
2100 +                       break;
2101                 }
2102 +               netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
2103 +                           phydev->phy_id, addr, irq_str, phydev_name(phydev),
2104 +                           act ? " active" : "");
2105 +               found = 1;
2106         }
2107
2108         if (!found && !mdio_node) {
2109 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
2110 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
2111 @@ -12,10 +12,6 @@
2112    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
2113    more details.
2114
2115 -  You should have received a copy of the GNU General Public License along with
2116 -  this program; if not, write to the Free Software Foundation, Inc.,
2117 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2118 -
2119    The full GNU General Public License is included in this distribution in
2120    the file called "COPYING".
2121
2122 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
2123 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
2124 @@ -12,10 +12,6 @@
2125    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
2126    more details.
2127
2128 -  You should have received a copy of the GNU General Public License along with
2129 -  this program; if not, write to the Free Software Foundation, Inc.,
2130 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2131 -
2132    The full GNU General Public License is included in this distribution in
2133    the file called "COPYING".
2134
2135 @@ -121,7 +117,6 @@ static struct stmmac_axi *stmmac_axi_set
2136         axi->axi_lpi_en = of_property_read_bool(np, "snps,lpi_en");
2137         axi->axi_xit_frm = of_property_read_bool(np, "snps,xit_frm");
2138         axi->axi_kbbe = of_property_read_bool(np, "snps,axi_kbbe");
2139 -       axi->axi_axi_all = of_property_read_bool(np, "snps,axi_all");
2140         axi->axi_fb = of_property_read_bool(np, "snps,axi_fb");
2141         axi->axi_mb = of_property_read_bool(np, "snps,axi_mb");
2142         axi->axi_rb =  of_property_read_bool(np, "snps,axi_rb");
2143 @@ -181,10 +176,19 @@ static int stmmac_dt_phy(struct plat_stm
2144                 mdio = false;
2145         }
2146
2147 -       /* If snps,dwmac-mdio is passed from DT, always register the MDIO */
2148 -       for_each_child_of_node(np, plat->mdio_node) {
2149 -               if (of_device_is_compatible(plat->mdio_node, "snps,dwmac-mdio"))
2150 -                       break;
2151 +       /* exception for dwmac-dwc-qos-eth glue logic */
2152 +       if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) {
2153 +               plat->mdio_node = of_get_child_by_name(np, "mdio");
2154 +       } else {
2155 +               /**
2156 +                * If snps,dwmac-mdio is passed from DT, always register
2157 +                * the MDIO
2158 +                */
2159 +               for_each_child_of_node(np, plat->mdio_node) {
2160 +                       if (of_device_is_compatible(plat->mdio_node,
2161 +                                                   "snps,dwmac-mdio"))
2162 +                               break;
2163 +               }
2164         }
2165
2166         if (plat->mdio_node) {
2167 @@ -249,6 +253,9 @@ stmmac_probe_config_dt(struct platform_d
2168         plat->force_sf_dma_mode =
2169                 of_property_read_bool(np, "snps,force_sf_dma_mode");
2170
2171 +       plat->en_tx_lpi_clockgating =
2172 +               of_property_read_bool(np, "snps,en-tx-lpi-clockgating");
2173 +
2174         /* Set the maxmtu to a default of JUMBO_LEN in case the
2175          * parameter is not present in the device tree.
2176          */
2177 @@ -333,7 +340,54 @@ stmmac_probe_config_dt(struct platform_d
2178
2179         plat->axi = stmmac_axi_setup(pdev);
2180
2181 +       /* clock setup */
2182 +       plat->stmmac_clk = devm_clk_get(&pdev->dev,
2183 +                                       STMMAC_RESOURCE_NAME);
2184 +       if (IS_ERR(plat->stmmac_clk)) {
2185 +               dev_warn(&pdev->dev, "Cannot get CSR clock\n");
2186 +               plat->stmmac_clk = NULL;
2187 +       }
2188 +       clk_prepare_enable(plat->stmmac_clk);
2189 +
2190 +       plat->pclk = devm_clk_get(&pdev->dev, "pclk");
2191 +       if (IS_ERR(plat->pclk)) {
2192 +               if (PTR_ERR(plat->pclk) == -EPROBE_DEFER)
2193 +                       goto error_pclk_get;
2194 +
2195 +               plat->pclk = NULL;
2196 +       }
2197 +       clk_prepare_enable(plat->pclk);
2198 +
2199 +       /* Fall-back to main clock in case of no PTP ref is passed */
2200 +       plat->clk_ptp_ref = devm_clk_get(&pdev->dev, "clk_ptp_ref");
2201 +       if (IS_ERR(plat->clk_ptp_ref)) {
2202 +               plat->clk_ptp_rate = clk_get_rate(plat->stmmac_clk);
2203 +               plat->clk_ptp_ref = NULL;
2204 +               dev_warn(&pdev->dev, "PTP uses main clock\n");
2205 +       } else {
2206 +               clk_prepare_enable(plat->clk_ptp_ref);
2207 +               plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref);
2208 +               dev_dbg(&pdev->dev, "PTP rate %d\n", plat->clk_ptp_rate);
2209 +       }
2210 +
2211 +       plat->stmmac_rst = devm_reset_control_get(&pdev->dev,
2212 +                                                 STMMAC_RESOURCE_NAME);
2213 +       if (IS_ERR(plat->stmmac_rst)) {
2214 +               if (PTR_ERR(plat->stmmac_rst) == -EPROBE_DEFER)
2215 +                       goto error_hw_init;
2216 +
2217 +               dev_info(&pdev->dev, "no reset control found\n");
2218 +               plat->stmmac_rst = NULL;
2219 +       }
2220 +
2221         return plat;
2222 +
2223 +error_hw_init:
2224 +       clk_disable_unprepare(plat->pclk);
2225 +error_pclk_get:
2226 +       clk_disable_unprepare(plat->stmmac_clk);
2227 +
2228 +       return ERR_PTR(-EPROBE_DEFER);
2229  }
2230
2231  /**
2232 @@ -357,7 +411,7 @@ void stmmac_remove_config_dt(struct plat
2233  struct plat_stmmacenet_data *
2234  stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)
2235  {
2236 -       return ERR_PTR(-ENOSYS);
2237 +       return ERR_PTR(-EINVAL);
2238  }
2239
2240  void stmmac_remove_config_dt(struct platform_device *pdev,
2241 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
2242 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
2243 @@ -12,10 +12,6 @@
2244    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
2245    more details.
2246
2247 -  You should have received a copy of the GNU General Public License along with
2248 -  this program; if not, write to the Free Software Foundation, Inc.,
2249 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2250 -
2251    The full GNU General Public License is included in this distribution in
2252    the file called "COPYING".
2253
2254 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
2255 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
2256 @@ -12,10 +12,6 @@
2257    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
2258    more details.
2259
2260 -  You should have received a copy of the GNU General Public License along with
2261 -  this program; if not, write to the Free Software Foundation, Inc.,
2262 -  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2263 -
2264    The full GNU General Public License is included in this distribution in
2265    the file called "COPYING".
2266
2267 --- a/include/linux/stmmac.h
2268 +++ b/include/linux/stmmac.h
2269 @@ -103,7 +103,6 @@ struct stmmac_axi {
2270         u32 axi_wr_osr_lmt;
2271         u32 axi_rd_osr_lmt;
2272         bool axi_kbbe;
2273 -       bool axi_axi_all;
2274         u32 axi_blen[AXI_BLEN];
2275         bool axi_fb;
2276         bool axi_mb;
2277 @@ -135,13 +134,18 @@ struct plat_stmmacenet_data {
2278         int tx_fifo_size;
2279         int rx_fifo_size;
2280         void (*fix_mac_speed)(void *priv, unsigned int speed);
2281 -       void (*bus_setup)(void __iomem *ioaddr);
2282         int (*init)(struct platform_device *pdev, void *priv);
2283         void (*exit)(struct platform_device *pdev, void *priv);
2284         void *bsp_priv;
2285 +       struct clk *stmmac_clk;
2286 +       struct clk *pclk;
2287 +       struct clk *clk_ptp_ref;
2288 +       unsigned int clk_ptp_rate;
2289 +       struct reset_control *stmmac_rst;
2290         struct stmmac_axi *axi;
2291         int has_gmac4;
2292         bool tso_en;
2293         int mac_port_sel_speed;
2294 +       bool en_tx_lpi_clockgating;
2295  };
2296  #endif