target/linux/sunxi/patches-4.9/0007-clk-sunxi-ng-Add-A64-clocks.patch

   1 From c6a0637460c29799f1e63a6a4a65bda22caf4a54 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 6 Jul 2016 08:31:34 +0200
   4 Subject: clk: sunxi-ng: Add A64 clocks
   5
   6 Add the A64 CCU clocks set.
   7
   8 Acked-by: Rob Herring <robh@kernel.org>
   9 Acked-by: Chen-Yu Tsai <wens@csie.org>
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  .../devicetree/bindings/clock/sunxi-ccu.txt        |   1 +
  13  drivers/clk/sunxi-ng/Kconfig                       |  11 +
  14  drivers/clk/sunxi-ng/Makefile                      |   1 +
  15  drivers/clk/sunxi-ng/ccu-sun50i-a64.c              | 915 +++++++++++++++++++++
  16  drivers/clk/sunxi-ng/ccu-sun50i-a64.h              |  72 ++
  17  include/dt-bindings/clock/sun50i-a64-ccu.h         | 134 +++
  18  include/dt-bindings/reset/sun50i-a64-ccu.h         |  98 +++
  19  7 files changed, 1232 insertions(+)
  20  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
  21  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
  22  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
  23  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
  24
  25 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
  26 +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
  27 @@ -7,6 +7,7 @@ Required properties :
  28                 - "allwinner,sun8i-a23-ccu"
  29                 - "allwinner,sun8i-a33-ccu"
  30                 - "allwinner,sun8i-h3-ccu"
  31 +               - "allwinner,sun50i-a64-ccu"
  32
  33  - reg: Must contain the registers base address and length
  34  - clocks: phandle to the oscillators feeding the CCU. Two are needed:
  35 --- a/drivers/clk/sunxi-ng/Kconfig
  36 +++ b/drivers/clk/sunxi-ng/Kconfig
  37 @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
  38
  39  # SoC Drivers
  40
  41 +config SUN50I_A64_CCU
  42 +       bool "Support for the Allwinner A64 CCU"
  43 +       select SUNXI_CCU_DIV
  44 +       select SUNXI_CCU_NK
  45 +       select SUNXI_CCU_NKM
  46 +       select SUNXI_CCU_NKMP
  47 +       select SUNXI_CCU_NM
  48 +       select SUNXI_CCU_MP
  49 +       select SUNXI_CCU_PHASE
  50 +       default ARM64 && ARCH_SUNXI
  51 +
  52  config SUN6I_A31_CCU
  53         bool "Support for the Allwinner A31/A31s CCU"
  54         select SUNXI_CCU_DIV
  55 --- a/drivers/clk/sunxi-ng/Makefile
  56 +++ b/drivers/clk/sunxi-ng/Makefile
  57 @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM)    += ccu_nm.o
  58  obj-$(CONFIG_SUNXI_CCU_MP)     += ccu_mp.o
  59
  60  # SoC support
  61 +obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
  62  obj-$(CONFIG_SUN6I_A31_CCU)    += ccu-sun6i-a31.o
  63  obj-$(CONFIG_SUN8I_A23_CCU)    += ccu-sun8i-a23.o
  64  obj-$(CONFIG_SUN8I_A33_CCU)    += ccu-sun8i-a33.o
  65 --- /dev/null
  66 +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
  67 @@ -0,0 +1,915 @@
  68 +/*
  69 + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
  70 + *
  71 + * This software is licensed under the terms of the GNU General Public
  72 + * License version 2, as published by the Free Software Foundation, and
  73 + * may be copied, distributed, and modified under those terms.
  74 + *
  75 + * This program is distributed in the hope that it will be useful,
  76 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  77 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  78 + * GNU General Public License for more details.
  79 + */
  80 +
  81 +#include <linux/clk-provider.h>
  82 +#include <linux/of_address.h>
  83 +#include <linux/platform_device.h>
  84 +
  85 +#include "ccu_common.h"
  86 +#include "ccu_reset.h"
  87 +
  88 +#include "ccu_div.h"
  89 +#include "ccu_gate.h"
  90 +#include "ccu_mp.h"
  91 +#include "ccu_mult.h"
  92 +#include "ccu_nk.h"
  93 +#include "ccu_nkm.h"
  94 +#include "ccu_nkmp.h"
  95 +#include "ccu_nm.h"
  96 +#include "ccu_phase.h"
  97 +
  98 +#include "ccu-sun50i-a64.h"
  99 +
 100 +static struct ccu_nkmp pll_cpux_clk = {
 101 +       .enable         = BIT(31),
 102 +       .lock           = BIT(28),
 103 +       .n              = _SUNXI_CCU_MULT(8, 5),
 104 +       .k              = _SUNXI_CCU_MULT(4, 2),
 105 +       .m              = _SUNXI_CCU_DIV(0, 2),
 106 +       .p              = _SUNXI_CCU_DIV_MAX(16, 2, 4),
 107 +       .common         = {
 108 +               .reg            = 0x000,
 109 +               .hw.init        = CLK_HW_INIT("pll-cpux",
 110 +                                             "osc24M",
 111 +                                             &ccu_nkmp_ops,
 112 +                                             CLK_SET_RATE_UNGATE),
 113 +       },
 114 +};
 115 +
 116 +/*
 117 + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
 118 + * the base (2x, 4x and 8x), and one variable divider (the one true
 119 + * pll audio).
 120 + *
 121 + * We don't have any need for the variable divider for now, so we just
 122 + * hardcode it to match with the clock names
 123 + */
 124 +#define SUN50I_A64_PLL_AUDIO_REG       0x008
 125 +
 126 +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 127 +                                  "osc24M", 0x008,
 128 +                                  8, 7,        /* N */
 129 +                                  0, 5,        /* M */
 130 +                                  BIT(31),     /* gate */
 131 +                                  BIT(28),     /* lock */
 132 +                                  CLK_SET_RATE_UNGATE);
 133 +
 134 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
 135 +                                       "osc24M", 0x010,
 136 +                                       8, 7,           /* N */
 137 +                                       0, 4,           /* M */
 138 +                                       BIT(24),        /* frac enable */
 139 +                                       BIT(25),        /* frac select */
 140 +                                       270000000,      /* frac rate 0 */
 141 +                                       297000000,      /* frac rate 1 */
 142 +                                       BIT(31),        /* gate */
 143 +                                       BIT(28),        /* lock */
 144 +                                       CLK_SET_RATE_UNGATE);
 145 +
 146 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
 147 +                                       "osc24M", 0x018,
 148 +                                       8, 7,           /* N */
 149 +                                       0, 4,           /* M */
 150 +                                       BIT(24),        /* frac enable */
 151 +                                       BIT(25),        /* frac select */
 152 +                                       270000000,      /* frac rate 0 */
 153 +                                       297000000,      /* frac rate 1 */
 154 +                                       BIT(31),        /* gate */
 155 +                                       BIT(28),        /* lock */
 156 +                                       CLK_SET_RATE_UNGATE);
 157 +
 158 +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
 159 +                                   "osc24M", 0x020,
 160 +                                   8, 5,       /* N */
 161 +                                   4, 2,       /* K */
 162 +                                   0, 2,       /* M */
 163 +                                   BIT(31),    /* gate */
 164 +                                   BIT(28),    /* lock */
 165 +                                   CLK_SET_RATE_UNGATE);
 166 +
 167 +static struct ccu_nk pll_periph0_clk = {
 168 +       .enable         = BIT(31),
 169 +       .lock           = BIT(28),
 170 +       .n              = _SUNXI_CCU_MULT(8, 5),
 171 +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
 172 +       .fixed_post_div = 2,
 173 +       .common         = {
 174 +               .reg            = 0x028,
 175 +               .features       = CCU_FEATURE_FIXED_POSTDIV,
 176 +               .hw.init        = CLK_HW_INIT("pll-periph0", "osc24M",
 177 +                                             &ccu_nk_ops, CLK_SET_RATE_UNGATE),
 178 +       },
 179 +};
 180 +
 181 +static struct ccu_nk pll_periph1_clk = {
 182 +       .enable         = BIT(31),
 183 +       .lock           = BIT(28),
 184 +       .n              = _SUNXI_CCU_MULT(8, 5),
 185 +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
 186 +       .fixed_post_div = 2,
 187 +       .common         = {
 188 +               .reg            = 0x02c,
 189 +               .features       = CCU_FEATURE_FIXED_POSTDIV,
 190 +               .hw.init        = CLK_HW_INIT("pll-periph1", "osc24M",
 191 +                                             &ccu_nk_ops, CLK_SET_RATE_UNGATE),
 192 +       },
 193 +};
 194 +
 195 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
 196 +                                       "osc24M", 0x030,
 197 +                                       8, 7,           /* N */
 198 +                                       0, 4,           /* M */
 199 +                                       BIT(24),        /* frac enable */
 200 +                                       BIT(25),        /* frac select */
 201 +                                       270000000,      /* frac rate 0 */
 202 +                                       297000000,      /* frac rate 1 */
 203 +                                       BIT(31),        /* gate */
 204 +                                       BIT(28),        /* lock */
 205 +                                       CLK_SET_RATE_UNGATE);
 206 +
 207 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 208 +                                       "osc24M", 0x038,
 209 +                                       8, 7,           /* N */
 210 +                                       0, 4,           /* M */
 211 +                                       BIT(24),        /* frac enable */
 212 +                                       BIT(25),        /* frac select */
 213 +                                       270000000,      /* frac rate 0 */
 214 +                                       297000000,      /* frac rate 1 */
 215 +                                       BIT(31),        /* gate */
 216 +                                       BIT(28),        /* lock */
 217 +                                       CLK_SET_RATE_UNGATE);
 218 +
 219 +/*
 220 + * The output function can be changed to something more complex that
 221 + * we do not handle yet.
 222 + *
 223 + * Hardcode the mode so that we don't fall in that case.
 224 + */
 225 +#define SUN50I_A64_PLL_MIPI_REG                0x040
 226 +
 227 +struct ccu_nkm pll_mipi_clk = {
 228 +       .enable         = BIT(31),
 229 +       .lock           = BIT(28),
 230 +       .n              = _SUNXI_CCU_MULT(8, 4),
 231 +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
 232 +       .m              = _SUNXI_CCU_DIV(0, 4),
 233 +       .common         = {
 234 +               .reg            = 0x040,
 235 +               .hw.init        = CLK_HW_INIT("pll-mipi", "pll-video0",
 236 +                                             &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
 237 +       },
 238 +};
 239 +
 240 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
 241 +                                       "osc24M", 0x044,
 242 +                                       8, 7,           /* N */
 243 +                                       0, 4,           /* M */
 244 +                                       BIT(24),        /* frac enable */
 245 +                                       BIT(25),        /* frac select */
 246 +                                       270000000,      /* frac rate 0 */
 247 +                                       297000000,      /* frac rate 1 */
 248 +                                       BIT(31),        /* gate */
 249 +                                       BIT(28),        /* lock */
 250 +                                       CLK_SET_RATE_UNGATE);
 251 +
 252 +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 253 +                                       "osc24M", 0x048,
 254 +                                       8, 7,           /* N */
 255 +                                       0, 4,           /* M */
 256 +                                       BIT(24),        /* frac enable */
 257 +                                       BIT(25),        /* frac select */
 258 +                                       270000000,      /* frac rate 0 */
 259 +                                       297000000,      /* frac rate 1 */
 260 +                                       BIT(31),        /* gate */
 261 +                                       BIT(28),        /* lock */
 262 +                                       CLK_SET_RATE_UNGATE);
 263 +
 264 +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
 265 +                                  "osc24M", 0x04c,
 266 +                                  8, 7,        /* N */
 267 +                                  0, 2,        /* M */
 268 +                                  BIT(31),     /* gate */
 269 +                                  BIT(28),     /* lock */
 270 +                                  CLK_SET_RATE_UNGATE);
 271 +
 272 +static const char * const cpux_parents[] = { "osc32k", "osc24M",
 273 +                                            "pll-cpux" , "pll-cpux" };
 274 +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
 275 +                    0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 276 +
 277 +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 278 +
 279 +static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 280 +                                            "axi" , "pll-periph0" };
 281 +static struct ccu_div ahb1_clk = {
 282 +       .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 283 +
 284 +       .mux            = {
 285 +               .shift  = 12,
 286 +               .width  = 2,
 287 +
 288 +               .variable_prediv        = {
 289 +                       .index  = 3,
 290 +                       .shift  = 6,
 291 +                       .width  = 2,
 292 +               },
 293 +       },
 294 +
 295 +       .common         = {
 296 +               .reg            = 0x054,
 297 +               .features       = CCU_FEATURE_VARIABLE_PREDIV,
 298 +               .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 299 +                                                     ahb1_parents,
 300 +                                                     &ccu_div_ops,
 301 +                                                     0),
 302 +       },
 303 +};
 304 +
 305 +static struct clk_div_table apb1_div_table[] = {
 306 +       { .val = 0, .div = 2 },
 307 +       { .val = 1, .div = 2 },
 308 +       { .val = 2, .div = 4 },
 309 +       { .val = 3, .div = 8 },
 310 +       { /* Sentinel */ },
 311 +};
 312 +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 313 +                          0x054, 8, 2, apb1_div_table, 0);
 314 +
 315 +static const char * const apb2_parents[] = { "osc32k", "osc24M",
 316 +                                            "pll-periph0-2x" ,
 317 +                                            "pll-periph0-2x" };
 318 +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 319 +                            0, 5,      /* M */
 320 +                            16, 2,     /* P */
 321 +                            24, 2,     /* mux */
 322 +                            0);
 323 +
 324 +static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
 325 +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
 326 +       { .index = 1, .div = 2 },
 327 +};
 328 +static struct ccu_mux ahb2_clk = {
 329 +       .mux            = {
 330 +               .shift  = 0,
 331 +               .width  = 1,
 332 +               .fixed_predivs  = ahb2_fixed_predivs,
 333 +               .n_predivs      = ARRAY_SIZE(ahb2_fixed_predivs),
 334 +       },
 335 +
 336 +       .common         = {
 337 +               .reg            = 0x05c,
 338 +               .features       = CCU_FEATURE_FIXED_PREDIV,
 339 +               .hw.init        = CLK_HW_INIT_PARENTS("ahb2",
 340 +                                                     ahb2_parents,
 341 +                                                     &ccu_mux_ops,
 342 +                                                     0),
 343 +       },
 344 +};
 345 +
 346 +static SUNXI_CCU_GATE(bus_mipi_dsi_clk,        "bus-mipi-dsi", "ahb1",
 347 +                     0x060, BIT(1), 0);
 348 +static SUNXI_CCU_GATE(bus_ce_clk,      "bus-ce",       "ahb1",
 349 +                     0x060, BIT(5), 0);
 350 +static SUNXI_CCU_GATE(bus_dma_clk,     "bus-dma",      "ahb1",
 351 +                     0x060, BIT(6), 0);
 352 +static SUNXI_CCU_GATE(bus_mmc0_clk,    "bus-mmc0",     "ahb1",
 353 +                     0x060, BIT(8), 0);
 354 +static SUNXI_CCU_GATE(bus_mmc1_clk,    "bus-mmc1",     "ahb1",
 355 +                     0x060, BIT(9), 0);
 356 +static SUNXI_CCU_GATE(bus_mmc2_clk,    "bus-mmc2",     "ahb1",
 357 +                     0x060, BIT(10), 0);
 358 +static SUNXI_CCU_GATE(bus_nand_clk,    "bus-nand",     "ahb1",
 359 +                     0x060, BIT(13), 0);
 360 +static SUNXI_CCU_GATE(bus_dram_clk,    "bus-dram",     "ahb1",
 361 +                     0x060, BIT(14), 0);
 362 +static SUNXI_CCU_GATE(bus_emac_clk,    "bus-emac",     "ahb2",
 363 +                     0x060, BIT(17), 0);
 364 +static SUNXI_CCU_GATE(bus_ts_clk,      "bus-ts",       "ahb1",
 365 +                     0x060, BIT(18), 0);
 366 +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer",  "ahb1",
 367 +                     0x060, BIT(19), 0);
 368 +static SUNXI_CCU_GATE(bus_spi0_clk,    "bus-spi0",     "ahb1",
 369 +                     0x060, BIT(20), 0);
 370 +static SUNXI_CCU_GATE(bus_spi1_clk,    "bus-spi1",     "ahb1",
 371 +                     0x060, BIT(21), 0);
 372 +static SUNXI_CCU_GATE(bus_otg_clk,     "bus-otg",      "ahb1",
 373 +                     0x060, BIT(23), 0);
 374 +static SUNXI_CCU_GATE(bus_ehci0_clk,   "bus-ehci0",    "ahb1",
 375 +                     0x060, BIT(24), 0);
 376 +static SUNXI_CCU_GATE(bus_ehci1_clk,   "bus-ehci1",    "ahb2",
 377 +                     0x060, BIT(25), 0);
 378 +static SUNXI_CCU_GATE(bus_ohci0_clk,   "bus-ohci0",    "ahb1",
 379 +                     0x060, BIT(28), 0);
 380 +static SUNXI_CCU_GATE(bus_ohci1_clk,   "bus-ohci1",    "ahb2",
 381 +                     0x060, BIT(29), 0);
 382 +
 383 +static SUNXI_CCU_GATE(bus_ve_clk,      "bus-ve",       "ahb1",
 384 +                     0x064, BIT(0), 0);
 385 +static SUNXI_CCU_GATE(bus_tcon0_clk,   "bus-tcon0",    "ahb1",
 386 +                     0x064, BIT(3), 0);
 387 +static SUNXI_CCU_GATE(bus_tcon1_clk,   "bus-tcon1",    "ahb1",
 388 +                     0x064, BIT(4), 0);
 389 +static SUNXI_CCU_GATE(bus_deinterlace_clk,     "bus-deinterlace",      "ahb1",
 390 +                     0x064, BIT(5), 0);
 391 +static SUNXI_CCU_GATE(bus_csi_clk,     "bus-csi",      "ahb1",
 392 +                     0x064, BIT(8), 0);
 393 +static SUNXI_CCU_GATE(bus_hdmi_clk,    "bus-hdmi",     "ahb1",
 394 +                     0x064, BIT(11), 0);
 395 +static SUNXI_CCU_GATE(bus_de_clk,      "bus-de",       "ahb1",
 396 +                     0x064, BIT(12), 0);
 397 +static SUNXI_CCU_GATE(bus_gpu_clk,     "bus-gpu",      "ahb1",
 398 +                     0x064, BIT(20), 0);
 399 +static SUNXI_CCU_GATE(bus_msgbox_clk,  "bus-msgbox",   "ahb1",
 400 +                     0x064, BIT(21), 0);
 401 +static SUNXI_CCU_GATE(bus_spinlock_clk,        "bus-spinlock", "ahb1",
 402 +                     0x064, BIT(22), 0);
 403 +
 404 +static SUNXI_CCU_GATE(bus_codec_clk,   "bus-codec",    "apb1",
 405 +                     0x068, BIT(0), 0);
 406 +static SUNXI_CCU_GATE(bus_spdif_clk,   "bus-spdif",    "apb1",
 407 +                     0x068, BIT(1), 0);
 408 +static SUNXI_CCU_GATE(bus_pio_clk,     "bus-pio",      "apb1",
 409 +                     0x068, BIT(5), 0);
 410 +static SUNXI_CCU_GATE(bus_ths_clk,     "bus-ths",      "apb1",
 411 +                     0x068, BIT(8), 0);
 412 +static SUNXI_CCU_GATE(bus_i2s0_clk,    "bus-i2s0",     "apb1",
 413 +                     0x068, BIT(12), 0);
 414 +static SUNXI_CCU_GATE(bus_i2s1_clk,    "bus-i2s1",     "apb1",
 415 +                     0x068, BIT(13), 0);
 416 +static SUNXI_CCU_GATE(bus_i2s2_clk,    "bus-i2s2",     "apb1",
 417 +                     0x068, BIT(14), 0);
 418 +
 419 +static SUNXI_CCU_GATE(bus_i2c0_clk,    "bus-i2c0",     "apb2",
 420 +                     0x06c, BIT(0), 0);
 421 +static SUNXI_CCU_GATE(bus_i2c1_clk,    "bus-i2c1",     "apb2",
 422 +                     0x06c, BIT(1), 0);
 423 +static SUNXI_CCU_GATE(bus_i2c2_clk,    "bus-i2c2",     "apb2",
 424 +                     0x06c, BIT(2), 0);
 425 +static SUNXI_CCU_GATE(bus_scr_clk,     "bus-scr",      "apb2",
 426 +                     0x06c, BIT(5), 0);
 427 +static SUNXI_CCU_GATE(bus_uart0_clk,   "bus-uart0",    "apb2",
 428 +                     0x06c, BIT(16), 0);
 429 +static SUNXI_CCU_GATE(bus_uart1_clk,   "bus-uart1",    "apb2",
 430 +                     0x06c, BIT(17), 0);
 431 +static SUNXI_CCU_GATE(bus_uart2_clk,   "bus-uart2",    "apb2",
 432 +                     0x06c, BIT(18), 0);
 433 +static SUNXI_CCU_GATE(bus_uart3_clk,   "bus-uart3",    "apb2",
 434 +                     0x06c, BIT(19), 0);
 435 +static SUNXI_CCU_GATE(bus_uart4_clk,   "bus-uart4",    "apb2",
 436 +                     0x06c, BIT(20), 0);
 437 +
 438 +static SUNXI_CCU_GATE(bus_dbg_clk,     "bus-dbg",      "ahb1",
 439 +                     0x070, BIT(7), 0);
 440 +
 441 +static struct clk_div_table ths_div_table[] = {
 442 +       { .val = 0, .div = 1 },
 443 +       { .val = 1, .div = 2 },
 444 +       { .val = 2, .div = 4 },
 445 +       { .val = 3, .div = 6 },
 446 +};
 447 +static const char * const ths_parents[] = { "osc24M" };
 448 +static struct ccu_div ths_clk = {
 449 +       .enable = BIT(31),
 450 +       .div    = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
 451 +       .mux    = _SUNXI_CCU_MUX(24, 2),
 452 +       .common = {
 453 +               .reg            = 0x074,
 454 +               .hw.init        = CLK_HW_INIT_PARENTS("ths",
 455 +                                                     ths_parents,
 456 +                                                     &ccu_div_ops,
 457 +                                                     0),
 458 +       },
 459 +};
 460 +
 461 +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
 462 +                                                    "pll-periph1" };
 463 +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 464 +                                 0, 4,         /* M */
 465 +                                 16, 2,        /* P */
 466 +                                 24, 2,        /* mux */
 467 +                                 BIT(31),      /* gate */
 468 +                                 0);
 469 +
 470 +static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
 471 +                                                   "pll-periph1-2x" };
 472 +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088,
 473 +                                 0, 4,         /* M */
 474 +                                 16, 2,        /* P */
 475 +                                 24, 2,        /* mux */
 476 +                                 BIT(31),      /* gate */
 477 +                                 0);
 478 +
 479 +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c,
 480 +                                 0, 4,         /* M */
 481 +                                 16, 2,        /* P */
 482 +                                 24, 2,        /* mux */
 483 +                                 BIT(31),      /* gate */
 484 +                                 0);
 485 +
 486 +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090,
 487 +                                 0, 4,         /* M */
 488 +                                 16, 2,        /* P */
 489 +                                 24, 2,        /* mux */
 490 +                                 BIT(31),      /* gate */
 491 +                                 0);
 492 +
 493 +static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
 494 +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
 495 +                                 0, 4,         /* M */
 496 +                                 16, 2,        /* P */
 497 +                                 24, 4,        /* mux */
 498 +                                 BIT(31),      /* gate */
 499 +                                 0);
 500 +
 501 +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
 502 +                                 0, 4,         /* M */
 503 +                                 16, 2,        /* P */
 504 +                                 24, 2,        /* mux */
 505 +                                 BIT(31),      /* gate */
 506 +                                 0);
 507 +
 508 +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 509 +                                 0, 4,         /* M */
 510 +                                 16, 2,        /* P */
 511 +                                 24, 2,        /* mux */
 512 +                                 BIT(31),      /* gate */
 513 +                                 0);
 514 +
 515 +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 516 +                                 0, 4,         /* M */
 517 +                                 16, 2,        /* P */
 518 +                                 24, 2,        /* mux */
 519 +                                 BIT(31),      /* gate */
 520 +                                 0);
 521 +
 522 +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 523 +                                           "pll-audio-2x", "pll-audio" };
 524 +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
 525 +                              0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 526 +
 527 +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
 528 +                              0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 529 +
 530 +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
 531 +                              0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 532 +
 533 +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
 534 +                            0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
 535 +
 536 +static SUNXI_CCU_GATE(usb_phy0_clk,    "usb-phy0",     "osc24M",
 537 +                     0x0cc, BIT(8), 0);
 538 +static SUNXI_CCU_GATE(usb_phy1_clk,    "usb-phy1",     "osc24M",
 539 +                     0x0cc, BIT(9), 0);
 540 +static SUNXI_CCU_GATE(usb_hsic_clk,    "usb-hsic",     "pll-hsic",
 541 +                     0x0cc, BIT(10), 0);
 542 +static SUNXI_CCU_GATE(usb_hsic_12m_clk,        "usb-hsic-12M", "osc12M",
 543 +                     0x0cc, BIT(11), 0);
 544 +static SUNXI_CCU_GATE(usb_ohci0_clk,   "usb-ohci0",    "osc12M",
 545 +                     0x0cc, BIT(16), 0);
 546 +static SUNXI_CCU_GATE(usb_ohci1_clk,   "usb-ohci1",    "usb-ohci0",
 547 +                     0x0cc, BIT(17), 0);
 548 +
 549 +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
 550 +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
 551 +                           0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
 552 +
 553 +static SUNXI_CCU_GATE(dram_ve_clk,     "dram-ve",      "dram",
 554 +                     0x100, BIT(0), 0);
 555 +static SUNXI_CCU_GATE(dram_csi_clk,    "dram-csi",     "dram",
 556 +                     0x100, BIT(1), 0);
 557 +static SUNXI_CCU_GATE(dram_deinterlace_clk,    "dram-deinterlace",     "dram",
 558 +                     0x100, BIT(2), 0);
 559 +static SUNXI_CCU_GATE(dram_ts_clk,     "dram-ts",      "dram",
 560 +                     0x100, BIT(3), 0);
 561 +
 562 +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 563 +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
 564 +                                0x104, 0, 4, 24, 3, BIT(31), 0);
 565 +
 566 +static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
 567 +static const u8 tcon0_table[] = { 0, 2, };
 568 +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
 569 +                                    tcon0_table, 0x118, 24, 3, BIT(31),
 570 +                                    CLK_SET_RATE_PARENT);
 571 +
 572 +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
 573 +static const u8 tcon1_table[] = { 0, 2, };
 574 +struct ccu_div tcon1_clk = {
 575 +       .enable         = BIT(31),
 576 +       .div            = _SUNXI_CCU_DIV(0, 4),
 577 +       .mux            = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
 578 +       .common         = {
 579 +               .reg            = 0x11c,
 580 +               .hw.init        = CLK_HW_INIT_PARENTS("tcon1",
 581 +                                                     tcon1_parents,
 582 +                                                     &ccu_div_ops,
 583 +                                                     CLK_SET_RATE_PARENT),
 584 +       },
 585 +};
 586 +
 587 +static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
 588 +static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
 589 +                                0x124, 0, 4, 24, 3, BIT(31), 0);
 590 +
 591 +static SUNXI_CCU_GATE(csi_misc_clk,    "csi-misc",     "osc24M",
 592 +                     0x130, BIT(31), 0);
 593 +
 594 +static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
 595 +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
 596 +                                0x134, 16, 4, 24, 3, BIT(31), 0);
 597 +
 598 +static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
 599 +static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
 600 +                                0x134, 0, 5, 8, 3, BIT(15), 0);
 601 +
 602 +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 603 +                            0x13c, 16, 3, BIT(31), 0);
 604 +
 605 +static SUNXI_CCU_GATE(ac_dig_clk,      "ac-dig",       "pll-audio",
 606 +                     0x140, BIT(31), CLK_SET_RATE_PARENT);
 607 +
 608 +static SUNXI_CCU_GATE(ac_dig_4x_clk,   "ac-dig-4x",    "pll-audio-4x",
 609 +                     0x140, BIT(30), CLK_SET_RATE_PARENT);
 610 +
 611 +static SUNXI_CCU_GATE(avs_clk,         "avs",          "osc24M",
 612 +                     0x144, BIT(31), 0);
 613 +
 614 +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
 615 +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
 616 +                                0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 617 +
 618 +static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
 619 +                     0x154, BIT(31), 0);
 620 +
 621 +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
 622 +                                                "pll-ddr0", "pll-ddr1" };
 623 +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 624 +                                0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 625 +
 626 +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
 627 +static const u8 dsi_dphy_table[] = { 0, 2, };
 628 +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
 629 +                                      dsi_dphy_parents, dsi_dphy_table,
 630 +                                      0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);
 631 +
 632 +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 633 +                            0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 634 +
 635 +/* Fixed Factor clocks */
 636 +static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);
 637 +
 638 +/* We hardcode the divider to 4 for now */
 639 +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 640 +                       "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
 641 +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 642 +                       "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 643 +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 644 +                       "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 645 +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 646 +                       "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 647 +static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
 648 +                       "pll-periph0", 1, 2, 0);
 649 +static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
 650 +                       "pll-periph1", 1, 2, 0);
 651 +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
 652 +                       "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
 653 +
 654 +static struct ccu_common *sun50i_a64_ccu_clks[] = {
 655 +       &pll_cpux_clk.common,
 656 +       &pll_audio_base_clk.common,
 657 +       &pll_video0_clk.common,
 658 +       &pll_ve_clk.common,
 659 +       &pll_ddr0_clk.common,
 660 +       &pll_periph0_clk.common,
 661 +       &pll_periph1_clk.common,
 662 +       &pll_video1_clk.common,
 663 +       &pll_gpu_clk.common,
 664 +       &pll_mipi_clk.common,
 665 +       &pll_hsic_clk.common,
 666 +       &pll_de_clk.common,
 667 +       &pll_ddr1_clk.common,
 668 +       &cpux_clk.common,
 669 +       &axi_clk.common,
 670 +       &ahb1_clk.common,
 671 +       &apb1_clk.common,
 672 +       &apb2_clk.common,
 673 +       &ahb2_clk.common,
 674 +       &bus_mipi_dsi_clk.common,
 675 +       &bus_ce_clk.common,
 676 +       &bus_dma_clk.common,
 677 +       &bus_mmc0_clk.common,
 678 +       &bus_mmc1_clk.common,
 679 +       &bus_mmc2_clk.common,
 680 +       &bus_nand_clk.common,
 681 +       &bus_dram_clk.common,
 682 +       &bus_emac_clk.common,
 683 +       &bus_ts_clk.common,
 684 +       &bus_hstimer_clk.common,
 685 +       &bus_spi0_clk.common,
 686 +       &bus_spi1_clk.common,
 687 +       &bus_otg_clk.common,
 688 +       &bus_ehci0_clk.common,
 689 +       &bus_ehci1_clk.common,
 690 +       &bus_ohci0_clk.common,
 691 +       &bus_ohci1_clk.common,
 692 +       &bus_ve_clk.common,
 693 +       &bus_tcon0_clk.common,
 694 +       &bus_tcon1_clk.common,
 695 +       &bus_deinterlace_clk.common,
 696 +       &bus_csi_clk.common,
 697 +       &bus_hdmi_clk.common,
 698 +       &bus_de_clk.common,
 699 +       &bus_gpu_clk.common,
 700 +       &bus_msgbox_clk.common,
 701 +       &bus_spinlock_clk.common,
 702 +       &bus_codec_clk.common,
 703 +       &bus_spdif_clk.common,
 704 +       &bus_pio_clk.common,
 705 +       &bus_ths_clk.common,
 706 +       &bus_i2s0_clk.common,
 707 +       &bus_i2s1_clk.common,
 708 +       &bus_i2s2_clk.common,
 709 +       &bus_i2c0_clk.common,
 710 +       &bus_i2c1_clk.common,
 711 +       &bus_i2c2_clk.common,
 712 +       &bus_scr_clk.common,
 713 +       &bus_uart0_clk.common,
 714 +       &bus_uart1_clk.common,
 715 +       &bus_uart2_clk.common,
 716 +       &bus_uart3_clk.common,
 717 +       &bus_uart4_clk.common,
 718 +       &bus_dbg_clk.common,
 719 +       &ths_clk.common,
 720 +       &nand_clk.common,
 721 +       &mmc0_clk.common,
 722 +       &mmc1_clk.common,
 723 +       &mmc2_clk.common,
 724 +       &ts_clk.common,
 725 +       &ce_clk.common,
 726 +       &spi0_clk.common,
 727 +       &spi1_clk.common,
 728 +       &i2s0_clk.common,
 729 +       &i2s1_clk.common,
 730 +       &i2s2_clk.common,
 731 +       &spdif_clk.common,
 732 +       &usb_phy0_clk.common,
 733 +       &usb_phy1_clk.common,
 734 +       &usb_hsic_clk.common,
 735 +       &usb_hsic_12m_clk.common,
 736 +       &usb_ohci0_clk.common,
 737 +       &usb_ohci1_clk.common,
 738 +       &dram_clk.common,
 739 +       &dram_ve_clk.common,
 740 +       &dram_csi_clk.common,
 741 +       &dram_deinterlace_clk.common,
 742 +       &dram_ts_clk.common,
 743 +       &de_clk.common,
 744 +       &tcon0_clk.common,
 745 +       &tcon1_clk.common,
 746 +       &deinterlace_clk.common,
 747 +       &csi_misc_clk.common,
 748 +       &csi_sclk_clk.common,
 749 +       &csi_mclk_clk.common,
 750 +       &ve_clk.common,
 751 +       &ac_dig_clk.common,
 752 +       &ac_dig_4x_clk.common,
 753 +       &avs_clk.common,
 754 +       &hdmi_clk.common,
 755 +       &hdmi_ddc_clk.common,
 756 +       &mbus_clk.common,
 757 +       &dsi_dphy_clk.common,
 758 +       &gpu_clk.common,
 759 +};
 760 +
 761 +static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
 762 +       .hws    = {
 763 +               [CLK_OSC_12M]           = &osc12M_clk.hw,
 764 +               [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 765 +               [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 766 +               [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 767 +               [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 768 +               [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 769 +               [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 770 +               [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 771 +               [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 772 +               [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 773 +               [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
 774 +               [CLK_PLL_PERIPH0]       = &pll_periph0_clk.common.hw,
 775 +               [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
 776 +               [CLK_PLL_PERIPH1]       = &pll_periph1_clk.common.hw,
 777 +               [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
 778 +               [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 779 +               [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 780 +               [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
 781 +               [CLK_PLL_HSIC]          = &pll_hsic_clk.common.hw,
 782 +               [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 783 +               [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
 784 +               [CLK_CPUX]              = &cpux_clk.common.hw,
 785 +               [CLK_AXI]               = &axi_clk.common.hw,
 786 +               [CLK_AHB1]              = &ahb1_clk.common.hw,
 787 +               [CLK_APB1]              = &apb1_clk.common.hw,
 788 +               [CLK_APB2]              = &apb2_clk.common.hw,
 789 +               [CLK_AHB2]              = &ahb2_clk.common.hw,
 790 +               [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
 791 +               [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
 792 +               [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 793 +               [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 794 +               [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 795 +               [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 796 +               [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 797 +               [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 798 +               [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
 799 +               [CLK_BUS_TS]            = &bus_ts_clk.common.hw,
 800 +               [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 801 +               [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 802 +               [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 803 +               [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 804 +               [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
 805 +               [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
 806 +               [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
 807 +               [CLK_BUS_OHCI1]         = &bus_ohci1_clk.common.hw,
 808 +               [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 809 +               [CLK_BUS_TCON0]         = &bus_tcon0_clk.common.hw,
 810 +               [CLK_BUS_TCON1]         = &bus_tcon1_clk.common.hw,
 811 +               [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
 812 +               [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 813 +               [CLK_BUS_HDMI]          = &bus_hdmi_clk.common.hw,
 814 +               [CLK_BUS_DE]            = &bus_de_clk.common.hw,
 815 +               [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 816 +               [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 817 +               [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 818 +               [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 819 +               [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
 820 +               [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 821 +               [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
 822 +               [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 823 +               [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 824 +               [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
 825 +               [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 826 +               [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 827 +               [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 828 +               [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 829 +               [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 830 +               [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 831 +               [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 832 +               [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
 833 +               [CLK_BUS_SCR]           = &bus_scr_clk.common.hw,
 834 +               [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
 835 +               [CLK_THS]               = &ths_clk.common.hw,
 836 +               [CLK_NAND]              = &nand_clk.common.hw,
 837 +               [CLK_MMC0]              = &mmc0_clk.common.hw,
 838 +               [CLK_MMC1]              = &mmc1_clk.common.hw,
 839 +               [CLK_MMC2]              = &mmc2_clk.common.hw,
 840 +               [CLK_TS]                = &ts_clk.common.hw,
 841 +               [CLK_CE]                = &ce_clk.common.hw,
 842 +               [CLK_SPI0]              = &spi0_clk.common.hw,
 843 +               [CLK_SPI1]              = &spi1_clk.common.hw,
 844 +               [CLK_I2S0]              = &i2s0_clk.common.hw,
 845 +               [CLK_I2S1]              = &i2s1_clk.common.hw,
 846 +               [CLK_I2S2]              = &i2s2_clk.common.hw,
 847 +               [CLK_SPDIF]             = &spdif_clk.common.hw,
 848 +               [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 849 +               [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 850 +               [CLK_USB_HSIC]          = &usb_hsic_clk.common.hw,
 851 +               [CLK_USB_HSIC_12M]      = &usb_hsic_12m_clk.common.hw,
 852 +               [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
 853 +               [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
 854 +               [CLK_DRAM]              = &dram_clk.common.hw,
 855 +               [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 856 +               [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 857 +               [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
 858 +               [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 859 +               [CLK_DE]                = &de_clk.common.hw,
 860 +               [CLK_TCON0]             = &tcon0_clk.common.hw,
 861 +               [CLK_TCON1]             = &tcon1_clk.common.hw,
 862 +               [CLK_DEINTERLACE]       = &deinterlace_clk.common.hw,
 863 +               [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
 864 +               [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 865 +               [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 866 +               [CLK_VE]                = &ve_clk.common.hw,
 867 +               [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 868 +               [CLK_AC_DIG_4X]         = &ac_dig_4x_clk.common.hw,
 869 +               [CLK_AVS]               = &avs_clk.common.hw,
 870 +               [CLK_HDMI]              = &hdmi_clk.common.hw,
 871 +               [CLK_HDMI_DDC]          = &hdmi_ddc_clk.common.hw,
 872 +               [CLK_MBUS]              = &mbus_clk.common.hw,
 873 +               [CLK_DSI_DPHY]          = &dsi_dphy_clk.common.hw,
 874 +               [CLK_GPU]               = &gpu_clk.common.hw,
 875 +       },
 876 +       .num    = CLK_NUMBER,
 877 +};
 878 +
 879 +static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
 880 +       [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 881 +       [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 882 +       [RST_USB_HSIC]          =  { 0x0cc, BIT(2) },
 883 +
 884 +       [RST_DRAM]              =  { 0x0f4, BIT(31) },
 885 +       [RST_MBUS]              =  { 0x0fc, BIT(31) },
 886 +
 887 +       [RST_BUS_MIPI_DSI]      =  { 0x2c0, BIT(1) },
 888 +       [RST_BUS_CE]            =  { 0x2c0, BIT(5) },
 889 +       [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
 890 +       [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
 891 +       [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
 892 +       [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
 893 +       [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
 894 +       [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
 895 +       [RST_BUS_EMAC]          =  { 0x2c0, BIT(17) },
 896 +       [RST_BUS_TS]            =  { 0x2c0, BIT(18) },
 897 +       [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
 898 +       [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
 899 +       [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
 900 +       [RST_BUS_OTG]           =  { 0x2c0, BIT(23) },
 901 +       [RST_BUS_EHCI0]         =  { 0x2c0, BIT(24) },
 902 +       [RST_BUS_EHCI1]         =  { 0x2c0, BIT(25) },
 903 +       [RST_BUS_OHCI0]         =  { 0x2c0, BIT(28) },
 904 +       [RST_BUS_OHCI1]         =  { 0x2c0, BIT(29) },
 905 +
 906 +       [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
 907 +       [RST_BUS_TCON0]         =  { 0x2c4, BIT(3) },
 908 +       [RST_BUS_TCON1]         =  { 0x2c4, BIT(4) },
 909 +       [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
 910 +       [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
 911 +       [RST_BUS_HDMI0]         =  { 0x2c4, BIT(10) },
 912 +       [RST_BUS_HDMI1]         =  { 0x2c4, BIT(11) },
 913 +       [RST_BUS_DE]            =  { 0x2c4, BIT(12) },
 914 +       [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
 915 +       [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
 916 +       [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
 917 +       [RST_BUS_DBG]           =  { 0x2c4, BIT(31) },
 918 +
 919 +       [RST_BUS_LVDS]          =  { 0x2c8, BIT(0) },
 920 +
 921 +       [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
 922 +       [RST_BUS_SPDIF]         =  { 0x2d0, BIT(1) },
 923 +       [RST_BUS_THS]           =  { 0x2d0, BIT(8) },
 924 +       [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
 925 +       [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
 926 +       [RST_BUS_I2S2]          =  { 0x2d0, BIT(14) },
 927 +
 928 +       [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
 929 +       [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
 930 +       [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
 931 +       [RST_BUS_SCR]           =  { 0x2d8, BIT(5) },
 932 +       [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
 933 +       [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
 934 +       [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
 935 +       [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
 936 +       [RST_BUS_UART4]         =  { 0x2d8, BIT(20) },
 937 +};
 938 +
 939 +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
 940 +       .ccu_clks       = sun50i_a64_ccu_clks,
 941 +       .num_ccu_clks   = ARRAY_SIZE(sun50i_a64_ccu_clks),
 942 +
 943 +       .hw_clks        = &sun50i_a64_hw_clks,
 944 +
 945 +       .resets         = sun50i_a64_ccu_resets,
 946 +       .num_resets     = ARRAY_SIZE(sun50i_a64_ccu_resets),
 947 +};
 948 +
 949 +static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 950 +{
 951 +       struct resource *res;
 952 +       void __iomem *reg;
 953 +       u32 val;
 954 +
 955 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 956 +       reg = devm_ioremap_resource(&pdev->dev, res);
 957 +       if (IS_ERR(reg))
 958 +               return PTR_ERR(reg);
 959 +
 960 +       /* Force the PLL-Audio-1x divider to 4 */
 961 +       val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
 962 +       val &= ~GENMASK(19, 16);
 963 +       writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
 964 +
 965 +       writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
 966 +
 967 +       return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
 968 +}
 969 +
 970 +static const struct of_device_id sun50i_a64_ccu_ids[] = {
 971 +       { .compatible = "allwinner,sun50i-a64-ccu" },
 972 +       { }
 973 +};
 974 +
 975 +static struct platform_driver sun50i_a64_ccu_driver = {
 976 +       .probe  = sun50i_a64_ccu_probe,
 977 +       .driver = {
 978 +               .name   = "sun50i-a64-ccu",
 979 +               .of_match_table = sun50i_a64_ccu_ids,
 980 +       },
 981 +};
 982 +builtin_platform_driver(sun50i_a64_ccu_driver);
 983 --- /dev/null
 984 +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
 985 @@ -0,0 +1,72 @@
 986 +/*
 987 + * Copyright 2016 Maxime Ripard
 988 + *
 989 + * Maxime Ripard <maxime.ripard@free-electrons.com>
 990 + *
 991 + * This program is free software; you can redistribute it and/or modify
 992 + * it under the terms of the GNU General Public License as published by
 993 + * the Free Software Foundation; either version 2 of the License, or
 994 + * (at your option) any later version.
 995 + *
 996 + * This program is distributed in the hope that it will be useful,
 997 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 998 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 999 + * GNU General Public License for more details.
1000 + */
1001 +
1002 +#ifndef _CCU_SUN50I_A64_H_
1003 +#define _CCU_SUN50I_A64_H_
1004 +
1005 +#include <dt-bindings/clock/sun50i-a64-ccu.h>
1006 +#include <dt-bindings/reset/sun50i-a64-ccu.h>
1007 +
1008 +#define CLK_OSC_12M                    0
1009 +#define CLK_PLL_CPUX                   1
1010 +#define CLK_PLL_AUDIO_BASE             2
1011 +#define CLK_PLL_AUDIO                  3
1012 +#define CLK_PLL_AUDIO_2X               4
1013 +#define CLK_PLL_AUDIO_4X               5
1014 +#define CLK_PLL_AUDIO_8X               6
1015 +#define CLK_PLL_VIDEO0                 7
1016 +#define CLK_PLL_VIDEO0_2X              8
1017 +#define CLK_PLL_VE                     9
1018 +#define CLK_PLL_DDR0                   10
1019 +#define CLK_PLL_PERIPH0                        11
1020 +#define CLK_PLL_PERIPH0_2X             12
1021 +#define CLK_PLL_PERIPH1                        13
1022 +#define CLK_PLL_PERIPH1_2X             14
1023 +#define CLK_PLL_VIDEO1                 15
1024 +#define CLK_PLL_GPU                    16
1025 +#define CLK_PLL_MIPI                   17
1026 +#define CLK_PLL_HSIC                   18
1027 +#define CLK_PLL_DE                     19
1028 +#define CLK_PLL_DDR1                   20
1029 +#define CLK_CPUX                       21
1030 +#define CLK_AXI                                22
1031 +#define CLK_APB                                23
1032 +#define CLK_AHB1                       24
1033 +#define CLK_APB1                       25
1034 +#define CLK_APB2                       26
1035 +#define CLK_AHB2                       27
1036 +
1037 +/* All the bus gates are exported */
1038 +
1039 +/* The first bunch of module clocks are exported */
1040 +
1041 +#define CLK_USB_OHCI0_12M              90
1042 +
1043 +#define CLK_USB_OHCI1_12M              92
1044 +
1045 +#define CLK_DRAM                       94
1046 +
1047 +/* All the DRAM gates are exported */
1048 +
1049 +/* Some more module clocks are exported */
1050 +
1051 +#define CLK_MBUS                       112
1052 +
1053 +/* And the DSI and GPU module clock is exported */
1054 +
1055 +#define CLK_NUMBER                     (CLK_GPU + 1)
1056 +
1057 +#endif /* _CCU_SUN50I_A64_H_ */
1058 --- /dev/null
1059 +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
1060 @@ -0,0 +1,134 @@
1061 +/*
1062 + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
1063 + *
1064 + * This file is dual-licensed: you can use it either under the terms
1065 + * of the GPL or the X11 license, at your option. Note that this dual
1066 + * licensing only applies to this file, and not this project as a
1067 + * whole.
1068 + *
1069 + *  a) This file is free software; you can redistribute it and/or
1070 + *     modify it under the terms of the GNU General Public License as
1071 + *     published by the Free Software Foundation; either version 2 of the
1072 + *     License, or (at your option) any later version.
1073 + *
1074 + *     This file is distributed in the hope that it will be useful,
1075 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
1076 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1077 + *     GNU General Public License for more details.
1078 + *
1079 + * Or, alternatively,
1080 + *
1081 + *  b) Permission is hereby granted, free of charge, to any person
1082 + *     obtaining a copy of this software and associated documentation
1083 + *     files (the "Software"), to deal in the Software without
1084 + *     restriction, including without limitation the rights to use,
1085 + *     copy, modify, merge, publish, distribute, sublicense, and/or
1086 + *     sell copies of the Software, and to permit persons to whom the
1087 + *     Software is furnished to do so, subject to the following
1088 + *     conditions:
1089 + *
1090 + *     The above copyright notice and this permission notice shall be
1091 + *     included in all copies or substantial portions of the Software.
1092 + *
1093 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1094 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1095 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1096 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1097 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1098 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1099 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1100 + *     OTHER DEALINGS IN THE SOFTWARE.
1101 + */
1102 +
1103 +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
1104 +#define _DT_BINDINGS_CLK_SUN50I_A64_H_
1105 +
1106 +#define CLK_BUS_MIPI_DSI       28
1107 +#define CLK_BUS_CE             29
1108 +#define CLK_BUS_DMA            30
1109 +#define CLK_BUS_MMC0           31
1110 +#define CLK_BUS_MMC1           32
1111 +#define CLK_BUS_MMC2           33
1112 +#define CLK_BUS_NAND           34
1113 +#define CLK_BUS_DRAM           35
1114 +#define CLK_BUS_EMAC           36
1115 +#define CLK_BUS_TS             37
1116 +#define CLK_BUS_HSTIMER                38
1117 +#define CLK_BUS_SPI0           39
1118 +#define CLK_BUS_SPI1           40
1119 +#define CLK_BUS_OTG            41
1120 +#define CLK_BUS_EHCI0          42
1121 +#define CLK_BUS_EHCI1          43
1122 +#define CLK_BUS_OHCI0          44
1123 +#define CLK_BUS_OHCI1          45
1124 +#define CLK_BUS_VE             46
1125 +#define CLK_BUS_TCON0          47
1126 +#define CLK_BUS_TCON1          48
1127 +#define CLK_BUS_DEINTERLACE    49
1128 +#define CLK_BUS_CSI            50
1129 +#define CLK_BUS_HDMI           51
1130 +#define CLK_BUS_DE             52
1131 +#define CLK_BUS_GPU            53
1132 +#define CLK_BUS_MSGBOX         54
1133 +#define CLK_BUS_SPINLOCK       55
1134 +#define CLK_BUS_CODEC          56
1135 +#define CLK_BUS_SPDIF          57
1136 +#define CLK_BUS_PIO            58
1137 +#define CLK_BUS_THS            59
1138 +#define CLK_BUS_I2S0           60
1139 +#define CLK_BUS_I2S1           61
1140 +#define CLK_BUS_I2S2           62
1141 +#define CLK_BUS_I2C0           63
1142 +#define CLK_BUS_I2C1           64
1143 +#define CLK_BUS_I2C2           65
1144 +#define CLK_BUS_SCR            66
1145 +#define CLK_BUS_UART0          67
1146 +#define CLK_BUS_UART1          68
1147 +#define CLK_BUS_UART2          69
1148 +#define CLK_BUS_UART3          70
1149 +#define CLK_BUS_UART4          71
1150 +#define CLK_BUS_DBG            72
1151 +#define CLK_THS                        73
1152 +#define CLK_NAND               74
1153 +#define CLK_MMC0               75
1154 +#define CLK_MMC1               76
1155 +#define CLK_MMC2               77
1156 +#define CLK_TS                 78
1157 +#define CLK_CE                 79
1158 +#define CLK_SPI0               80
1159 +#define CLK_SPI1               81
1160 +#define CLK_I2S0               82
1161 +#define CLK_I2S1               83
1162 +#define CLK_I2S2               84
1163 +#define CLK_SPDIF              85
1164 +#define CLK_USB_PHY0           86
1165 +#define CLK_USB_PHY1           87
1166 +#define CLK_USB_HSIC           88
1167 +#define CLK_USB_HSIC_12M       89
1168 +
1169 +#define CLK_USB_OHCI0          91
1170 +
1171 +#define CLK_USB_OHCI1          93
1172 +
1173 +#define CLK_DRAM_VE            95
1174 +#define CLK_DRAM_CSI           96
1175 +#define CLK_DRAM_DEINTERLACE   97
1176 +#define CLK_DRAM_TS            98
1177 +#define CLK_DE                 99
1178 +#define CLK_TCON0              100
1179 +#define CLK_TCON1              101
1180 +#define CLK_DEINTERLACE                102
1181 +#define CLK_CSI_MISC           103
1182 +#define CLK_CSI_SCLK           104
1183 +#define CLK_CSI_MCLK           105
1184 +#define CLK_VE                 106
1185 +#define CLK_AC_DIG             107
1186 +#define CLK_AC_DIG_4X          108
1187 +#define CLK_AVS                        109
1188 +#define CLK_HDMI               110
1189 +#define CLK_HDMI_DDC           111
1190 +
1191 +#define CLK_DSI_DPHY           113
1192 +#define CLK_GPU                        114
1193 +
1194 +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
1195 --- /dev/null
1196 +++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
1197 @@ -0,0 +1,98 @@
1198 +/*
1199 + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
1200 + *
1201 + * This file is dual-licensed: you can use it either under the terms
1202 + * of the GPL or the X11 license, at your option. Note that this dual
1203 + * licensing only applies to this file, and not this project as a
1204 + * whole.
1205 + *
1206 + *  a) This file is free software; you can redistribute it and/or
1207 + *     modify it under the terms of the GNU General Public License as
1208 + *     published by the Free Software Foundation; either version 2 of the
1209 + *     License, or (at your option) any later version.
1210 + *
1211 + *     This file is distributed in the hope that it will be useful,
1212 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
1213 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1214 + *     GNU General Public License for more details.
1215 + *
1216 + * Or, alternatively,
1217 + *
1218 + *  b) Permission is hereby granted, free of charge, to any person
1219 + *     obtaining a copy of this software and associated documentation
1220 + *     files (the "Software"), to deal in the Software without
1221 + *     restriction, including without limitation the rights to use,
1222 + *     copy, modify, merge, publish, distribute, sublicense, and/or
1223 + *     sell copies of the Software, and to permit persons to whom the
1224 + *     Software is furnished to do so, subject to the following
1225 + *     conditions:
1226 + *
1227 + *     The above copyright notice and this permission notice shall be
1228 + *     included in all copies or substantial portions of the Software.
1229 + *
1230 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1231 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1232 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1233 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1234 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1235 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1236 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1237 + *     OTHER DEALINGS IN THE SOFTWARE.
1238 + */
1239 +
1240 +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
1241 +#define _DT_BINDINGS_RST_SUN50I_A64_H_
1242 +
1243 +#define RST_USB_PHY0           0
1244 +#define RST_USB_PHY1           1
1245 +#define RST_USB_HSIC           2
1246 +#define RST_DRAM               3
1247 +#define RST_MBUS               4
1248 +#define RST_BUS_MIPI_DSI       5
1249 +#define RST_BUS_CE             6
1250 +#define RST_BUS_DMA            7
1251 +#define RST_BUS_MMC0           8
1252 +#define RST_BUS_MMC1           9
1253 +#define RST_BUS_MMC2           10
1254 +#define RST_BUS_NAND           11
1255 +#define RST_BUS_DRAM           12
1256 +#define RST_BUS_EMAC           13
1257 +#define RST_BUS_TS             14
1258 +#define RST_BUS_HSTIMER                15
1259 +#define RST_BUS_SPI0           16
1260 +#define RST_BUS_SPI1           17
1261 +#define RST_BUS_OTG            18
1262 +#define RST_BUS_EHCI0          19
1263 +#define RST_BUS_EHCI1          20
1264 +#define RST_BUS_OHCI0          21
1265 +#define RST_BUS_OHCI1          22
1266 +#define RST_BUS_VE             23
1267 +#define RST_BUS_TCON0          24
1268 +#define RST_BUS_TCON1          25
1269 +#define RST_BUS_DEINTERLACE    26
1270 +#define RST_BUS_CSI            27
1271 +#define RST_BUS_HDMI0          28
1272 +#define RST_BUS_HDMI1          29
1273 +#define RST_BUS_DE             30
1274 +#define RST_BUS_GPU            31
1275 +#define RST_BUS_MSGBOX         32
1276 +#define RST_BUS_SPINLOCK       33
1277 +#define RST_BUS_DBG            34
1278 +#define RST_BUS_LVDS           35
1279 +#define RST_BUS_CODEC          36
1280 +#define RST_BUS_SPDIF          37
1281 +#define RST_BUS_THS            38
1282 +#define RST_BUS_I2S0           39
1283 +#define RST_BUS_I2S1           40
1284 +#define RST_BUS_I2S2           41
1285 +#define RST_BUS_I2C0           42
1286 +#define RST_BUS_I2C1           43
1287 +#define RST_BUS_I2C2           44
1288 +#define RST_BUS_SCR            45
1289 +#define RST_BUS_UART0          46
1290 +#define RST_BUS_UART1          47
1291 +#define RST_BUS_UART2          48
1292 +#define RST_BUS_UART3          49
1293 +#define RST_BUS_UART4          50
1294 +
1295 +#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */