First git repo commit for the libreCMC project
[librecmc/librecmc.git] / target / linux / sunxi / patches-4.4 / 133-dt-sun8i-add-usbphy-usbhost-ctrl-nodes.patch
1 From 5971a2f283d21eab36d7de24d35301f081f83418 Mon Sep 17 00:00:00 2001
2 From: Reinder de Haan <patchesrdh@mveas.com>
3 Date: Tue, 3 Nov 2015 15:14:20 +0100
4 Subject: [PATCH] ARM: dts: sun8i: Add usbphy and usb host controller nodes
5
6 Add nodes describing the H3's usbphy and usb host controller nodes.
7
8 Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
9 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
10 ---
11  arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++
12  1 file changed, 101 insertions(+)
13
14 --- a/arch/arm/boot/dts/sun8i-h3.dtsi
15 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
16 @@ -362,6 +362,107 @@
17                         #size-cells = <0>;
18                 };
19  
20 +               usbphy: phy@01c19400 {
21 +                       compatible = "allwinner,sun8i-h3-usb-phy";
22 +                       reg = <0x01c19400 0x2c>,
23 +                             <0x01c1a800 0x4>,
24 +                             <0x01c1b800 0x4>,
25 +                             <0x01c1c800 0x4>,
26 +                             <0x01c1d800 0x4>;
27 +                       reg-names = "phy_ctrl",
28 +                                   "pmu0",
29 +                                   "pmu1",
30 +                                   "pmu2",
31 +                                   "pmu3";
32 +                       clocks = <&usb_clk 8>,
33 +                                <&usb_clk 9>,
34 +                                <&usb_clk 10>,
35 +                                <&usb_clk 11>;
36 +                       clock-names = "usb0_phy",
37 +                                     "usb1_phy",
38 +                                     "usb2_phy",
39 +                                     "usb3_phy";
40 +                       resets = <&usb_clk 0>,
41 +                                <&usb_clk 1>,
42 +                                <&usb_clk 2>,
43 +                                <&usb_clk 3>;
44 +                       reset-names = "usb0_reset",
45 +                                     "usb1_reset",
46 +                                     "usb2_reset",
47 +                                     "usb3_reset";
48 +                       status = "disabled";
49 +                       #phy-cells = <1>;
50 +               };
51 +
52 +               ehci1: usb@01c1b000 {
53 +                       compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
54 +                       reg = <0x01c1b000 0x100>;
55 +                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
56 +                       clocks = <&bus_gates 25>, <&bus_gates 29>;
57 +                       resets = <&ahb_rst 25>, <&ahb_rst 29>;
58 +                       phys = <&usbphy 1>;
59 +                       phy-names = "usb";
60 +                       status = "disabled";
61 +               };
62 +
63 +               ohci1: usb@01c1b400 {
64 +                       compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
65 +                       reg = <0x01c1b400 0x100>;
66 +                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
67 +                       clocks = <&bus_gates 29>, <&bus_gates 25>,
68 +                                <&usb_clk 17>;
69 +                       resets = <&ahb_rst 29>, <&ahb_rst 25>;
70 +                       phys = <&usbphy 1>;
71 +                       phy-names = "usb";
72 +                       status = "disabled";
73 +               };
74 +
75 +               ehci2: usb@01c1c000 {
76 +                       compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
77 +                       reg = <0x01c1c000 0x100>;
78 +                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
79 +                       clocks = <&bus_gates 26>, <&bus_gates 30>;
80 +                       resets = <&ahb_rst 26>, <&ahb_rst 30>;
81 +                       phys = <&usbphy 2>;
82 +                       phy-names = "usb";
83 +                       status = "disabled";
84 +               };
85 +
86 +               ohci2: usb@01c1c400 {
87 +                       compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
88 +                       reg = <0x01c1c400 0x100>;
89 +                       interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
90 +                       clocks = <&bus_gates 30>, <&bus_gates 26>,
91 +                                <&usb_clk 18>;
92 +                       resets = <&ahb_rst 30>, <&ahb_rst 26>;
93 +                       phys = <&usbphy 2>;
94 +                       phy-names = "usb";
95 +                       status = "disabled";
96 +               };
97 +
98 +               ehci3: usb@01c1d000 {
99 +                       compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
100 +                       reg = <0x01c1d000 0x100>;
101 +                       interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
102 +                       clocks = <&bus_gates 27>, <&bus_gates 31>;
103 +                       resets = <&ahb_rst 27>, <&ahb_rst 31>;
104 +                       phys = <&usbphy 3>;
105 +                       phy-names = "usb";
106 +                       status = "disabled";
107 +               };
108 +
109 +               ohci3: usb@01c1d400 {
110 +                       compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
111 +                       reg = <0x01c1d400 0x100>;
112 +                       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
113 +                       clocks = <&bus_gates 31>, <&bus_gates 27>,
114 +                                <&usb_clk 19>;
115 +                       resets = <&ahb_rst 31>, <&ahb_rst 27>;
116 +                       phys = <&usbphy 3>;
117 +                       phy-names = "usb";
118 +                       status = "disabled";
119 +               };
120 +
121                 pio: pinctrl@01c20800 {
122                         compatible = "allwinner,sun8i-h3-pinctrl";
123                         reg = <0x01c20800 0x400>;